1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x0 0x70000000 0x0 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x70000000 0x800000>; 15 16 atf-sram@0 { 17 reg = <0x0 0x20000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 30 31 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: gic-its@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 smmu0: smmu@36600000 { 44 compatible = "arm,smmu-v3"; 45 reg = <0x0 0x36600000 0x0 0x100000>; 46 power-domains = <&k3_pds 229 TI_SCI_PD_EXCLUSIVE>; 47 interrupt-parent = <&gic500>; 48 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 49 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 50 interrupt-names = "eventq", "gerror"; 51 #iommu-cells = <1>; 52 }; 53 54 main_gpio_intr: interrupt-controller0 { 55 compatible = "ti,sci-intr"; 56 ti,intr-trigger-type = <1>; 57 interrupt-controller; 58 interrupt-parent = <&gic500>; 59 #interrupt-cells = <2>; 60 ti,sci = <&dmsc>; 61 ti,sci-dst-id = <14>; 62 ti,sci-rm-range-girq = <0x1>; 63 }; 64 65 cbass_main_navss: interconnect0 { 66 compatible = "simple-bus"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 ranges; 70 71 main_navss_intr: interrupt-controller1 { 72 compatible = "ti,sci-intr"; 73 ti,intr-trigger-type = <4>; 74 interrupt-controller; 75 interrupt-parent = <&gic500>; 76 #interrupt-cells = <2>; 77 ti,sci = <&dmsc>; 78 ti,sci-dst-id = <14>; 79 ti,sci-rm-range-girq = <0>, <2>; 80 }; 81 82 main_udmass_inta: interrupt-controller@33d00000 { 83 compatible = "ti,sci-inta"; 84 reg = <0x0 0x33d00000 0x0 0x100000>; 85 interrupt-controller; 86 interrupt-parent = <&main_navss_intr>; 87 msi-controller; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <209>; 90 ti,sci-rm-range-vint = <0xa>; 91 ti,sci-rm-range-global-event = <0xd>; 92 }; 93 94 hwspinlock: spinlock@30e00000 { 95 compatible = "ti,am654-hwspinlock"; 96 reg = <0x00 0x30e00000 0x00 0x1000>; 97 #hwlock-cells = <1>; 98 }; 99 }; 100 101 secure_proxy_main: mailbox@32c00000 { 102 compatible = "ti,am654-secure-proxy"; 103 #mbox-cells = <1>; 104 reg-names = "target_data", "rt", "scfg"; 105 reg = <0x00 0x32c00000 0x00 0x100000>, 106 <0x00 0x32400000 0x00 0x100000>, 107 <0x00 0x32800000 0x00 0x100000>; 108 interrupt-names = "rx_011"; 109 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 main_pmx0: pinmux@11c000 { 113 compatible = "pinctrl-single"; 114 /* Proxy 0 addressing */ 115 reg = <0x0 0x11c000 0x0 0x2b4>; 116 #pinctrl-cells = <1>; 117 pinctrl-single,register-width = <32>; 118 pinctrl-single,function-mask = <0xffffffff>; 119 }; 120 121 main_uart0: serial@2800000 { 122 compatible = "ti,j721e-uart", "ti,am654-uart"; 123 reg = <0x00 0x02800000 0x00 0x100>; 124 reg-shift = <2>; 125 reg-io-width = <4>; 126 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 127 clock-frequency = <48000000>; 128 current-speed = <115200>; 129 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 130 clocks = <&k3_clks 146 0>; 131 clock-names = "fclk"; 132 }; 133 134 main_uart1: serial@2810000 { 135 compatible = "ti,j721e-uart", "ti,am654-uart"; 136 reg = <0x00 0x02810000 0x00 0x100>; 137 reg-shift = <2>; 138 reg-io-width = <4>; 139 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 140 clock-frequency = <48000000>; 141 current-speed = <115200>; 142 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 143 clocks = <&k3_clks 278 0>; 144 clock-names = "fclk"; 145 }; 146 147 main_uart2: serial@2820000 { 148 compatible = "ti,j721e-uart", "ti,am654-uart"; 149 reg = <0x00 0x02820000 0x00 0x100>; 150 reg-shift = <2>; 151 reg-io-width = <4>; 152 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 153 clock-frequency = <48000000>; 154 current-speed = <115200>; 155 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 156 clocks = <&k3_clks 279 0>; 157 clock-names = "fclk"; 158 }; 159 160 main_uart3: serial@2830000 { 161 compatible = "ti,j721e-uart", "ti,am654-uart"; 162 reg = <0x00 0x02830000 0x00 0x100>; 163 reg-shift = <2>; 164 reg-io-width = <4>; 165 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 166 clock-frequency = <48000000>; 167 current-speed = <115200>; 168 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 169 clocks = <&k3_clks 280 0>; 170 clock-names = "fclk"; 171 }; 172 173 main_uart4: serial@2840000 { 174 compatible = "ti,j721e-uart", "ti,am654-uart"; 175 reg = <0x00 0x02840000 0x00 0x100>; 176 reg-shift = <2>; 177 reg-io-width = <4>; 178 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 179 clock-frequency = <48000000>; 180 current-speed = <115200>; 181 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 182 clocks = <&k3_clks 281 0>; 183 clock-names = "fclk"; 184 }; 185 186 main_uart5: serial@2850000 { 187 compatible = "ti,j721e-uart", "ti,am654-uart"; 188 reg = <0x00 0x02850000 0x00 0x100>; 189 reg-shift = <2>; 190 reg-io-width = <4>; 191 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 192 clock-frequency = <48000000>; 193 current-speed = <115200>; 194 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 195 clocks = <&k3_clks 282 0>; 196 clock-names = "fclk"; 197 }; 198 199 main_uart6: serial@2860000 { 200 compatible = "ti,j721e-uart", "ti,am654-uart"; 201 reg = <0x00 0x02860000 0x00 0x100>; 202 reg-shift = <2>; 203 reg-io-width = <4>; 204 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 205 clock-frequency = <48000000>; 206 current-speed = <115200>; 207 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 208 clocks = <&k3_clks 283 0>; 209 clock-names = "fclk"; 210 }; 211 212 main_uart7: serial@2870000 { 213 compatible = "ti,j721e-uart", "ti,am654-uart"; 214 reg = <0x00 0x02870000 0x00 0x100>; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 218 clock-frequency = <48000000>; 219 current-speed = <115200>; 220 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 221 clocks = <&k3_clks 284 0>; 222 clock-names = "fclk"; 223 }; 224 225 main_uart8: serial@2880000 { 226 compatible = "ti,j721e-uart", "ti,am654-uart"; 227 reg = <0x00 0x02880000 0x00 0x100>; 228 reg-shift = <2>; 229 reg-io-width = <4>; 230 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 231 clock-frequency = <48000000>; 232 current-speed = <115200>; 233 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 234 clocks = <&k3_clks 285 0>; 235 clock-names = "fclk"; 236 }; 237 238 main_uart9: serial@2890000 { 239 compatible = "ti,j721e-uart", "ti,am654-uart"; 240 reg = <0x00 0x02890000 0x00 0x100>; 241 reg-shift = <2>; 242 reg-io-width = <4>; 243 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 244 clock-frequency = <48000000>; 245 current-speed = <115200>; 246 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 247 clocks = <&k3_clks 286 0>; 248 clock-names = "fclk"; 249 }; 250 251 main_gpio0: gpio@600000 { 252 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 253 reg = <0x0 0x00600000 0x0 0x100>; 254 gpio-controller; 255 #gpio-cells = <2>; 256 interrupt-parent = <&main_gpio_intr>; 257 interrupts = <105 0>, <105 1>, <105 2>, <105 3>, 258 <105 4>, <105 5>, <105 6>, <105 7>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 ti,ngpio = <128>; 262 ti,davinci-gpio-unbanked = <0>; 263 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 264 clocks = <&k3_clks 105 0>; 265 clock-names = "gpio"; 266 }; 267 268 main_gpio1: gpio@601000 { 269 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 270 reg = <0x0 0x00601000 0x0 0x100>; 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-parent = <&main_gpio_intr>; 274 interrupts = <106 0>, <106 1>, <106 2>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 ti,ngpio = <36>; 278 ti,davinci-gpio-unbanked = <0>; 279 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 280 clocks = <&k3_clks 106 0>; 281 clock-names = "gpio"; 282 }; 283 284 main_gpio2: gpio@610000 { 285 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 286 reg = <0x0 0x00610000 0x0 0x100>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 interrupt-parent = <&main_gpio_intr>; 290 interrupts = <107 0>, <107 1>, <107 2>, <107 3>, 291 <107 4>, <107 5>, <107 6>, <107 7>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 ti,ngpio = <128>; 295 ti,davinci-gpio-unbanked = <0>; 296 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 297 clocks = <&k3_clks 107 0>; 298 clock-names = "gpio"; 299 }; 300 301 main_gpio3: gpio@611000 { 302 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 303 reg = <0x0 0x00611000 0x0 0x100>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupt-parent = <&main_gpio_intr>; 307 interrupts = <108 0>, <108 1>, <108 2>; 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 ti,ngpio = <36>; 311 ti,davinci-gpio-unbanked = <0>; 312 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 313 clocks = <&k3_clks 108 0>; 314 clock-names = "gpio"; 315 }; 316 317 main_gpio4: gpio@620000 { 318 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 319 reg = <0x0 0x00620000 0x0 0x100>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-parent = <&main_gpio_intr>; 323 interrupts = <109 0>, <109 1>, <109 2>, <109 3>, 324 <109 4>, <109 5>, <109 6>, <109 7>; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 ti,ngpio = <128>; 328 ti,davinci-gpio-unbanked = <0>; 329 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 330 clocks = <&k3_clks 109 0>; 331 clock-names = "gpio"; 332 }; 333 334 main_gpio5: gpio@621000 { 335 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 336 reg = <0x0 0x00621000 0x0 0x100>; 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-parent = <&main_gpio_intr>; 340 interrupts = <110 0>, <110 1>, <110 2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 ti,ngpio = <36>; 344 ti,davinci-gpio-unbanked = <0>; 345 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 346 clocks = <&k3_clks 110 0>; 347 clock-names = "gpio"; 348 }; 349 350 main_gpio6: gpio@630000 { 351 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 352 reg = <0x0 0x00630000 0x0 0x100>; 353 gpio-controller; 354 #gpio-cells = <2>; 355 interrupt-parent = <&main_gpio_intr>; 356 interrupts = <111 0>, <111 1>, <111 2>, <111 3>, 357 <111 4>, <111 5>, <111 6>, <111 7>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 ti,ngpio = <128>; 361 ti,davinci-gpio-unbanked = <0>; 362 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 111 0>; 364 clock-names = "gpio"; 365 }; 366 367 main_gpio7: gpio@631000 { 368 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 369 reg = <0x0 0x00631000 0x0 0x100>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-parent = <&main_gpio_intr>; 373 interrupts = <112 0>, <112 1>, <112 2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 ti,ngpio = <36>; 377 ti,davinci-gpio-unbanked = <0>; 378 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 379 clocks = <&k3_clks 112 0>; 380 clock-names = "gpio"; 381 }; 382}; 383