| /arch/powerpc/lib/ |
| D | mem_64.S | 40 mr r6,r3
45 stb r4,0(r6)
46 addi r6,r6,1
48 sth r4,0(r6)
49 addi r6,r6,2
51 stw r4,0(r6)
52 addi r6,r6,4
58 4: std r4,0(r6)
59 std r4,8(r6)
60 std r4,16(r6)
[all …]
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| D | checksum_64.S | 26 srdi. r6,r4,3 /* less than 8 bytes? */
35 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
39 sub r6,r7,r6
40 mtctr r6
43 lhz r6,0(r3) /* align to doubleword */
46 adde r0,r0,r6
55 srdi. r6,r4,7
58 srdi r6,r4,6
59 subi r6,r6,1
60 mtctr r6
[all …]
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| D | copy_32.S | 20 stw r7,4(r6); \
21 stw r8,8(r6); \
22 stw r9,12(r6); \
23 stwu r10,16(r6)
35 stw r7,4(r6); \
37 stw r8,8(r6); \
39 stw r9,12(r6); \
41 stwu r10,16(r6)
71 addi r6, r3, -4
75 1: stwu r4, 4(r6)
[all …]
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| D | string_32.S | 35 subf r6, r0, r10
37 clrlwi r7, r6, 32 - LG_CACHELINE_BYTES
46 4: stwu r3, 4(r6)
50 10: dcbz r7, r6
51 addi r6, r6, CACHELINE_BYTES
59 1: stwu r3, 4(r6)
64 addi r6, r6, 3
65 8: stbu r3, 1(r6)
72 addi r6, r10, -1
73 9: stbu r3, 1(r6)
[all …]
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| D | ldstfp.S | 22 mfmsr r6
23 ori r7, r6, MSR_FP
39 2: MTMSRD(r6)
46 mfmsr r6
47 ori r7, r6, MSR_FP
63 2: MTMSRD(r6)
71 mfmsr r6
72 oris r7, r6, MSR_VEC@h
88 2: MTMSRD(r6)
95 mfmsr r6
[all …]
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| /arch/powerpc/kernel/ |
| D | fsl_booke_entry_mapping.S | 5 invstr: mflr r6 /* Make it accessible */
12 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
26 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
34 tlbsx 0,r6 /* Fall through, we had to match */
48 li r6,0 /* Set Entry counter to 0 */
50 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
55 cmpw r3,r6
60 skpinv: addi r6,r6,1 /* Increment */
61 cmpw r6,r9 /* Are we done? */
65 li r6,0x04
[all …]
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| D | vector.S | 81 addi r6,r5,THREAD_VRSTATE
85 lvx v0,r10,r6
87 REST_32VRS(0,r4,r6)
131 li r6,1
132 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
214 li r6,0
215 1: lfsx fr0,r4,r6
216 lfsx fr1,r5,r6
218 stfsx fr0,r3,r6
219 addi r6,r6,4
[all …]
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| /arch/arm/mm/ |
| D | abort-lv4t.S | 67 and r6, r8, r7
69 add r6, r6, r9, lsr #1
71 add r6, r6, r9, lsr #2
73 add r6, r6, r9, lsr #3
74 add r6, r6, r6, lsr #8
75 add r6, r6, r6, lsr #4
76 and r6, r6, #15 @ r6 = no. of registers to transfer.
80 subne r7, r7, r6, lsl #2 @ Undo increment
81 addeq r7, r7, r6, lsl #2 @ Undo decrement
93 andne r6, r8, #0xf00 @ { immediate high nibble
[all …]
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| /arch/arm/kernel/ |
| D | head-nommu.S | 272 ldr r6, =(_end) @ Cover whole kernel
273 sub r6, r6, r5 @ Minimum size of region to map
274 clz r6, r6 @ Region size must be 2^N...
275 rsb r6, r6, #31 @ ...so round up region size
276 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
277 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
294 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
296 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
305 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled
307 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
[all …]
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| /arch/arm/mach-imx/ |
| D | suspend-imx6.S | 79 mov r6, #0x0
80 str r6, [r11, #L2X0_CACHE_SYNC]
82 ldr r6, [r11, #L2X0_CACHE_SYNC]
83 ands r6, r6, #0x1
97 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
104 subs r6, r6, #0x1
116 ldr r6, [r11, r7]
117 orr r6, r6, #(1 << 31)
118 str r6, [r11, r7]
120 ldr r6, [r11, r7]
[all …]
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| /arch/csky/kernel/ |
| D | head.S | 13 lrw r6, init_thread_union + THREAD_SIZE
14 mov sp, r6
25 lrw r6, secondary_msa1
26 ld.w r6, (r6, 0)
27 mtcr r6, cr<31, 15>
30 lrw r6, secondary_stack
31 ld.w r6, (r6, 0)
32 mov sp, r6
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| /arch/powerpc/crypto/ |
| D | aes-spe-keys.S | 30 xor r6,r6,r6; \
77 LOAD_KEY(r6,r4,4)
81 stw r6,4(r3)
93 xor r6,r6,r5
94 xor r7,r7,r6
97 stw r6,4(r3)
119 LOAD_KEY(r6,r4,4)
125 stw r6,4(r3)
139 xor r6,r6,r5
140 xor r7,r7,r6
[all …]
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| /arch/arm/lib/ |
| D | io-readsb.S | 29 .Linsb_aligned: stmfd sp!, {r4 - r6, lr}
38 ldrb r6, [r0]
43 orr r3, r3, r6, put_byte_3
44 ldrb r6, [r0]
49 orr r4, r4, r6, put_byte_2
50 ldrb r6, [r0]
55 orr r5, r5, r6, put_byte_1
56 ldrb r6, [r0]
61 mov r6, r6, put_byte_0
62 orr r6, r6, ip, put_byte_1
[all …]
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| /arch/hexagon/lib/ |
| D | memset.S | 27 r6 = #8 define
35 r9 = sub(r6, r7) /* bytes until double alignment */
57 r6 = #1 define
70 r6 = #2 define
83 r6 = #4 define
103 r6 = #8 define
123 r6 = #4 define
158 r6 = r0 define
183 r6 = add(r0, #1) define
190 p0 = tstbit(r6,#1)
[all …]
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| /arch/powerpc/mm/book3s32/ |
| D | hash_low.S | 54 11: lwz r6,0(r8)
55 cmpwi 0,r6,0
57 10: lwarx r6,0,r8
58 cmpwi 0,r6,0
113 lwarx r6,0,r8 /* get linux-style pte, flag word */
114 andc. r5,r3,r6 /* check access & ~permission */
120 or r5,r0,r6 /* set accessed/dirty bits */
123 subf r10,r6,r8 /* create false data dependency */
125 lwzx r10,r6,r10 /* Get upper PTE word */
203 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
[all …]
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| /arch/powerpc/platforms/83xx/ |
| D | suspend-asm.S | 64 lwz r6, 4(r4)
67 stw r6, SS_MEMSAVE+4(r3)
70 mfspr r6, SPRN_HID1
74 stw r6, SS_HID+4(r3)
79 mfspr r6, SPRN_IBCR
86 stw r6, SS_IBCR(r3)
93 mfspr r6, SPRN_SPRG2
99 stw r6, SS_SPRG+8(r3)
105 mfspr r6, SPRN_SPRG6
110 stw r6, SS_SPRG+24(r3)
[all …]
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| /arch/powerpc/mm/nohash/ |
| D | tlb_low.S | 45 mfspr r6,SPRN_PID
49 mtspr SPRN_PID,r6
92 tlbsx. r6,0,r3
102 tlbwe r6,r6,PPC44x_TLB_PAGEID
108 oris r7,r6,0x8000 /* specify way explicitly */
155 li r6,0 /* Default entry value 0 */
163 tlbre r6,r5,0 /* Read entry */
165 andi. r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
168 rlwinm r6,r6,0,21,19 /* Clear V */
169 tlbwe r6,r7,0 /* Write it */
[all …]
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| /arch/sh/lib/ |
| D | memset.S | 17 tst r6,r6
19 add r6,r4
21 cmp/gt r6,r0
27 sub r0,r6
39 mov r6,r0
41 shlr r0 ! r0 = r6 >> 3
49 and r0,r6
50 tst r6,r6
54 dt r6
|
| D | checksum.S | 62 addc r0, r6 ! t=0 from previous tst
63 mov r6, r0
64 shll8 r6
67 or r0, r6
82 addc r0, r6
84 add #1, r6
150 addc r0, r6
158 addc r0, r6
160 addc r0, r6
166 mov r6, r0
[all …]
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| /arch/powerpc/boot/ |
| D | string.S | 26 addi r6,r3,-1
30 stbu r0,1(r6)
97 addi r6,r3,-4
100 stwu r4,4(r6)
102 andi. r0,r6,3
104 subf r6,r0,r6
108 1: stwu r4,4(r6)
114 addi r6,r6,3
115 8: stbu r4,1(r6)
128 addi r6,r3,-4
[all …]
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| D | div64.S | 16 lwz r5,0(r3) # get the dividend into r5/r6
17 lwz r6,4(r3)
33 andc r11,r6,r10 # ever be too large, only too small)
42 subfc r6,r10,r6 # take the product from the divisor,
46 3: cmplw r6,r4
48 divwu r0,r6,r4 # perform the remaining 32-bit division
51 subf r6,r10,r6
54 mr r3,r6 # return the remainder in r3
73 subfic r6,r5,32
76 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
[all …]
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| /arch/csky/abiv2/inc/abi/ |
| D | entry.h | 180 lrw r6, DEFAULT_PSR_VALUE
181 mtcr r6, psr
185 movi r6, 7
186 lsli r6, 16
187 addi r6, (1<<4) | 3
188 mtcr r6, cr17
191 bgeni r6, 26
192 mtcr r6, cr<8, 15> /* Set MCIR */
195 mfcr r6, cr18
196 btsti r6, 0
[all …]
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| /arch/microblaze/kernel/ |
| D | hw_exception_handler.S | 91 lwi r6, r1, PT_R6; \
337 swi r6, r1, PT_R6
366 addk r6, r5, r5; /* << 1 */
367 addk r6, r6, r6; /* << 2 */
374 lwi r5, r6, TOPHYS(exception_debug_table)
376 swi r5, r6, TOPHYS(exception_debug_table)
380 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
381 bra r6
388 mfs r6, rmsr;
390 swi r6, r1, 0; /* RMSR_OFFSET */
[all …]
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| /arch/powerpc/kernel/vdso64/ |
| D | cacheflush.S | 34 andc r6,r11,r5 /* round low to line bdy */
35 subf r8,r6,r4 /* compute length */
42 1: dcbst 0,r6
43 add r6,r6,r7
51 andc r6,r11,r5 /* round low to line bdy */
52 subf r8,r6,r4 /* compute length */
59 2: icbi 0,r6
60 add r6,r6,r7
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| /arch/powerpc/kernel/vdso32/ |
| D | cacheflush.S | 34 andc r6,r11,r5 /* round low to line bdy */
35 subf r8,r6,r4 /* compute length */
42 1: dcbst 0,r6
43 add r6,r6,r7
51 andc r6,r11,r5 /* round low to line bdy */
52 subf r8,r6,r4 /* compute length */
59 2: icbi 0,r6
60 add r6,r6,r7
|