| /arch/sh/drivers/pci/ |
| D | pci-sh7780.c | 100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
105 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
113 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
119 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
132 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
177 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
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| D | pci-sh4.h | 173 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
179 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
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| D | pcie-sh7786.h | 568 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
574 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
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| D | pci-sh7751.c | 83 chan->reg_base = 0xfe200000; in sh7751_pci_init()
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| D | pcie-sh7786.c | 119 .reg_base = start, \
238 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()
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| /arch/powerpc/boot/ |
| D | uartlite.c | 29 static void * reg_base; variable
34 out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX); in uartlite_open()
42 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_putc()
43 out_be32(reg_base + ULITE_TX, c); in uartlite_putc()
50 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_getc()
51 return in_be32(reg_base + ULITE_RX); in uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_tstc()
65 n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base)); in uartlite_console_init()
66 if (n != sizeof(reg_base)) { in uartlite_console_init()
70 reg_base = (void *)reg_phys; in uartlite_console_init()
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| D | ns16550.c | 31 static unsigned char *reg_base; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
43 out_8(reg_base, c); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
49 return in_8(reg_base); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
62 if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) { in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
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| D | virtex.c | 27 unsigned char *reg_base; in virtex_ns16550_console_init() local
32 if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) in virtex_ns16550_console_init()
37 reg_base += reg_offset; in virtex_ns16550_console_init()
55 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
58 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); in virtex_ns16550_console_init()
59 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); in virtex_ns16550_console_init()
62 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); in virtex_ns16550_console_init()
68 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
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| /arch/arm/mach-rockchip/ |
| D | rockchip.c | 29 void __iomem *reg_base; in rockchip_timer_init() local
36 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
37 if (reg_base) { in rockchip_timer_init()
38 writel(0, reg_base + 0x30); in rockchip_timer_init()
39 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
40 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
41 writel(1, reg_base + 0x30); in rockchip_timer_init()
43 iounmap(reg_base); in rockchip_timer_init()
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| /arch/sparc/kernel/ |
| D | sbus.c | 213 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq() local
223 imap += reg_base; in sbus_build_irq()
238 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
241 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
244 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
248 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
275 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler() local
280 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
281 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
349 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler() local
[all …]
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| D | prom_irqtrans.c | 652 unsigned long reg_base = (unsigned long) _data; in sbus_of_build_irq() local
673 imap += reg_base; in sbus_of_build_irq()
686 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_of_build_irq()
689 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_of_build_irq()
692 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_of_build_irq()
696 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_of_build_irq()
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| /arch/powerpc/platforms/powernv/ |
| D | opal-xscom.c | 94 u64 reg, reg_base, reg_cnt, val; in scom_debug_read() local
99 reg_base = off >> 3; in scom_debug_read()
103 rc = opal_scom_read(ent->chip, reg_base, reg, &val); in scom_debug_read()
125 u64 reg, reg_base, reg_cnt, val; in scom_debug_write() local
130 reg_base = off >> 3; in scom_debug_write()
136 rc = opal_scom_write(ent->chip, reg_base, reg, val); in scom_debug_write()
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| /arch/arm/mach-s3c24xx/ |
| D | common.h | 114 void __iomem *reg_base);
118 unsigned long ext_f, void __iomem *reg_base);
123 void __iomem *reg_base);
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| /arch/arm/mach-s3c64xx/ |
| D | common.h | 26 unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
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| /arch/x86/platform/intel-quark/ |
| D | imr.c | 41 int reg_base; member
110 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; in imr_read()
142 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; in imr_write()
587 idev->reg_base = QUARK_X1000_IMR_REGBASE; in imr_init()
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| /arch/sh/include/asm/ |
| D | pci.h | 29 unsigned long reg_base; member
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| /arch/powerpc/kvm/ |
| D | mpic.c | 198 gpa_t reg_base; member
1390 ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); in kvm_mpic_read()
1431 ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, in kvm_mpic_write()
1451 opp->reg_base, OPENPIC_REG_SIZE, in map_mmio()
1473 if (base == opp->reg_base) in set_base_addr()
1479 opp->reg_base = base; in set_base_addr()
1569 attr64 = opp->reg_base; in mpic_get_attr()
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| /arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 735 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
736 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
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| D | tegra210.dtsi | 1462 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1463 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
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| /arch/arm/boot/dts/ |
| D | tegra124.dtsi | 883 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
884 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
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