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Searched refs:rt (Results 1 – 25 of 62) sorted by relevance

123

/arch/mips/ralink/
Dtimer.c37 static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val) in rt_timer_w32() argument
39 __raw_writel(val, rt->membase + reg); in rt_timer_w32()
42 static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg) in rt_timer_r32() argument
44 return __raw_readl(rt->membase + reg); in rt_timer_r32()
49 struct rt_timer *rt = (struct rt_timer *) _rt; in rt_timer_irq() local
51 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); in rt_timer_irq()
52 rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT); in rt_timer_irq()
58 static int rt_timer_request(struct rt_timer *rt) in rt_timer_request() argument
60 int err = request_irq(rt->irq, rt_timer_irq, 0, in rt_timer_request()
61 dev_name(rt->dev), rt); in rt_timer_request()
[all …]
/arch/mips/cavium-octeon/crypto/
Docteon-crypto.h36 : [rt] "d" (cpu_to_be64(value))); \
48 : [rt] "=d" (__value) \
62 : [rt] "d" (cpu_to_be64(value))); \
73 : [rt] "d" (cpu_to_be64(value))); \
84 : [rt] "d" (value)); \
95 : [rt] "d" (value)); \
110 : [rt] "d" (value)); \
122 : [rt] "=d" (__value) \
136 : [rt] "d" (value)); \
147 : [rt] "d" (value)); \
[all …]
/arch/mips/include/asm/
Duasm.h211 # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) argument
212 # define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd) argument
213 # define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) argument
214 # define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off) argument
215 # define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd) argument
216 # define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd) argument
217 # define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd) argument
218 # define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh) argument
219 # define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off) argument
220 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) argument
[all …]
Dmipsmtregs.h286 #define mftc0(rt,sel) \ argument
294 " # mftc0 $1, $" #rt ", " #sel " \n" \
295 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
303 #define mftgpr(rt) \ argument
311 " # mftgpr $1," #rt " \n" \
312 " .word 0x41000820 | (" #rt " << 16) \n" \
320 #define mftr(rt, u, sel) \ argument
325 " mftr %0, " #rt ", " #u ", " #sel " \n" \
/arch/arm/mm/
Dcache-v7m.S22 .macro v7m_cache_read, rt, reg
23 movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
24 movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
25 ldr \rt, [\rt]
28 .macro v7m_cacheop, rt, tmp, op, c = al
31 str\c \rt, [\tmp]
35 .macro read_ccsidr, rt argument
36 v7m_cache_read \rt, V7M_SCB_CCSIDR
39 .macro read_clidr, rt argument
40 v7m_cache_read \rt, V7M_SCB_CLIDR
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/arch/mips/kernel/
Dmips-r2-to-r6-emul.c405 s32 rt, rs; in mult_func() local
407 rt = regs->regs[MIPSInst_RT(ir)]; in mult_func()
409 res = (s64)rt * (s64)rs; in mult_func()
413 rt = res >> 32; in mult_func()
414 res = (s64)rt; in mult_func()
432 u32 rt, rs; in multu_func() local
434 rt = regs->regs[MIPSInst_RT(ir)]; in multu_func()
436 res = (u64)rt * (u64)rs; in multu_func()
437 rt = res; in multu_func()
438 regs->lo = (s64)(s32)rt; in multu_func()
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Dbranch.c76 if (insn.mm_i_format.rt != 0) /* Not mm_jr */ in __mm_isBranchInstr()
77 regs->regs[insn.mm_i_format.rt] = in __mm_isBranchInstr()
87 switch (insn.mm_i_format.rt) { in __mm_isBranchInstr()
176 switch (insn.mm_i_format.rt) { in __mm_isBranchInstr()
211 regs->regs[insn.mm_i_format.rt]) in __mm_isBranchInstr()
222 regs->regs[insn.mm_i_format.rt]) in __mm_isBranchInstr()
450 switch (insn.i_format.rt) { in __compute_return_epc_for_insn()
458 if (insn.i_format.rt == bltzl_op) in __compute_return_epc_for_insn()
472 if (insn.i_format.rt == bgezl_op) in __compute_return_epc_for_insn()
482 insn.i_format.rt == bltzall_op)) in __compute_return_epc_for_insn()
[all …]
Drtlx.c286 struct rtlx_channel *rt; in rtlx_write() local
294 rt = &rtlx->channel[index]; in rtlx_write()
298 rt_read = rt->rt_read; in rtlx_write()
301 count = min_t(size_t, count, write_spacefree(rt_read, rt->rt_write, in rtlx_write()
302 rt->buffer_size)); in rtlx_write()
305 fl = min(count, (size_t) rt->buffer_size - rt->rt_write); in rtlx_write()
307 failed = copy_from_user(rt->rt_buffer + rt->rt_write, buffer, fl); in rtlx_write()
313 failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl); in rtlx_write()
319 rt->rt_write = (rt->rt_write + count) % rt->buffer_size; in rtlx_write()
Dunaligned.c982 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
995 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
1008 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
1016 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
1029 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
1060 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
1079 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
1098 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
1117 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
1140 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
[all …]
/arch/powerpc/kernel/
Dkvm.c77 static void __init kvm_patch_ins_ll(u32 *inst, long addr, u32 rt) in kvm_patch_ins_ll() argument
80 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ll()
82 kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ll()
86 static void __init kvm_patch_ins_ld(u32 *inst, long addr, u32 rt) in kvm_patch_ins_ld() argument
89 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ld()
91 kvm_patch_ins(inst, KVM_INST_LWZ | rt | ((addr + 4) & 0x0000fffc)); in kvm_patch_ins_ld()
95 static void __init kvm_patch_ins_lwz(u32 *inst, long addr, u32 rt) in kvm_patch_ins_lwz() argument
97 kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000ffff)); in kvm_patch_ins_lwz()
100 static void __init kvm_patch_ins_std(u32 *inst, long addr, u32 rt) in kvm_patch_ins_std() argument
103 kvm_patch_ins(inst, KVM_INST_STD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_std()
[all …]
/arch/x86/pci/
Dirq.c67 struct irq_routing_table *rt; in pirq_check_routing_table() local
71 rt = (struct irq_routing_table *) addr; in pirq_check_routing_table()
72 if (rt->signature != PIRQ_SIGNATURE || in pirq_check_routing_table()
73 rt->version != PIRQ_VERSION || in pirq_check_routing_table()
74 rt->size % 16 || in pirq_check_routing_table()
75 rt->size < sizeof(struct irq_routing_table)) in pirq_check_routing_table()
78 for (i = 0; i < rt->size; i++) in pirq_check_routing_table()
82 rt); in pirq_check_routing_table()
83 return rt; in pirq_check_routing_table()
97 struct irq_routing_table *rt; in pirq_find_routing_table() local
[all …]
Dpcbios.c356 struct irq_routing_table *rt = NULL; in pcibios_get_irq_routing_table() local
391 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL); in pcibios_get_irq_routing_table()
392 if (rt) { in pcibios_get_irq_routing_table()
393 memset(rt, 0, sizeof(struct irq_routing_table)); in pcibios_get_irq_routing_table()
394 rt->size = opt.size + sizeof(struct irq_routing_table); in pcibios_get_irq_routing_table()
395 rt->exclusive_irqs = map; in pcibios_get_irq_routing_table()
396 memcpy(rt->slots, (void *) page, opt.size); in pcibios_get_irq_routing_table()
401 return rt; in pcibios_get_irq_routing_table()
/arch/mips/kvm/
Ddyntrans.c88 synci_inst.i_format.rt = synci_op; in kvm_mips_trans_cache_va()
108 mfc0_inst.r_format.rd = inst.c0r_format.rt; in kvm_mips_trans_mfc0()
112 mfc0_inst.i_format.rt = inst.c0r_format.rt; in kvm_mips_trans_mfc0()
134 mtc0_inst.i_format.rt = inst.c0r_format.rt; in kvm_mips_trans_mtc0()
Demulate.c82 switch (insn.i_format.rt) { in kvm_compute_return_epc()
156 arch->gprs[insn.i_format.rt]) in kvm_compute_return_epc()
166 arch->gprs[insn.i_format.rt]) in kvm_compute_return_epc()
177 if (insn.i_format.rt != 0) in kvm_compute_return_epc()
190 if (insn.i_format.rt != 0) in kvm_compute_return_epc()
209 if (insn.i_format.rt != 0) in kvm_compute_return_epc()
215 if (insn.i_format.rs != 0 || insn.i_format.rt != 0) in kvm_compute_return_epc()
1270 u32 rt, rd, sel; in kvm_mips_emulate_CP0() local
1310 rt = inst.c0r_format.rt; in kvm_mips_emulate_CP0()
1321 vcpu->arch.gprs[rt] = in kvm_mips_emulate_CP0()
[all …]
/arch/arm/net/
Dbpf_jit_32.c311 static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12) in arm_bpf_ldst_imm12() argument
313 op |= rt << 12 | rn << 16; in arm_bpf_ldst_imm12()
321 static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8) in arm_bpf_ldst_imm8() argument
323 op |= rt << 12 | rn << 16; in arm_bpf_ldst_imm8()
331 #define ARM_LDR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off) argument
332 #define ARM_LDRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off) argument
333 #define ARM_LDRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off) argument
334 #define ARM_LDRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off) argument
336 #define ARM_STR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off) argument
337 #define ARM_STRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off) argument
[all …]
Dbpf_jit_32.h189 #define ARM_LDR_R(rt, rn, rm) (ARM_INST_LDR_R | ARM_INST_LDST__U \ argument
190 | (rt) << 12 | (rn) << 16 \
192 #define ARM_LDR_R_SI(rt, rn, rm, type, imm) \ argument
194 | (rt) << 12 | (rn) << 16 \
196 #define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | ARM_INST_LDST__U \ argument
197 | (rt) << 12 | (rn) << 16 \
199 #define ARM_LDRH_R(rt, rn, rm) (ARM_INST_LDRH_R | ARM_INST_LDST__U \ argument
200 | (rt) << 12 | (rn) << 16 \
/arch/arm/probes/kprobes/
Dactions-arm.c73 int rt = (insn >> 12) & 0xf; in emulate_ldrdstrd() local
77 register unsigned long rtv asm("r0") = regs->uregs[rt]; in emulate_ldrdstrd()
78 register unsigned long rt2v asm("r1") = regs->uregs[rt+1]; in emulate_ldrdstrd()
91 regs->uregs[rt] = rtv; in emulate_ldrdstrd()
92 regs->uregs[rt+1] = rt2v; in emulate_ldrdstrd()
102 int rt = (insn >> 12) & 0xf; in emulate_ldr() local
118 if (rt == 15) in emulate_ldr()
121 regs->uregs[rt] = rtv; in emulate_ldr()
133 int rt = (insn >> 12) & 0xf; in emulate_str() local
137 register unsigned long rtv asm("r0") = (rt == 15) ? rtpc in emulate_str()
[all …]
Dactions-thumb.c110 int rt = (insn >> 12) & 0xf; in t32_simulate_ldr_literal() local
122 if (rt == 15) { in t32_simulate_ldr_literal()
140 regs->uregs[rt] = rtv; in t32_simulate_ldr_literal()
188 int rt = (insn >> 12) & 0xf; in t32_emulate_ldrstr() local
192 register unsigned long rtv asm("r0") = regs->uregs[rt]; in t32_emulate_ldrstr()
204 if (rt == 15) /* Can't be true for a STR as they aren't allowed */ in t32_emulate_ldrstr()
207 regs->uregs[rt] = rtv; in t32_emulate_ldrstr()
325 int rt = (insn >> 8) & 0x7; in t16_simulate_ldr_literal() local
326 regs->uregs[rt] = base[index]; in t16_simulate_ldr_literal()
335 int rt = (insn >> 8) & 0x7; in t16_simulate_ldrstr_sp_relative() local
[all …]
/arch/arm/mach-rpc/
Decard-loader.S12 #define CPSR2SPSR(rt) \ argument
13 mrs rt, cpsr; \
14 msr spsr_cxsf, rt
/arch/mips/include/uapi/asm/
Dinst.h635 __BITFIELD_FIELD(unsigned int rt : 5,
643 __BITFIELD_FIELD(unsigned int rt : 5,
660 __BITFIELD_FIELD(unsigned int rt : 5,
670 __BITFIELD_FIELD(unsigned int rt : 5,
680 __BITFIELD_FIELD(unsigned int rt : 5,
700 __BITFIELD_FIELD(unsigned int rt : 5,
711 __BITFIELD_FIELD(unsigned int rt : 5,
780 __BITFIELD_FIELD(unsigned int rt:5,
826 __BITFIELD_FIELD(unsigned int rt : 5,
835 __BITFIELD_FIELD(unsigned int rt : 5,
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/arch/powerpc/kvm/
Demulate.c128 static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) in kvmppc_emulate_mfspr() argument
186 kvmppc_set_gpr(vcpu, rt, spr_val); in kvmppc_emulate_mfspr()
197 int rs, rt, sprn; in kvmppc_emulate_instruction() local
211 rt = get_rt(inst); in kvmppc_emulate_instruction()
243 emulated = kvmppc_emulate_mfspr(vcpu, sprn, rt); in kvmppc_emulate_instruction()
/arch/ia64/kernel/
Dsmpboot.c215 get_delta (long *rt, long *master) in get_delta() argument
233 *rt = best_t1 - best_t0; in get_delta()
279 unsigned long flags, rt, master_time_stamp, bound; in ia64_sync_itc() local
282 long rt; /* roundtrip time */ in ia64_sync_itc() member
310 delta = get_delta(&rt, &master_time_stamp); in ia64_sync_itc()
313 bound = rt; in ia64_sync_itc()
326 t[i].rt = rt; in ia64_sync_itc()
338 t[i].rt, t[i].master, t[i].diff, t[i].lat); in ia64_sync_itc()
342 "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt); in ia64_sync_itc()
/arch/arm64/kernel/
Dtraps.c432 int rt = ESR_ELx_SYS64_ISS_RT(esr); in user_cache_maint_handler() local
436 address = untagged_addr(pt_regs_read_reg(regs, rt)); in user_cache_maint_handler()
470 int rt = ESR_ELx_SYS64_ISS_RT(esr); in ctr_read_handler() local
482 pt_regs_write_reg(regs, rt, val); in ctr_read_handler()
489 int rt = ESR_ELx_SYS64_ISS_RT(esr); in cntvct_read_handler() local
491 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); in cntvct_read_handler()
497 int rt = ESR_ELx_SYS64_ISS_RT(esr); in cntfrq_read_handler() local
499 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); in cntfrq_read_handler()
505 u32 sysreg, rt; in mrs_handler() local
507 rt = ESR_ELx_SYS64_ISS_RT(esr); in mrs_handler()
[all …]
/arch/mips/math-emu/
Dcp1emu.c91 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; in microMIPS32_to_MIPS32()
92 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; in microMIPS32_to_MIPS32()
96 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; in microMIPS32_to_MIPS32()
97 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; in microMIPS32_to_MIPS32()
101 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; in microMIPS32_to_MIPS32()
102 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; in microMIPS32_to_MIPS32()
106 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; in microMIPS32_to_MIPS32()
107 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; in microMIPS32_to_MIPS32()
111 if ((insn.mm_i_format.rt == mm_bc1f_op) || in microMIPS32_to_MIPS32()
112 (insn.mm_i_format.rt == mm_bc1t_op)) { in microMIPS32_to_MIPS32()
[all …]
/arch/powerpc/crypto/
Dsha1-powerpc-asm.S13 #define LWZ(rt, d, ra) \ argument
14 lwz rt,d(ra)
16 #define LWZ(rt, d, ra) \ argument
17 li rt,d; \
18 lwbrx rt,rt,ra

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