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Searched refs:sel (Results 1 – 25 of 90) sorted by relevance

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/arch/mips/include/asm/netlogic/
Dmips-extns.h174 #define __read_64bit_c2_split(source, sel) \ argument
180 if (sel == 0) \
192 "dmfc2\t%M0, " #source ", " #sel "\n\t" \
203 #define __write_64bit_c2_split(source, sel, val) \ argument
208 if (sel == 0) \
225 "dmtc2\t%L0, " #source ", " #sel "\n\t" \
231 #define __read_32bit_c2_register(source, sel) \ argument
233 if (sel == 0) \
242 "mfc2\t%0, " #source ", " #sel "\n\t" \
248 #define __read_64bit_c2_register(source, sel) \ argument
[all …]
/arch/arm/mach-dove/
Dmpp.c71 static void __init dove_mpp_cfg_nfc(int sel) in dove_mpp_cfg_nfc() argument
76 mpp_gen_cfg |= sel; in dove_mpp_cfg_nfc()
82 static void __init dove_mpp_cfg_au1(int sel) in dove_mpp_cfg_au1() argument
94 if (!sel || sel == 0x2) in dove_mpp_cfg_au1()
99 if (sel & 0x1) { in dove_mpp_cfg_au1()
103 if (sel & 0x2) { in dove_mpp_cfg_au1()
107 if (sel & 0x4) { in dove_mpp_cfg_au1()
111 if (sel & 0x8) in dove_mpp_cfg_au1()
129 unsigned int sel = MPP_SEL(*mpp_grp_list); in dove_mpp_conf_grp() local
137 mpp_ctrl4 |= sel << num; in dove_mpp_conf_grp()
[all …]
/arch/x86/kernel/
Dtls.c119 unsigned short __maybe_unused sel, modified_sel; in do_set_thread_area() local
156 savesegment(ds, sel); in do_set_thread_area()
157 if (sel == modified_sel) in do_set_thread_area()
158 loadsegment(ds, sel); in do_set_thread_area()
160 savesegment(es, sel); in do_set_thread_area()
161 if (sel == modified_sel) in do_set_thread_area()
162 loadsegment(es, sel); in do_set_thread_area()
164 savesegment(fs, sel); in do_set_thread_area()
165 if (sel == modified_sel) in do_set_thread_area()
166 loadsegment(fs, sel); in do_set_thread_area()
[all …]
Dldt.c35 unsigned short sel; in refresh_ldt_segments() local
41 savesegment(ds, sel); in refresh_ldt_segments()
42 if ((sel & SEGMENT_TI_MASK) == SEGMENT_LDT) in refresh_ldt_segments()
43 loadsegment(ds, sel); in refresh_ldt_segments()
45 savesegment(es, sel); in refresh_ldt_segments()
46 if ((sel & SEGMENT_TI_MASK) == SEGMENT_LDT) in refresh_ldt_segments()
47 loadsegment(es, sel); in refresh_ldt_segments()
/arch/mips/kvm/
Ddyntrans.c101 u32 rd, sel; in kvm_mips_trans_mfc0() local
104 sel = inst.c0r_format.sel; in kvm_mips_trans_mfc0()
106 if (rd == MIPS_CP0_ERRCTL && sel == 0) { in kvm_mips_trans_mfc0()
114 offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); in kvm_mips_trans_mfc0()
128 u32 rd, sel; in kvm_mips_trans_mtc0() local
131 sel = inst.c0r_format.sel; in kvm_mips_trans_mtc0()
136 offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); in kvm_mips_trans_mtc0()
Dvz.c907 u32 rt, rd, sel; in kvm_vz_gpsi_cop0() local
931 sel = inst.c0r_format.sel; in kvm_vz_gpsi_cop0()
937 cop0->stat[rd][sel]++; in kvm_vz_gpsi_cop0()
940 sel == 0) { /* Count */ in kvm_vz_gpsi_cop0()
943 sel == 0) { /* Compare */ in kvm_vz_gpsi_cop0()
946 sel == 0) { /* LLAddr */ in kvm_vz_gpsi_cop0()
953 sel == 1 && /* MAAR */ in kvm_vz_gpsi_cop0()
962 (sel == 0 || /* PRid */ in kvm_vz_gpsi_cop0()
963 sel == 2 || /* CDMMBase */ in kvm_vz_gpsi_cop0()
964 sel == 3)) || /* CMGCRBase */ in kvm_vz_gpsi_cop0()
[all …]
Demulate.c1270 u32 rt, rd, sel; in kvm_mips_emulate_CP0() local
1312 sel = inst.c0r_format.sel; in kvm_mips_emulate_CP0()
1317 cop0->stat[rd][sel]++; in kvm_mips_emulate_CP0()
1320 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { in kvm_mips_emulate_CP0()
1323 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) { in kvm_mips_emulate_CP0()
1329 vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel]; in kvm_mips_emulate_CP0()
1337 KVM_TRACE_COP0(rd, sel), in kvm_mips_emulate_CP0()
1342 vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; in kvm_mips_emulate_CP0()
1345 KVM_TRACE_COP0(rd, sel), in kvm_mips_emulate_CP0()
1351 cop0->stat[rd][sel]++; in kvm_mips_emulate_CP0()
[all …]
/arch/x86/lib/
Dinsn-eval.c324 unsigned short sel; in get_segment_selector() local
334 savesegment(ds, sel); in get_segment_selector()
335 return sel; in get_segment_selector()
337 savesegment(es, sel); in get_segment_selector()
338 return sel; in get_segment_selector()
340 savesegment(fs, sel); in get_segment_selector()
341 return sel; in get_segment_selector()
343 savesegment(gs, sel); in get_segment_selector()
344 return sel; in get_segment_selector()
574 static bool get_desc(struct desc_struct *out, unsigned short sel) in get_desc() argument
[all …]
/arch/mips/include/asm/
Dmipsregs.h1351 #define ___read_32bit_c0_register(source, sel, vol) \ argument
1353 if (sel == 0) \
1361 "mfc0\t%0, " #source ", " #sel "\n\t" \
1367 #define ___read_64bit_c0_register(source, sel, vol) \ argument
1370 __res = __read_64bit_c0_split(source, sel, vol); \
1371 else if (sel == 0) \
1382 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1388 #define __read_32bit_c0_register(source, sel) \ argument
1389 ___read_32bit_c0_register(source, sel, __volatile__)
1391 #define __read_const_32bit_c0_register(source, sel) \ argument
[all …]
Dmipsmtregs.h286 #define mftc0(rt,sel) \ argument
294 " # mftc0 $1, $" #rt ", " #sel " \n" \
295 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
320 #define mftr(rt, u, sel) \ argument
325 " mftr %0, " #rt ", " #u ", " #sel " \n" \
344 #define mttc0(rd, sel, v) \ argument
351 " # mttc0 %0," #rd ", " #sel " \n" \
352 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
359 #define mttr(rd, u, sel, v) \ argument
362 "mttr %0," #rd ", " #u ", " #sel \
Dkvm_host.h475 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ argument
478 return cop0->reg[(_reg)][(sel)]; \
483 cop0->reg[(_reg)][(sel)] = val; \
487 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ argument
491 cop0->reg[(_reg)][(sel)] |= val; \
496 cop0->reg[(_reg)][(sel)] &= ~val; \
503 cop0->reg[(_reg)][(sel)] &= ~_mask; \
504 cop0->reg[(_reg)][(sel)] |= val & _mask; \
508 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ argument
512 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
[all …]
/arch/powerpc/perf/
Dmpc7450-pmu.c79 int pmc, sel; in mpc7450_threshold_use() local
82 sel = event & PM_PMCSEL_MSK; in mpc7450_threshold_use()
85 if (sel == 0x1e || sel == 0x1f) in mpc7450_threshold_use()
87 if (sel == 0x28 || sel == 0x2b) in mpc7450_threshold_use()
91 if (sel == 0x20) in mpc7450_threshold_use()
95 if (sel == 0xc || sel == 0xd) in mpc7450_threshold_use()
97 if (sel == 0x11) in mpc7450_threshold_use()
101 if (sel == 0x10) in mpc7450_threshold_use()
/arch/alpha/kernel/
Dtime.c206 unsigned char x, sel = 0; in common_init_rtc() local
214 sel = RTC_REF_CLCK_32KHZ + 6; in common_init_rtc()
217 sel = RTC_REF_CLCK_32KHZ + __builtin_ffs(32768 / CONFIG_HZ); in common_init_rtc()
221 if (sel) { in common_init_rtc()
223 CONFIG_HZ, sel); in common_init_rtc()
224 CMOS_WRITE(sel, RTC_FREQ_SELECT); in common_init_rtc()
/arch/arm/plat-orion/
Dmpp.c48 unsigned int sel = MPP_SEL(*mpp_list); in orion_mpp_conf() local
65 mpp_ctrl[num / 8] |= sel << shift; in orion_mpp_conf()
/arch/x86/boot/
Dvideo.c203 unsigned int sel; in mode_menu() local
224 sel = get_entry(); in mode_menu()
225 if (sel != SCAN) in mode_menu()
226 return sel; in mode_menu()
/arch/x86/kernel/cpu/resctrl/
Dpseudo_lock.c1157 static int pseudo_lock_measure_cycles(struct rdtgroup *rdtgrp, int sel) in pseudo_lock_measure_cycles() argument
1186 if (sel == 1) in pseudo_lock_measure_cycles()
1191 else if (sel == 2) in pseudo_lock_measure_cycles()
1196 else if (sel == 3) in pseudo_lock_measure_cycles()
1232 int sel; in pseudo_lock_measure_trigger() local
1239 ret = kstrtoint(buf, 10, &sel); in pseudo_lock_measure_trigger()
1241 if (sel != 1 && sel != 2 && sel != 3) in pseudo_lock_measure_trigger()
1246 ret = pseudo_lock_measure_cycles(rdtgrp, sel); in pseudo_lock_measure_trigger()
/arch/arm/boot/dts/
Dmt2701-evb.dts45 i2s1-in-sel-gpio1 = <&pio 53 0>;
46 i2s1-in-sel-gpio2 = <&pio 54 0>;
Dsocfpga_cyclone5_mcvevk.dts64 ts,ref-sel = <0>;
Dbcm53340-ubnt-unifi-switch8.dts35 bspi-sel = <0>;
Dtegra124-apalis-emc.dtsi107 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
204 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
301 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
398 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
495 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
592 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
689 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
786 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
883 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
980 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi102 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
270 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
438 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
606 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
774 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
942 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1110 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1278 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1446 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1614 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi91 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
259 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
427 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
595 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
763 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
931 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1099 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1267 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1435 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1603 nvidia,emc-sel-dpd-ctrl = <0x00040000>;
Dtegra124-nyan-big-emc.dtsi91 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
259 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
427 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
595 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
763 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
931 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1099 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1267 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1435 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1603 nvidia,emc-sel-dpd-ctrl = <0x00040000>;
/arch/arm64/boot/dts/mediatek/
Dmt8183.dtsi379 clock-names = "parent-clk", "sel-clk", "spi-clk";
406 clock-names = "parent-clk", "sel-clk", "spi-clk";
433 clock-names = "parent-clk", "sel-clk", "spi-clk";
446 clock-names = "parent-clk", "sel-clk", "spi-clk";
519 clock-names = "parent-clk", "sel-clk", "spi-clk";
532 clock-names = "parent-clk", "sel-clk", "spi-clk";
/arch/x86/oprofile/
Dop_model_p4.c353 #define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25)) argument
359 #define CCCR_SET_ESCR_SELECT(cccr, sel) ((cccr) |= (((sel) & 0x07) << 13)) argument

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