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Searched refs:writel (Results 1 – 25 of 186) sorted by relevance

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/arch/arc/plat-hsdk/
Dplatform.c225 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
226 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
227 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
228 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
229 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
231 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
232 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
233 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
234 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
235 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
[all …]
/arch/arm/mach-pxa/
Dcm-x2xx-pci.c133 writel(0x848, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
134 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
137 writel(0x840, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
138 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
140 writel(0x20, IT8152_GPIO_GPDR); in cmx2xx_pci_preinit()
143 writel(0x4000, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
148 writel(0x408C, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
149 writel(0x1022, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
151 writel(0x4080, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
152 writel(0x3844d060, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
[all …]
/arch/unicore32/kernel/
Dirq.c64 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); in puv3_gpio_type()
65 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); in puv3_gpio_type()
75 writel((1 << d->irq), GPIO_GEDR); in puv3_low_gpio_ack()
80 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); in puv3_low_gpio_mask()
85 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); in puv3_low_gpio_unmask()
91 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
93 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
121 writel(mask, GPIO_GEDR); in puv3_gpio_handler()
143 writel(mask, GPIO_GEDR); in puv3_high_gpio_ack()
152 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); in puv3_high_gpio_mask()
[all …]
Dtime.c26 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_ost0_interrupt()
27 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_ost0_interrupt()
38 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); in puv3_osmr0_set_next_event()
40 writel(next, OST_OSMR0); in puv3_osmr0_set_next_event()
48 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_osmr0_shutdown()
49 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_osmr0_shutdown()
84 writel(0, OST_OIER); /* disable any timer interrupts */ in time_init()
85 writel(0, OST_OSSR); /* clear status on all timers */ in time_init()
117 writel(0, OST_OSSR); in puv3_timer_resume()
118 writel(osmr[0], OST_OSMR0); in puv3_timer_resume()
[all …]
Dpci.c28 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_read_config()
47 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_write_config()
50 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) in puv3_write_config()
54 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) in puv3_write_config()
58 writel(value, PCICFG_DATA); in puv3_write_config()
73 writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); in pci_puv3_preinit()
75 writel(0, PCIBRI_AHBCTL0); in pci_puv3_preinit()
76 writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); in pci_puv3_preinit()
77 writel(0xFFFF0000, PCIBRI_AHBAMR0); in pci_puv3_preinit()
78 writel(0, PCIBRI_AHBTAR0); in pci_puv3_preinit()
[all …]
/arch/m68k/coldfire/
Dm53xx.c317 writel(0x77777777, MCF_SCM_MPR); in scm_init()
321 writel(0, MCF_SCM_PACRA); in scm_init()
322 writel(0, MCF_SCM_PACRB); in scm_init()
323 writel(0, MCF_SCM_PACRC); in scm_init()
324 writel(0, MCF_SCM_PACRD); in scm_init()
325 writel(0, MCF_SCM_PACRE); in scm_init()
326 writel(0, MCF_SCM_PACRF); in scm_init()
329 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); in scm_init()
338 writel(0x10080000, MCF_FBCS1_CSAR); in fbcs_init()
340 writel(0x002A3780, MCF_FBCS1_CSCR); in fbcs_init()
[all …]
/arch/arm/plat-orion/
Dtime.c87 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_next_event()
91 writel(u, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
96 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event()
103 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
119 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
123 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_shutdown()
126 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_shutdown()
141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_set_periodic()
142 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_set_periodic()
146 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_set_periodic()
[all …]
Dpcie.c89 writel(stat, base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
105 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
115 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); in orion_pcie_setup_wins()
136 writel(0, base + PCIE_BAR_LO_OFF(i)); in orion_pcie_setup_wins()
137 writel(0, base + PCIE_BAR_HI_OFF(i)); in orion_pcie_setup_wins()
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); in orion_pcie_setup_wins()
142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); in orion_pcie_setup_wins()
146 writel(0, base + PCIE_WIN5_CTRL_OFF); in orion_pcie_setup_wins()
[all …]
/arch/mips/ar7/
Dirq.c41 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_unmask_irq()
47 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_mask_irq()
53 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_ack_irq()
59 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
64 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
69 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
98 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
99 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
100 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
101 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init()
[all …]
/arch/arm/mach-cns3xxx/
Dcore.c104 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
115 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_shutdown()
125 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_oneshot()
136 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_set_periodic()
138 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_periodic()
147 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_timer_set_next_event()
148 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
185 writel(val & ~(1 << 2), stat); in cns3xxx_timer_interrupt()
211 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
213 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); in __cns3xxx_timer_init()
[all …]
/arch/arm/mach-sunxi/
Dplatsmp.c85 writel(__pa_symbol(secondary_startup), in sun6i_smp_boot_secondary()
89 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
93 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
97 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
101 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); in sun6i_smp_boot_secondary()
106 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
110 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
114 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
169 writel(__pa_symbol(secondary_startup), in sun8i_smp_boot_secondary()
173 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun8i_smp_boot_secondary()
[all …]
Dmc_smp.c130 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
132 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
134 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
136 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
138 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
141 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
151 writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base); in sunxi_cpu0_hotplug_support_set()
152 writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4); in sunxi_cpu0_hotplug_support_set()
154 writel(0x0, sram_b_smp_base); in sunxi_cpu0_hotplug_support_set()
155 writel(0x0, sram_b_smp_base + 0x4); in sunxi_cpu0_hotplug_support_set()
[all …]
/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c28 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init()
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
54 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init()
58 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, in s3c_usb_otgphy_init()
61 writel(0, S3C_RSTCON); in s3c_usb_otgphy_init()
68 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit()
71 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
/arch/arm/mach-orion5x/
Dtsx09-common.c32 writel(0x83, UART1_REG(LCR)); in qnap_tsx09_power_off()
33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
34 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in qnap_tsx09_power_off()
35 writel(0x03, UART1_REG(LCR)); in qnap_tsx09_power_off()
36 writel(0x00, UART1_REG(IER)); in qnap_tsx09_power_off()
37 writel(0x00, UART1_REG(FCR)); in qnap_tsx09_power_off()
38 writel(0x00, UART1_REG(MCR)); in qnap_tsx09_power_off()
41 writel('A', UART1_REG(TX)); in qnap_tsx09_power_off()
/arch/arm/mach-mvebu/
Dpm.c55 writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); in mvebu_pm_powerdown()
62 writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); in mvebu_pm_powerdown()
124 writel(BOOT_MAGIC_WORD, store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
125 writel(resume_pc, store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
133 writel(MBUS_WINDOW_12_CTRL, store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
134 writel(0x0, store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
140 writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
141 writel(mvebu_internal_reg_base(), store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
150 writel(BOOT_MAGIC_LIST_END, store_addr); in mvebu_pm_store_armadaxp_bootinfo()
/arch/arm/mach-highbank/
Dsysregs.h47 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_suspend()
53 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_shutdown()
59 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_soft_reset()
65 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_hard_reset()
71 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
/arch/mips/jz4740/
Dtimer.c20 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_enable_watchdog()
26 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_disable_watchdog()
38 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_init()
41 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_init()
/arch/arm/mach-socfpga/
Dplatsmp.c27 writel(RSTMGR_MPUMODRST_CPU1, in socfpga_boot_secondary()
32 writel(__pa_symbol(secondary_startup), in socfpga_boot_secondary()
40 writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST); in socfpga_boot_secondary()
51 writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + in socfpga_a10_boot_secondary()
55 writel(__pa_symbol(secondary_startup), in socfpga_a10_boot_secondary()
63 writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST); in socfpga_a10_boot_secondary()
Docram.c37 writel(ALTR_OCRAM_CLEAR_ECC, mapped_ocr_edac_addr); in socfpga_init_ocram_ecc()
38 writel(ALTR_OCRAM_ECC_EN, mapped_ocr_edac_addr); in socfpga_init_ocram_ecc()
72 writel(value, ioaddr); in ecc_set_bits()
80 writel(value, ioaddr); in ecc_clear_bits()
109 writel(ALTR_A10_ECC_ERRPENA_MASK, in altr_init_memory_port()
142 writel(ALTR_A10_OCRAM_ECC_EN_CTL, in socfpga_init_arria10_ocram_ecc()
164 writel(ALTR_A10_OCRAM_ECC_EN_CTL, in socfpga_init_arria10_ocram_ecc()
Dl2_cache.c42 writel(0x01, mapped_l2_edac_addr); in socfpga_init_l2_ecc()
70 writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr + in socfpga_init_arria10_l2_ecc()
73 writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr + in socfpga_init_arria10_l2_ecc()
75 writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr + in socfpga_init_arria10_l2_ecc()
/arch/arm/mach-rockchip/
Drockchip.c38 writel(0, reg_base + 0x30); in rockchip_timer_init()
39 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
40 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
41 writel(1, reg_base + 0x30); in rockchip_timer_init()
/arch/arm/mach-ep93xx/
Dtimer-ep93xx.c81 writel(tmode, EP93XX_TIMER3_CONTROL); in ep93xx_clkevt_set_next_event()
84 writel(next, EP93XX_TIMER3_LOAD); in ep93xx_clkevt_set_next_event()
85 writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, in ep93xx_clkevt_set_next_event()
94 writel(0, EP93XX_TIMER3_CONTROL); in ep93xx_clkevt_shutdown()
114 writel(1, EP93XX_TIMER3_CLEAR); in ep93xx_timer_interrupt()
131 writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, in ep93xx_timer_init()
/arch/arm/mach-dove/
Dmpp.c77 writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
114 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
115 writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
116 writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
117 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
143 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
/arch/mips/include/asm/mach-jz4740/
Dtimer.h57 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_stop()
62 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_start()
102 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); in jz4740_timer_ack_full()
107 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); in jz4740_timer_irq_full_enable()
108 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); in jz4740_timer_irq_full_enable()
113 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_irq_full_disable()
/arch/arm/mach-berlin/
Dplatsmp.c39 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu()
41 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu()
86 writel(boot_inst, vectors_base + RESET_VECT); in berlin_smp_prepare_cpus()
92 writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR); in berlin_smp_prepare_cpus()
113 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_cpu_kill()

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