1======================================================= 2Activity Monitors Unit (AMU) extension in AArch64 Linux 3======================================================= 4 5Author: Ionela Voinescu <ionela.voinescu@arm.com> 6 7Date: 2019-09-10 8 9This document briefly describes the provision of Activity Monitors Unit 10support in AArch64 Linux. 11 12 13Architecture overview 14--------------------- 15 16The activity monitors extension is an optional extension introduced by the 17ARMv8.4 CPU architecture. 18 19The activity monitors unit, implemented in each CPU, provides performance 20counters intended for system management use. The AMU extension provides a 21system register interface to the counter registers and also supports an 22optional external memory-mapped interface. 23 24Version 1 of the Activity Monitors architecture implements a counter group 25of four fixed and architecturally defined 64-bit event counters. 26 - CPU cycle counter: increments at the frequency of the CPU. 27 - Constant counter: increments at the fixed frequency of the system 28 clock. 29 - Instructions retired: increments with every architecturally executed 30 instruction. 31 - Memory stall cycles: counts instruction dispatch stall cycles caused by 32 misses in the last level cache within the clock domain. 33 34When in WFI or WFE these counters do not increment. 35 36The Activity Monitors architecture provides space for up to 16 architected 37event counters. Future versions of the architecture may use this space to 38implement additional architected event counters. 39 40Additionally, version 1 implements a counter group of up to 16 auxiliary 4164-bit event counters. 42 43On cold reset all counters reset to 0. 44 45 46Basic support 47------------- 48 49The kernel can safely run a mix of CPUs with and without support for the 50activity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is 51selected we unconditionally enable the capability to allow any late CPU 52(secondary or hotplugged) to detect and use the feature. 53 54When the feature is detected on a CPU, we flag the availability of the 55feature but this does not guarantee the correct functionality of the 56counters, only the presence of the extension. 57 58Firmware (code running at higher exception levels, e.g. arm-tf) support is 59needed to: 60 - Enable access for lower exception levels (EL2 and EL1) to the AMU 61 registers. 62 - Enable the counters. If not enabled these will read as 0. 63 - Save/restore the counters before/after the CPU is being put/brought up 64 from the 'off' power state. 65 66When using kernels that have this feature enabled but boot with broken 67firmware the user may experience panics or lockups when accessing the 68counter registers. Even if these symptoms are not observed, the values 69returned by the register reads might not correctly reflect reality. Most 70commonly, the counters will read as 0, indicating that they are not 71enabled. 72 73If proper support is not provided in firmware it's best to disable 74CONFIG_ARM64_AMU_EXTN. To be noted that for security reasons, this does not 75bypass the setting of AMUSERENR_EL0 to trap accesses from EL0 (userspace) to 76EL1 (kernel). Therefore, firmware should still ensure accesses to AMU registers 77are not trapped in EL2/EL3. 78 79The fixed counters of AMUv1 are accessible though the following system 80register definitions: 81 - SYS_AMEVCNTR0_CORE_EL0 82 - SYS_AMEVCNTR0_CONST_EL0 83 - SYS_AMEVCNTR0_INST_RET_EL0 84 - SYS_AMEVCNTR0_MEM_STALL_EL0 85 86Auxiliary platform specific counters can be accessed using 87SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15. 88 89Details can be found in: arch/arm64/include/asm/sysreg.h. 90 91 92Userspace access 93---------------- 94 95Currently, access from userspace to the AMU registers is disabled due to: 96 - Security reasons: they might expose information about code executed in 97 secure mode. 98 - Purpose: AMU counters are intended for system management use. 99 100Also, the presence of the feature is not visible to userspace. 101 102 103Virtualization 104-------------- 105 106Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM 107guest side is disabled due to: 108 - Security reasons: they might expose information about code executed 109 by other guests or the host. 110 111Any attempt to access the AMU registers will result in an UNDEFINED 112exception being injected into the guest. 113