1* Renesas SDHI SD/MMC controller 2 3Required properties: 4- compatible: should contain one or more of the following: 5 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC 6 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC 7 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC 8 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC 9 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC 10 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC 11 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC 12 "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC 13 "renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC 14 "renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC 15 "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC 16 "renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC 17 "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC 18 "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC 19 "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC 20 "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC 21 "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC 22 "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC 23 "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC 24 "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC 25 "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC 26 "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC 27 "renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC 28 "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC 29 "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC 30 "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC 31 "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller 32 "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller 33 "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI 34 (not SDHI/MMC) controller 35 "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2 36 SDHI controller 37 38 39 When compatible with the generic version, nodes must list 40 the SoC-specific version corresponding to the platform 41 first followed by the generic version. 42 43- clocks: Most controllers only have 1 clock source per channel. However, on 44 some variations of this controller, the internal card detection 45 logic that exists in this controller is sectioned off to be run by a 46 separate second clock source to allow the main core clock to be turned 47 off to save power. 48 If 2 clocks are specified by the hardware, you must name them as 49 "core" and "cd". If the controller only has 1 clock, naming is not 50 required. 51 Devices which have more than 1 clock are listed below: 52 2: R7S72100, R7S9210 53 54Optional properties: 55- pinctrl-names: should be "default", "state_uhs" 56- pinctrl-0: should contain default/high speed pin ctrl 57- pinctrl-1: should contain uhs mode pin ctrl 58 59Example: R8A7790 (R-Car H2) SDHI controller nodes 60 61 sdhi0: sd@ee100000 { 62 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 63 reg = <0 0xee100000 0 0x328>; 64 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 65 clocks = <&cpg CPG_MOD 314>; 66 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 67 <&dmac1 0xcd>, <&dmac1 0xce>; 68 dma-names = "tx", "rx", "tx", "rx"; 69 max-frequency = <195000000>; 70 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 71 resets = <&cpg 314>; 72 }; 73 74 sdhi1: sd@ee120000 { 75 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 76 reg = <0 0xee120000 0 0x328>; 77 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&cpg CPG_MOD 313>; 79 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, 80 <&dmac1 0xc9>, <&dmac1 0xca>; 81 dma-names = "tx", "rx", "tx", "rx"; 82 max-frequency = <195000000>; 83 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 84 resets = <&cpg 313>; 85 }; 86 87 sdhi2: sd@ee140000 { 88 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 89 reg = <0 0xee140000 0 0x100>; 90 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&cpg CPG_MOD 312>; 92 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 93 <&dmac1 0xc1>, <&dmac1 0xc2>; 94 dma-names = "tx", "rx", "tx", "rx"; 95 max-frequency = <97500000>; 96 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 97 resets = <&cpg 312>; 98 }; 99 100 sdhi3: sd@ee160000 { 101 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; 102 reg = <0 0xee160000 0 0x100>; 103 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&cpg CPG_MOD 311>; 105 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 106 <&dmac1 0xd3>, <&dmac1 0xd4>; 107 dma-names = "tx", "rx", "tx", "rx"; 108 max-frequency = <97500000>; 109 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 110 resets = <&cpg 311>; 111 }; 112