• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1* Ingenic JZ4780 NAND/ECC
2
3This file documents the device tree bindings for NAND flash devices on the
4JZ4780. NAND devices are connected to the NEMC controller (described in
5memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
6be children of the NEMC node.
7
8Required NAND controller device properties:
9- compatible: Should be one of:
10  * ingenic,jz4740-nand
11  * ingenic,jz4725b-nand
12  * ingenic,jz4780-nand
13- reg: For each bank with a NAND chip attached, should specify a bank number,
14  an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
15
16Optional NAND controller device properties:
17- ecc-engine: To make use of the hardware ECC controller, this
18  property must contain a phandle for the ECC controller node. The required
19  properties for this node are described below. If this is not specified,
20  software ECC will be used instead.
21
22Optional children nodes:
23- Individual NAND chips are children of the NAND controller node.
24
25Required children node properties:
26- reg: An integer ranging from 1 to 6 representing the CS line to use.
27
28Optional children node properties:
29- nand-ecc-step-size: ECC block size in bytes.
30- nand-ecc-strength: ECC strength (max number of correctable bits).
31- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
32- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
33- rb-gpios: GPIO specifier for the busy pin.
34- wp-gpios: GPIO specifier for the write protect pin.
35
36Optional child node of NAND chip nodes:
37- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
38
39Example:
40
41nemc: nemc@13410000 {
42	...
43
44	nandc: nand-controller@1 {
45		compatible = "ingenic,jz4780-nand";
46		reg = <1 0 0x1000000>;	/* Bank 1 */
47
48		#address-cells = <1>;
49		#size-cells = <0>;
50
51		ecc-engine = <&bch>;
52
53		nand@1 {
54			reg = <1>;
55
56			nand-ecc-step-size = <1024>;
57			nand-ecc-strength = <24>;
58			nand-ecc-mode = "hw";
59			nand-on-flash-bbt;
60
61			rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
62			wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
63
64			partitions {
65				#address-cells = <2>;
66				#size-cells = <2>;
67				...
68			}
69		};
70	};
71};
72
73The ECC controller is a separate SoC component used for error correction on
74NAND devices. The following is a description of the device properties for a
75ECC controller.
76
77Required ECC properties:
78- compatible: Should be one of:
79  * ingenic,jz4740-ecc
80  * ingenic,jz4725b-bch
81  * ingenic,jz4780-bch
82- reg: Should specify the ECC controller registers location and length.
83- clocks: Clock for the ECC controller.
84
85Example:
86
87bch: bch@134d0000 {
88	compatible = "ingenic,jz4780-bch";
89	reg = <0x134d0000 0x10000>;
90
91	clocks = <&cgu JZ4780_CLK_BCH>;
92};
93