1* Serial NOR flash controller for MediaTek SoCs 2 3Required properties: 4- compatible: For mt8173, compatible should be "mediatek,mt8173-nor", 5 and it's the fallback compatible for other Soc. 6 For every other SoC, should contain both the SoC-specific compatible 7 string and "mediatek,mt8173-nor". 8 The possible values are: 9 "mediatek,mt2701-nor", "mediatek,mt8173-nor" 10 "mediatek,mt2712-nor", "mediatek,mt8173-nor" 11 "mediatek,mt7622-nor", "mediatek,mt8173-nor" 12 "mediatek,mt7623-nor", "mediatek,mt8173-nor" 13 "mediatek,mt7629-nor", "mediatek,mt8173-nor" 14 "mediatek,mt8173-nor" 15- reg: physical base address and length of the controller's register 16- clocks: the phandle of the clocks needed by the nor controller 17- clock-names: the names of the clocks 18 the clocks should be named "spi" and "sf". "spi" is used for spi bus, 19 and "sf" is used for controller, these are the clocks witch 20 hardware needs to enabling nor flash and nor flash controller. 21 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 22- #address-cells: should be <1> 23- #size-cells: should be <0> 24 25The SPI flash must be a child of the nor_flash node and must have a 26compatible property. Also see jedec,spi-nor.txt. 27 28Required properties: 29- compatible: May include a device-specific string consisting of the manufacturer 30 and name of the chip. Must also include "jedec,spi-nor" for any 31 SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). 32- reg : Chip-Select number 33 34Example: 35 36nor_flash: spi@1100d000 { 37 compatible = "mediatek,mt8173-nor"; 38 reg = <0 0x1100d000 0 0xe0>; 39 clocks = <&pericfg CLK_PERI_SPI>, 40 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 41 clock-names = "spi", "sf"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 flash@0 { 46 compatible = "jedec,spi-nor"; 47 reg = <0>; 48 }; 49}; 50 51