1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/alpha/kernel/sys_mikasa.c
4 *
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
8 *
9 * Code supporting the MIKASA (AlphaServer 1000).
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/mm.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/bitops.h>
19
20 #include <asm/ptrace.h>
21 #include <asm/mce.h>
22 #include <asm/dma.h>
23 #include <asm/irq.h>
24 #include <asm/mmu_context.h>
25 #include <asm/io.h>
26 #include <asm/pgtable.h>
27 #include <asm/core_apecs.h>
28 #include <asm/core_cia.h>
29 #include <asm/tlbflush.h>
30
31 #include "proto.h"
32 #include "irq_impl.h"
33 #include "pci_impl.h"
34 #include "machvec_impl.h"
35
36
37 /* Note mask bit is true for ENABLED irqs. */
38 static int cached_irq_mask;
39
40 static inline void
mikasa_update_irq_hw(int mask)41 mikasa_update_irq_hw(int mask)
42 {
43 outw(mask, 0x536);
44 }
45
46 static inline void
mikasa_enable_irq(struct irq_data * d)47 mikasa_enable_irq(struct irq_data *d)
48 {
49 mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
50 }
51
52 static void
mikasa_disable_irq(struct irq_data * d)53 mikasa_disable_irq(struct irq_data *d)
54 {
55 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
56 }
57
58 static struct irq_chip mikasa_irq_type = {
59 .name = "MIKASA",
60 .irq_unmask = mikasa_enable_irq,
61 .irq_mask = mikasa_disable_irq,
62 .irq_mask_ack = mikasa_disable_irq,
63 };
64
65 static void
mikasa_device_interrupt(unsigned long vector)66 mikasa_device_interrupt(unsigned long vector)
67 {
68 unsigned long pld;
69 unsigned int i;
70
71 /* Read the interrupt summary registers */
72 pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
73 | (((unsigned long) inb(0xa0)) << 8)
74 | inb(0x20));
75
76 /*
77 * Now for every possible bit set, work through them and call
78 * the appropriate interrupt handler.
79 */
80 while (pld) {
81 i = ffz(~pld);
82 pld &= pld - 1; /* clear least bit set */
83 if (i < 16) {
84 isa_device_interrupt(vector);
85 } else {
86 handle_irq(i);
87 }
88 }
89 }
90
91 static void __init
mikasa_init_irq(void)92 mikasa_init_irq(void)
93 {
94 long i;
95
96 if (alpha_using_srm)
97 alpha_mv.device_interrupt = srm_device_interrupt;
98
99 mikasa_update_irq_hw(0);
100
101 for (i = 16; i < 32; ++i) {
102 irq_set_chip_and_handler(i, &mikasa_irq_type,
103 handle_level_irq);
104 irq_set_status_flags(i, IRQ_LEVEL);
105 }
106
107 init_i8259a_irqs();
108 common_init_isa_dma();
109 }
110
111
112 /*
113 * PCI Fixup configuration.
114 *
115 * Summary @ 0x536:
116 * Bit Meaning
117 * 0 Interrupt Line A from slot 0
118 * 1 Interrupt Line B from slot 0
119 * 2 Interrupt Line C from slot 0
120 * 3 Interrupt Line D from slot 0
121 * 4 Interrupt Line A from slot 1
122 * 5 Interrupt line B from slot 1
123 * 6 Interrupt Line C from slot 1
124 * 7 Interrupt Line D from slot 1
125 * 8 Interrupt Line A from slot 2
126 * 9 Interrupt Line B from slot 2
127 *10 Interrupt Line C from slot 2
128 *11 Interrupt Line D from slot 2
129 *12 NCR 810 SCSI
130 *13 Power Supply Fail
131 *14 Temperature Warn
132 *15 Reserved
133 *
134 * The device to slot mapping looks like:
135 *
136 * Slot Device
137 * 6 NCR SCSI controller
138 * 7 Intel PCI-EISA bridge chip
139 * 11 PCI on board slot 0
140 * 12 PCI on board slot 1
141 * 13 PCI on board slot 2
142 *
143 *
144 * This two layered interrupt approach means that we allocate IRQ 16 and
145 * above for PCI interrupts. The IRQ relates to which bit the interrupt
146 * comes in on. This makes interrupt processing much easier.
147 */
148
149 static int
mikasa_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)150 mikasa_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
151 {
152 static char irq_tab[8][5] = {
153 /*INT INTA INTB INTC INTD */
154 {16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 17, SCSI */
155 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
156 { -1, -1, -1, -1, -1}, /* IdSel 19, ???? */
157 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
158 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
159 { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */
160 { 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
161 { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */
162 };
163 const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
164 return COMMON_TABLE_LOOKUP;
165 }
166
167
168 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
169 static void
mikasa_apecs_machine_check(unsigned long vector,unsigned long la_ptr)170 mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
171 {
172 #define MCHK_NO_DEVSEL 0x205U
173 #define MCHK_NO_TABT 0x204U
174
175 struct el_common *mchk_header;
176 unsigned int code;
177
178 mchk_header = (struct el_common *)la_ptr;
179
180 /* Clear the error before any reporting. */
181 mb();
182 mb(); /* magic */
183 draina();
184 apecs_pci_clr_err();
185 wrmces(0x7);
186 mb();
187
188 code = mchk_header->code;
189 process_mcheck_info(vector, la_ptr, "MIKASA APECS",
190 (mcheck_expected(0)
191 && (code == MCHK_NO_DEVSEL
192 || code == MCHK_NO_TABT)));
193 }
194 #endif
195
196
197 /*
198 * The System Vector
199 */
200
201 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
202 struct alpha_machine_vector mikasa_mv __initmv = {
203 .vector_name = "Mikasa",
204 DO_EV4_MMU,
205 DO_DEFAULT_RTC,
206 DO_APECS_IO,
207 .machine_check = mikasa_apecs_machine_check,
208 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
209 .min_io_address = DEFAULT_IO_BASE,
210 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
211
212 .nr_irqs = 32,
213 .device_interrupt = mikasa_device_interrupt,
214
215 .init_arch = apecs_init_arch,
216 .init_irq = mikasa_init_irq,
217 .init_rtc = common_init_rtc,
218 .init_pci = common_init_pci,
219 .pci_map_irq = mikasa_map_irq,
220 .pci_swizzle = common_swizzle,
221 };
222 ALIAS_MV(mikasa)
223 #endif
224
225 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
226 struct alpha_machine_vector mikasa_primo_mv __initmv = {
227 .vector_name = "Mikasa-Primo",
228 DO_EV5_MMU,
229 DO_DEFAULT_RTC,
230 DO_CIA_IO,
231 .machine_check = cia_machine_check,
232 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
233 .min_io_address = DEFAULT_IO_BASE,
234 .min_mem_address = CIA_DEFAULT_MEM_BASE,
235
236 .nr_irqs = 32,
237 .device_interrupt = mikasa_device_interrupt,
238
239 .init_arch = cia_init_arch,
240 .init_irq = mikasa_init_irq,
241 .init_rtc = common_init_rtc,
242 .init_pci = cia_init_pci,
243 .kill_arch = cia_kill_arch,
244 .pci_map_irq = mikasa_map_irq,
245 .pci_swizzle = common_swizzle,
246 };
247 ALIAS_MV(mikasa_primo)
248 #endif
249