1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) 4 */ 5/dts-v1/; 6 7/include/ "skeleton.dtsi" 8 9/ { 10 model = "snps,nsim"; 11 compatible = "snps,nsim"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 interrupt-parent = <&core_intc>; 15 16 chosen { 17 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1"; 18 }; 19 20 aliases { 21 serial0 = &arcuart0; 22 }; 23 24 fpga { 25 compatible = "simple-bus"; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 29 /* child and parent address space 1:1 mapped */ 30 ranges; 31 32 core_clk: core_clk { 33 #clock-cells = <0>; 34 compatible = "fixed-clock"; 35 clock-frequency = <80000000>; 36 }; 37 38 core_intc: interrupt-controller { 39 compatible = "snps,arc700-intc"; 40 interrupt-controller; 41 #interrupt-cells = <1>; 42 }; 43 44 arcuart0: serial@c0fc1000 { 45 compatible = "snps,arc-uart"; 46 reg = <0xc0fc1000 0x100>; 47 interrupts = <5>; 48 clock-frequency = <80000000>; 49 current-speed = <115200>; 50 status = "okay"; 51 }; 52 53 ethernet@c0fc2000 { 54 compatible = "snps,arc-emac"; 55 reg = <0xc0fc2000 0x3c>; 56 interrupts = <6>; 57 mac-address = [ 00 11 22 33 44 55 ]; 58 clock-frequency = <80000000>; 59 max-speed = <100>; 60 phy = <&phy0>; 61 62 #address-cells = <1>; 63 #size-cells = <0>; 64 phy0: ethernet-phy@0 { 65 reg = <1>; 66 }; 67 }; 68 69 arcpct0: pct { 70 compatible = "snps,arc700-pct"; 71 }; 72 }; 73}; 74