1/* 2 * Device Tree Source for AM4372 SoC 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/am4.h> 15 16/ { 17 compatible = "ti,am4372", "ti,am43"; 18 interrupt-parent = <&wakeupgen>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 aliases { 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 ethernet0 = &cpsw_emac0; 39 ethernet1 = &cpsw_emac1; 40 spi0 = &qspi; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu: cpu@0 { 47 compatible = "arm,cortex-a9"; 48 device_type = "cpu"; 49 reg = <0>; 50 51 clocks = <&dpll_mpu_ck>; 52 clock-names = "cpu"; 53 54 operating-points-v2 = <&cpu0_opp_table>; 55 56 clock-latency = <300000>; /* From omap-cpufreq driver */ 57 }; 58 }; 59 60 cpu0_opp_table: opp-table { 61 compatible = "operating-points-v2-ti-cpu"; 62 syscon = <&scm_conf>; 63 64 opp50-300000000 { 65 opp-hz = /bits/ 64 <300000000>; 66 opp-microvolt = <950000 931000 969000>; 67 opp-supported-hw = <0xFF 0x01>; 68 opp-suspend; 69 }; 70 71 opp100-600000000 { 72 opp-hz = /bits/ 64 <600000000>; 73 opp-microvolt = <1100000 1078000 1122000>; 74 opp-supported-hw = <0xFF 0x04>; 75 }; 76 77 opp120-720000000 { 78 opp-hz = /bits/ 64 <720000000>; 79 opp-microvolt = <1200000 1176000 1224000>; 80 opp-supported-hw = <0xFF 0x08>; 81 }; 82 83 oppturbo-800000000 { 84 opp-hz = /bits/ 64 <800000000>; 85 opp-microvolt = <1260000 1234800 1285200>; 86 opp-supported-hw = <0xFF 0x10>; 87 }; 88 89 oppnitro-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = <1325000 1298500 1351500>; 92 opp-supported-hw = <0xFF 0x20>; 93 }; 94 }; 95 96 soc { 97 compatible = "ti,omap-infra"; 98 mpu { 99 compatible = "ti,omap4-mpu"; 100 ti,hwmods = "mpu"; 101 pm-sram = <&pm_sram_code 102 &pm_sram_data>; 103 }; 104 }; 105 106 gic: interrupt-controller@48241000 { 107 compatible = "arm,cortex-a9-gic"; 108 interrupt-controller; 109 #interrupt-cells = <3>; 110 reg = <0x48241000 0x1000>, 111 <0x48240100 0x0100>; 112 interrupt-parent = <&gic>; 113 }; 114 115 wakeupgen: interrupt-controller@48281000 { 116 compatible = "ti,omap4-wugen-mpu"; 117 interrupt-controller; 118 #interrupt-cells = <3>; 119 reg = <0x48281000 0x1000>; 120 interrupt-parent = <&gic>; 121 }; 122 123 scu: scu@48240000 { 124 compatible = "arm,cortex-a9-scu"; 125 reg = <0x48240000 0x100>; 126 }; 127 128 global_timer: timer@48240200 { 129 compatible = "arm,cortex-a9-global-timer"; 130 reg = <0x48240200 0x100>; 131 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 132 interrupt-parent = <&gic>; 133 clocks = <&mpu_periphclk>; 134 }; 135 136 local_timer: timer@48240600 { 137 compatible = "arm,cortex-a9-twd-timer"; 138 reg = <0x48240600 0x100>; 139 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 140 interrupt-parent = <&gic>; 141 clocks = <&mpu_periphclk>; 142 }; 143 144 l2-cache-controller@48242000 { 145 compatible = "arm,pl310-cache"; 146 reg = <0x48242000 0x1000>; 147 cache-unified; 148 cache-level = <2>; 149 }; 150 151 ocp@44000000 { 152 compatible = "ti,am4372-l3-noc", "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 ti,hwmods = "l3_main"; 157 ti,no-idle; 158 reg = <0x44000000 0x400000 159 0x44800000 0x400000>; 160 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 162 163 l4_wkup: interconnect@44c00000 { 164 wkup_m3: wkup_m3@100000 { 165 compatible = "ti,am4372-wkup-m3"; 166 reg = <0x100000 0x4000>, 167 <0x180000 0x2000>; 168 reg-names = "umem", "dmem"; 169 ti,hwmods = "wkup_m3"; 170 ti,pm-firmware = "am335x-pm-firmware.elf"; 171 }; 172 }; 173 l4_per: interconnect@48000000 { 174 }; 175 l4_fast: interconnect@4a000000 { 176 }; 177 178 emif: emif@4c000000 { 179 compatible = "ti,emif-am4372"; 180 reg = <0x4c000000 0x1000000>; 181 ti,hwmods = "emif"; 182 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 183 ti,no-idle; 184 sram = <&pm_sram_code 185 &pm_sram_data>; 186 }; 187 188 edma: edma@49000000 { 189 compatible = "ti,edma3-tpcc"; 190 ti,hwmods = "tpcc"; 191 reg = <0x49000000 0x10000>; 192 reg-names = "edma3_cc"; 193 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-names = "edma3_ccint", "edma3_mperr", 197 "edma3_ccerrint"; 198 dma-requests = <64>; 199 #dma-cells = <2>; 200 201 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 202 <&edma_tptc2 0>; 203 204 ti,edma-memcpy-channels = <58 59>; 205 }; 206 207 edma_tptc0: tptc@49800000 { 208 compatible = "ti,edma3-tptc"; 209 ti,hwmods = "tptc0"; 210 reg = <0x49800000 0x100000>; 211 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "edma3_tcerrint"; 213 }; 214 215 edma_tptc1: tptc@49900000 { 216 compatible = "ti,edma3-tptc"; 217 ti,hwmods = "tptc1"; 218 reg = <0x49900000 0x100000>; 219 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-names = "edma3_tcerrint"; 221 }; 222 223 edma_tptc2: tptc@49a00000 { 224 compatible = "ti,edma3-tptc"; 225 ti,hwmods = "tptc2"; 226 reg = <0x49a00000 0x100000>; 227 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 228 interrupt-names = "edma3_tcerrint"; 229 }; 230 231 target-module@47810000 { 232 compatible = "ti,sysc-omap2", "ti,sysc"; 233 ti,hwmods = "mmc3"; 234 reg = <0x478102fc 0x4>, 235 <0x47810110 0x4>, 236 <0x47810114 0x4>; 237 reg-names = "rev", "sysc", "syss"; 238 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 239 SYSC_OMAP2_ENAWAKEUP | 240 SYSC_OMAP2_SOFTRESET | 241 SYSC_OMAP2_AUTOIDLE)>; 242 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 243 <SYSC_IDLE_NO>, 244 <SYSC_IDLE_SMART>; 245 ti,syss-mask = <1>; 246 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; 247 clock-names = "fck"; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0x0 0x47810000 0x1000>; 251 252 mmc3: mmc@0 { 253 compatible = "ti,omap4-hsmmc"; 254 ti,needs-special-reset; 255 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 256 reg = <0x0 0x1000>; 257 }; 258 }; 259 260 sham: sham@53100000 { 261 compatible = "ti,omap5-sham"; 262 ti,hwmods = "sham"; 263 reg = <0x53100000 0x300>; 264 dmas = <&edma 36 0>; 265 dma-names = "rx"; 266 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 267 }; 268 269 aes: aes@53501000 { 270 compatible = "ti,omap4-aes"; 271 ti,hwmods = "aes"; 272 reg = <0x53501000 0xa0>; 273 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 274 dmas = <&edma 6 0>, 275 <&edma 5 0>; 276 dma-names = "tx", "rx"; 277 }; 278 279 des: des@53701000 { 280 compatible = "ti,omap4-des"; 281 ti,hwmods = "des"; 282 reg = <0x53701000 0xa0>; 283 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 284 dmas = <&edma 34 0>, 285 <&edma 33 0>; 286 dma-names = "tx", "rx"; 287 }; 288 289 gpmc: gpmc@50000000 { 290 compatible = "ti,am3352-gpmc"; 291 ti,hwmods = "gpmc"; 292 dmas = <&edma 52 0>; 293 dma-names = "rxtx"; 294 clocks = <&l3s_gclk>; 295 clock-names = "fck"; 296 reg = <0x50000000 0x2000>; 297 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 298 gpmc,num-cs = <7>; 299 gpmc,num-waitpins = <2>; 300 #address-cells = <2>; 301 #size-cells = <1>; 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 status = "disabled"; 307 }; 308 309 qspi: spi@47900000 { 310 compatible = "ti,am4372-qspi"; 311 reg = <0x47900000 0x100>, 312 <0x30000000 0x4000000>; 313 reg-names = "qspi_base", "qspi_mmap"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 ti,hwmods = "qspi"; 317 interrupts = <0 138 0x4>; 318 num-cs = <4>; 319 status = "disabled"; 320 }; 321 322 dss: dss@4832a000 { 323 compatible = "ti,omap3-dss"; 324 reg = <0x4832a000 0x200>; 325 status = "disabled"; 326 ti,hwmods = "dss_core"; 327 clocks = <&disp_clk>; 328 clock-names = "fck"; 329 #address-cells = <1>; 330 #size-cells = <1>; 331 ranges; 332 333 dispc: dispc@4832a400 { 334 compatible = "ti,omap3-dispc"; 335 reg = <0x4832a400 0x400>; 336 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 337 ti,hwmods = "dss_dispc"; 338 clocks = <&disp_clk>; 339 clock-names = "fck"; 340 341 max-memory-bandwidth = <230000000>; 342 }; 343 344 rfbi: rfbi@4832a800 { 345 compatible = "ti,omap3-rfbi"; 346 reg = <0x4832a800 0x100>; 347 ti,hwmods = "dss_rfbi"; 348 clocks = <&disp_clk>; 349 clock-names = "fck"; 350 status = "disabled"; 351 }; 352 }; 353 354 ocmcram: ocmcram@40300000 { 355 compatible = "mmio-sram"; 356 reg = <0x40300000 0x40000>; /* 256k */ 357 ranges = <0x0 0x40300000 0x40000>; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 361 pm_sram_code: pm-sram-code@0 { 362 compatible = "ti,sram"; 363 reg = <0x0 0x1000>; 364 protect-exec; 365 }; 366 367 pm_sram_data: pm-sram-data@1000 { 368 compatible = "ti,sram"; 369 reg = <0x1000 0x1000>; 370 pool; 371 }; 372 }; 373 }; 374}; 375 376#include "am437x-l4.dtsi" 377#include "am43xx-clocks.dtsi" 378