1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 38x family of SoCs. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 */ 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 model = "Marvell Armada 38x family SoC"; 22 compatible = "marvell,armada380"; 23 24 aliases { 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 }; 30 31 pmu { 32 compatible = "arm,cortex-a9-pmu"; 33 interrupts-extended = <&mpic 3>; 34 }; 35 36 soc { 37 compatible = "marvell,armada380-mbus", "simple-bus"; 38 #address-cells = <2>; 39 #size-cells = <1>; 40 controller = <&mbusc>; 41 interrupt-parent = <&gic>; 42 pcie-mem-aperture = <0xe0000000 0x8000000>; 43 pcie-io-aperture = <0xe8000000 0x100000>; 44 45 bootrom { 46 compatible = "marvell,bootrom"; 47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 48 }; 49 50 devbus_bootcs: devbus-bootcs { 51 compatible = "marvell,mvebu-devbus"; 52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 clocks = <&coreclk 0>; 57 status = "disabled"; 58 }; 59 60 devbus_cs0: devbus-cs0 { 61 compatible = "marvell,mvebu-devbus"; 62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 clocks = <&coreclk 0>; 67 status = "disabled"; 68 }; 69 70 devbus_cs1: devbus-cs1 { 71 compatible = "marvell,mvebu-devbus"; 72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 clocks = <&coreclk 0>; 77 status = "disabled"; 78 }; 79 80 devbus_cs2: devbus-cs2 { 81 compatible = "marvell,mvebu-devbus"; 82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 clocks = <&coreclk 0>; 87 status = "disabled"; 88 }; 89 90 devbus_cs3: devbus-cs3 { 91 compatible = "marvell,mvebu-devbus"; 92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 clocks = <&coreclk 0>; 97 status = "disabled"; 98 }; 99 100 internal-regs { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 105 106 L2: cache-controller@8000 { 107 compatible = "arm,pl310-cache"; 108 reg = <0x8000 0x1000>; 109 cache-unified; 110 cache-level = <2>; 111 arm,double-linefill-incr = <0>; 112 arm,double-linefill-wrap = <0>; 113 arm,double-linefill = <0>; 114 prefetch-data = <1>; 115 }; 116 117 scu@c000 { 118 compatible = "arm,cortex-a9-scu"; 119 reg = <0xc000 0x58>; 120 }; 121 122 timer@c200 { 123 compatible = "arm,cortex-a9-global-timer"; 124 reg = <0xc200 0x20>; 125 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 126 clocks = <&coreclk 2>; 127 }; 128 129 timer@c600 { 130 compatible = "arm,cortex-a9-twd-timer"; 131 reg = <0xc600 0x20>; 132 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 133 clocks = <&coreclk 2>; 134 }; 135 136 gic: interrupt-controller@d000 { 137 compatible = "arm,cortex-a9-gic"; 138 #interrupt-cells = <3>; 139 #size-cells = <0>; 140 interrupt-controller; 141 reg = <0xd000 0x1000>, 142 <0xc100 0x100>; 143 }; 144 145 i2c0: i2c@11000 { 146 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 147 reg = <0x11000 0x20>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 151 timeout-ms = <1000>; 152 clocks = <&coreclk 0>; 153 status = "disabled"; 154 }; 155 156 i2c1: i2c@11100 { 157 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 158 reg = <0x11100 0x20>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 162 timeout-ms = <1000>; 163 clocks = <&coreclk 0>; 164 status = "disabled"; 165 }; 166 167 uart0: serial@12000 { 168 compatible = "marvell,armada-38x-uart", "ns16550a"; 169 reg = <0x12000 0x100>; 170 reg-shift = <2>; 171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 172 reg-io-width = <1>; 173 clocks = <&coreclk 0>; 174 status = "disabled"; 175 }; 176 177 uart1: serial@12100 { 178 compatible = "marvell,armada-38x-uart", "ns16550a"; 179 reg = <0x12100 0x100>; 180 reg-shift = <2>; 181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 182 reg-io-width = <1>; 183 clocks = <&coreclk 0>; 184 status = "disabled"; 185 }; 186 187 pinctrl: pinctrl@18000 { 188 reg = <0x18000 0x20>; 189 190 ge0_rgmii_pins: ge-rgmii-pins-0 { 191 marvell,pins = "mpp6", "mpp7", "mpp8", 192 "mpp9", "mpp10", "mpp11", 193 "mpp12", "mpp13", "mpp14", 194 "mpp15", "mpp16", "mpp17"; 195 marvell,function = "ge0"; 196 }; 197 198 ge1_rgmii_pins: ge-rgmii-pins-1 { 199 marvell,pins = "mpp21", "mpp27", "mpp28", 200 "mpp29", "mpp30", "mpp31", 201 "mpp32", "mpp37", "mpp38", 202 "mpp39", "mpp40", "mpp41"; 203 marvell,function = "ge1"; 204 }; 205 206 i2c0_pins: i2c-pins-0 { 207 marvell,pins = "mpp2", "mpp3"; 208 marvell,function = "i2c0"; 209 }; 210 211 mdio_pins: mdio-pins { 212 marvell,pins = "mpp4", "mpp5"; 213 marvell,function = "ge"; 214 }; 215 216 ref_clk0_pins: ref-clk-pins-0 { 217 marvell,pins = "mpp45"; 218 marvell,function = "ref"; 219 }; 220 221 ref_clk1_pins: ref-clk-pins-1 { 222 marvell,pins = "mpp46"; 223 marvell,function = "ref"; 224 }; 225 226 spi0_pins: spi-pins-0 { 227 marvell,pins = "mpp22", "mpp23", "mpp24", 228 "mpp25"; 229 marvell,function = "spi0"; 230 }; 231 232 spi1_pins: spi-pins-1 { 233 marvell,pins = "mpp56", "mpp57", "mpp58", 234 "mpp59"; 235 marvell,function = "spi1"; 236 }; 237 238 nand_pins: nand-pins { 239 marvell,pins = "mpp22", "mpp34", "mpp23", 240 "mpp33", "mpp38", "mpp28", 241 "mpp40", "mpp42", "mpp35", 242 "mpp36", "mpp25", "mpp30", 243 "mpp32"; 244 marvell,function = "dev"; 245 }; 246 247 nand_rb: nand-rb { 248 marvell,pins = "mpp41"; 249 marvell,function = "nand"; 250 }; 251 252 uart0_pins: uart-pins-0 { 253 marvell,pins = "mpp0", "mpp1"; 254 marvell,function = "ua0"; 255 }; 256 257 uart1_pins: uart-pins-1 { 258 marvell,pins = "mpp19", "mpp20"; 259 marvell,function = "ua1"; 260 }; 261 262 sdhci_pins: sdhci-pins { 263 marvell,pins = "mpp48", "mpp49", "mpp50", 264 "mpp52", "mpp53", "mpp54", 265 "mpp55", "mpp57", "mpp58", 266 "mpp59"; 267 marvell,function = "sd0"; 268 }; 269 270 sata0_pins: sata-pins-0 { 271 marvell,pins = "mpp20"; 272 marvell,function = "sata0"; 273 }; 274 275 sata1_pins: sata-pins-1 { 276 marvell,pins = "mpp19"; 277 marvell,function = "sata1"; 278 }; 279 280 sata2_pins: sata-pins-2 { 281 marvell,pins = "mpp47"; 282 marvell,function = "sata2"; 283 }; 284 285 sata3_pins: sata-pins-3 { 286 marvell,pins = "mpp44"; 287 marvell,function = "sata3"; 288 }; 289 }; 290 291 gpio0: gpio@18100 { 292 compatible = "marvell,armada-370-gpio", 293 "marvell,orion-gpio"; 294 reg = <0x18100 0x40>, <0x181c0 0x08>; 295 reg-names = "gpio", "pwm"; 296 ngpios = <32>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 #pwm-cells = <2>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&coreclk 0>; 307 }; 308 309 gpio1: gpio@18140 { 310 compatible = "marvell,armada-370-gpio", 311 "marvell,orion-gpio"; 312 reg = <0x18140 0x40>, <0x181c8 0x08>; 313 reg-names = "gpio", "pwm"; 314 ngpios = <28>; 315 gpio-controller; 316 #gpio-cells = <2>; 317 #pwm-cells = <2>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&coreclk 0>; 325 }; 326 327 systemc: system-controller@18200 { 328 compatible = "marvell,armada-380-system-controller", 329 "marvell,armada-370-xp-system-controller"; 330 reg = <0x18200 0x100>; 331 }; 332 333 gateclk: clock-gating-control@18220 { 334 compatible = "marvell,armada-380-gating-clock"; 335 reg = <0x18220 0x4>; 336 clocks = <&coreclk 0>; 337 #clock-cells = <1>; 338 }; 339 340 comphy: phy@18300 { 341 compatible = "marvell,armada-380-comphy"; 342 reg-names = "comphy", "conf"; 343 reg = <0x18300 0x100>, <0x18460 4>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 comphy0: phy@0 { 348 reg = <0>; 349 #phy-cells = <1>; 350 }; 351 352 comphy1: phy@1 { 353 reg = <1>; 354 #phy-cells = <1>; 355 }; 356 357 comphy2: phy@2 { 358 reg = <2>; 359 #phy-cells = <1>; 360 }; 361 362 comphy3: phy@3 { 363 reg = <3>; 364 #phy-cells = <1>; 365 }; 366 367 comphy4: phy@4 { 368 reg = <4>; 369 #phy-cells = <1>; 370 }; 371 372 comphy5: phy@5 { 373 reg = <5>; 374 #phy-cells = <1>; 375 }; 376 }; 377 378 coreclk: mvebu-sar@18600 { 379 compatible = "marvell,armada-380-core-clock"; 380 reg = <0x18600 0x04>; 381 #clock-cells = <1>; 382 }; 383 384 mbusc: mbus-controller@20000 { 385 compatible = "marvell,mbus-controller"; 386 reg = <0x20000 0x100>, <0x20180 0x20>, 387 <0x20250 0x8>; 388 }; 389 390 mpic: interrupt-controller@20a00 { 391 compatible = "marvell,mpic"; 392 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 393 #interrupt-cells = <1>; 394 #size-cells = <1>; 395 interrupt-controller; 396 msi-controller; 397 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 398 }; 399 400 timer: timer@20300 { 401 compatible = "marvell,armada-380-timer", 402 "marvell,armada-xp-timer"; 403 reg = <0x20300 0x30>, <0x21040 0x30>; 404 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 405 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 406 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 407 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 408 <&mpic 5>, 409 <&mpic 6>; 410 clocks = <&coreclk 2>, <&refclk>; 411 clock-names = "nbclk", "fixed"; 412 }; 413 414 watchdog: watchdog@20300 { 415 compatible = "marvell,armada-380-wdt"; 416 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 417 clocks = <&coreclk 2>, <&refclk>; 418 clock-names = "nbclk", "fixed"; 419 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 420 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 421 }; 422 423 cpurst: cpurst@20800 { 424 compatible = "marvell,armada-370-cpu-reset"; 425 reg = <0x20800 0x10>; 426 }; 427 428 mpcore-soc-ctrl@20d20 { 429 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 430 reg = <0x20d20 0x6c>; 431 }; 432 433 coherencyfab: coherency-fabric@21010 { 434 compatible = "marvell,armada-380-coherency-fabric"; 435 reg = <0x21010 0x1c>; 436 }; 437 438 pmsu: pmsu@22000 { 439 compatible = "marvell,armada-380-pmsu"; 440 reg = <0x22000 0x1000>; 441 }; 442 443 /* 444 * As a special exception to the "order by 445 * register address" rule, the eth0 node is 446 * placed here to ensure that it gets 447 * registered as the first interface, since 448 * the network subsystem doesn't allow naming 449 * interfaces using DT aliases. Without this, 450 * the ordering of interfaces is different 451 * from the one used in U-Boot and the 452 * labeling of interfaces on the boards, which 453 * is very confusing for users. 454 */ 455 eth0: ethernet@70000 { 456 compatible = "marvell,armada-370-neta"; 457 reg = <0x70000 0x4000>; 458 interrupts-extended = <&mpic 8>; 459 clocks = <&gateclk 4>; 460 tx-csum-limit = <9800>; 461 status = "disabled"; 462 }; 463 464 eth1: ethernet@30000 { 465 compatible = "marvell,armada-370-neta"; 466 reg = <0x30000 0x4000>; 467 interrupts-extended = <&mpic 10>; 468 clocks = <&gateclk 3>; 469 status = "disabled"; 470 }; 471 472 eth2: ethernet@34000 { 473 compatible = "marvell,armada-370-neta"; 474 reg = <0x34000 0x4000>; 475 interrupts-extended = <&mpic 12>; 476 clocks = <&gateclk 2>; 477 status = "disabled"; 478 }; 479 480 usb0: usb@58000 { 481 compatible = "marvell,orion-ehci"; 482 reg = <0x58000 0x500>; 483 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&gateclk 18>; 485 status = "disabled"; 486 }; 487 488 xor0: xor@60800 { 489 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 490 reg = <0x60800 0x100 491 0x60a00 0x100>; 492 clocks = <&gateclk 22>; 493 status = "okay"; 494 495 xor00 { 496 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 497 dmacap,memcpy; 498 dmacap,xor; 499 }; 500 xor01 { 501 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 502 dmacap,memcpy; 503 dmacap,xor; 504 dmacap,memset; 505 }; 506 }; 507 508 xor1: xor@60900 { 509 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 510 reg = <0x60900 0x100 511 0x60b00 0x100>; 512 clocks = <&gateclk 28>; 513 status = "okay"; 514 515 xor10 { 516 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 517 dmacap,memcpy; 518 dmacap,xor; 519 }; 520 xor11 { 521 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 522 dmacap,memcpy; 523 dmacap,xor; 524 dmacap,memset; 525 }; 526 }; 527 528 mdio: mdio@72004 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 compatible = "marvell,orion-mdio"; 532 reg = <0x72004 0x4>; 533 clocks = <&gateclk 4>; 534 }; 535 536 cesa: crypto@90000 { 537 compatible = "marvell,armada-38x-crypto"; 538 reg = <0x90000 0x10000>; 539 reg-names = "regs"; 540 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gateclk 23>, <&gateclk 21>, 543 <&gateclk 14>, <&gateclk 16>; 544 clock-names = "cesa0", "cesa1", 545 "cesaz0", "cesaz1"; 546 marvell,crypto-srams = <&crypto_sram0>, 547 <&crypto_sram1>; 548 marvell,crypto-sram-size = <0x800>; 549 }; 550 551 rtc: rtc@a3800 { 552 compatible = "marvell,armada-380-rtc"; 553 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 554 reg-names = "rtc", "rtc-soc"; 555 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 556 }; 557 558 ahci0: sata@a8000 { 559 compatible = "marvell,armada-380-ahci"; 560 reg = <0xa8000 0x2000>; 561 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&gateclk 15>; 563 status = "disabled"; 564 }; 565 566 bm: bm@c8000 { 567 compatible = "marvell,armada-380-neta-bm"; 568 reg = <0xc8000 0xac>; 569 clocks = <&gateclk 13>; 570 internal-mem = <&bm_bppi>; 571 status = "disabled"; 572 }; 573 574 ahci1: sata@e0000 { 575 compatible = "marvell,armada-380-ahci"; 576 reg = <0xe0000 0x2000>; 577 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&gateclk 30>; 579 status = "disabled"; 580 }; 581 582 coredivclk: clock@e4250 { 583 compatible = "marvell,armada-380-corediv-clock"; 584 reg = <0xe4250 0xc>; 585 #clock-cells = <1>; 586 clocks = <&mainpll>; 587 clock-output-names = "nand"; 588 }; 589 590 thermal: thermal@e8078 { 591 compatible = "marvell,armada380-thermal"; 592 reg = <0xe4078 0x4>, <0xe4070 0x8>; 593 status = "okay"; 594 }; 595 596 nand_controller: nand-controller@d0000 { 597 compatible = "marvell,armada370-nand-controller"; 598 reg = <0xd0000 0x54>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&coredivclk 0>; 603 status = "disabled"; 604 }; 605 606 sdhci: sdhci@d8000 { 607 compatible = "marvell,armada-380-sdhci"; 608 reg-names = "sdhci", "mbus", "conf-sdio3"; 609 reg = <0xd8000 0x1000>, 610 <0xdc000 0x100>, 611 <0x18454 0x4>; 612 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&gateclk 17>; 614 mrvl,clk-delay-cycles = <0x1F>; 615 status = "disabled"; 616 }; 617 618 usb3_0: usb3@f0000 { 619 compatible = "marvell,armada-380-xhci"; 620 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 621 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&gateclk 9>; 623 status = "disabled"; 624 }; 625 626 usb3_1: usb3@f8000 { 627 compatible = "marvell,armada-380-xhci"; 628 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 629 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&gateclk 10>; 631 status = "disabled"; 632 }; 633 }; 634 635 crypto_sram0: sa-sram0 { 636 compatible = "mmio-sram"; 637 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 638 clocks = <&gateclk 23>; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 642 }; 643 644 crypto_sram1: sa-sram1 { 645 compatible = "mmio-sram"; 646 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 647 clocks = <&gateclk 21>; 648 #address-cells = <1>; 649 #size-cells = <1>; 650 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 651 }; 652 653 bm_bppi: bm-bppi { 654 compatible = "mmio-sram"; 655 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 656 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 clocks = <&gateclk 13>; 660 no-memory-wc; 661 status = "disabled"; 662 }; 663 664 spi0: spi@10600 { 665 compatible = "marvell,armada-380-spi", 666 "marvell,orion-spi"; 667 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 cell-index = <0>; 671 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&coreclk 0>; 673 status = "disabled"; 674 }; 675 676 spi1: spi@10680 { 677 compatible = "marvell,armada-380-spi", 678 "marvell,orion-spi"; 679 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 cell-index = <1>; 683 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&coreclk 0>; 685 status = "disabled"; 686 }; 687 }; 688 689 clocks { 690 /* 1 GHz fixed main PLL */ 691 mainpll: mainpll { 692 compatible = "fixed-clock"; 693 #clock-cells = <0>; 694 clock-frequency = <1000000000>; 695 }; 696 697 /* 25 MHz reference crystal */ 698 refclk: oscillator { 699 compatible = "fixed-clock"; 700 #clock-cells = <0>; 701 clock-frequency = <25000000>; 702 }; 703 }; 704}; 705