1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 39x family of SoCs. 4 * 5 * Copyright (C) 2015 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 model = "Marvell Armada 39x family SoC"; 19 compatible = "marvell,armada390"; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 enable-method = "marvell,armada-390-smp"; 34 35 cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a9"; 38 reg = <0>; 39 }; 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a9"; 43 reg = <1>; 44 }; 45 }; 46 47 pmu { 48 compatible = "arm,cortex-a9-pmu"; 49 interrupts-extended = <&mpic 3>; 50 }; 51 52 soc { 53 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", 54 "simple-bus"; 55 #address-cells = <2>; 56 #size-cells = <1>; 57 controller = <&mbusc>; 58 interrupt-parent = <&gic>; 59 pcie-mem-aperture = <0xe0000000 0x8000000>; 60 pcie-io-aperture = <0xe8000000 0x100000>; 61 62 bootrom { 63 compatible = "marvell,bootrom"; 64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 65 }; 66 67 internal-regs { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 72 73 L2: cache-controller@8000 { 74 compatible = "arm,pl310-cache"; 75 reg = <0x8000 0x1000>; 76 cache-unified; 77 cache-level = <2>; 78 arm,double-linefill-incr = <0>; 79 arm,double-linefill-wrap = <0>; 80 arm,double-linefill = <0>; 81 prefetch-data = <1>; 82 }; 83 84 scu@c000 { 85 compatible = "arm,cortex-a9-scu"; 86 reg = <0xc000 0x100>; 87 }; 88 89 timer@c600 { 90 compatible = "arm,cortex-a9-twd-timer"; 91 reg = <0xc600 0x20>; 92 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 93 clocks = <&coreclk 2>; 94 }; 95 96 gic: interrupt-controller@d000 { 97 compatible = "arm,cortex-a9-gic"; 98 #interrupt-cells = <3>; 99 #size-cells = <0>; 100 interrupt-controller; 101 reg = <0xd000 0x1000>, 102 <0xc100 0x100>; 103 }; 104 105 i2c0: i2c@11000 { 106 compatible = "marvell,mv64xxx-i2c"; 107 reg = <0x11000 0x20>; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 111 timeout-ms = <1000>; 112 clocks = <&coreclk 0>; 113 status = "disabled"; 114 }; 115 116 i2c1: i2c@11100 { 117 compatible = "marvell,mv64xxx-i2c"; 118 reg = <0x11100 0x20>; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 122 timeout-ms = <1000>; 123 clocks = <&coreclk 0>; 124 status = "disabled"; 125 }; 126 127 i2c2: i2c@11200 { 128 compatible = "marvell,mv64xxx-i2c"; 129 reg = <0x11200 0x20>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 133 timeout-ms = <1000>; 134 clocks = <&coreclk 0>; 135 status = "disabled"; 136 }; 137 138 i2c3: i2c@11300 { 139 compatible = "marvell,mv64xxx-i2c"; 140 reg = <0x11300 0x20>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 144 timeout-ms = <1000>; 145 clocks = <&coreclk 0>; 146 status = "disabled"; 147 }; 148 149 uart0: serial@12000 { 150 compatible = "snps,dw-apb-uart"; 151 reg = <0x12000 0x100>; 152 reg-shift = <2>; 153 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 154 reg-io-width = <1>; 155 clocks = <&coreclk 0>; 156 status = "disabled"; 157 }; 158 159 uart1: serial@12100 { 160 compatible = "snps,dw-apb-uart"; 161 reg = <0x12100 0x100>; 162 reg-shift = <2>; 163 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 164 reg-io-width = <1>; 165 clocks = <&coreclk 0>; 166 status = "disabled"; 167 }; 168 169 uart2: serial@12200 { 170 compatible = "snps,dw-apb-uart"; 171 reg = <0x12200 0x100>; 172 reg-shift = <2>; 173 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 174 reg-io-width = <1>; 175 clocks = <&coreclk 0>; 176 status = "disabled"; 177 }; 178 179 uart3: serial@12300 { 180 compatible = "snps,dw-apb-uart"; 181 reg = <0x12300 0x100>; 182 reg-shift = <2>; 183 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 184 reg-io-width = <1>; 185 clocks = <&coreclk 0>; 186 status = "disabled"; 187 }; 188 189 pinctrl@18000 { 190 i2c0_pins: i2c0-pins { 191 marvell,pins = "mpp2", "mpp3"; 192 marvell,function = "i2c0"; 193 }; 194 195 uart0_pins: uart0-pins { 196 marvell,pins = "mpp0", "mpp1"; 197 marvell,function = "ua0"; 198 }; 199 200 uart1_pins: uart1-pins { 201 marvell,pins = "mpp19", "mpp20"; 202 marvell,function = "ua1"; 203 }; 204 205 spi1_pins: spi1-pins { 206 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; 207 marvell,function = "spi1"; 208 }; 209 210 nand_pins: nand-pins { 211 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", 212 "mpp38", "mpp28", "mpp40", "mpp42", 213 "mpp35", "mpp36", "mpp25", "mpp30", 214 "mpp32"; 215 marvell,function = "dev"; 216 }; 217 }; 218 219 gpio0: gpio@18100 { 220 compatible = "marvell,orion-gpio"; 221 reg = <0x18100 0x40>; 222 ngpios = <32>; 223 gpio-controller; 224 #gpio-cells = <2>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 231 }; 232 233 gpio1: gpio@18140 { 234 compatible = "marvell,orion-gpio"; 235 reg = <0x18140 0x40>; 236 ngpios = <28>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 245 }; 246 247 system-controller@18200 { 248 compatible = "marvell,armada-390-system-controller", 249 "marvell,armada-370-xp-system-controller"; 250 reg = <0x18200 0x100>; 251 }; 252 253 gateclk: clock-gating-control@18220 { 254 compatible = "marvell,armada-390-gating-clock"; 255 reg = <0x18220 0x4>; 256 clocks = <&coreclk 0>; 257 #clock-cells = <1>; 258 }; 259 260 coreclk: mvebu-sar@18600 { 261 compatible = "marvell,armada-390-core-clock"; 262 reg = <0x18600 0x04>; 263 #clock-cells = <1>; 264 }; 265 266 mbusc: mbus-controller@20000 { 267 compatible = "marvell,mbus-controller"; 268 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; 269 }; 270 271 mpic: interrupt-controller@20a00 { 272 compatible = "marvell,mpic"; 273 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 274 #interrupt-cells = <1>; 275 #size-cells = <1>; 276 interrupt-controller; 277 msi-controller; 278 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 timer@20300 { 282 compatible = "marvell,armada-380-timer", 283 "marvell,armada-xp-timer"; 284 reg = <0x20300 0x30>, <0x21040 0x30>; 285 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 286 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 287 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 288 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 289 <&mpic 5>, 290 <&mpic 6>; 291 clocks = <&coreclk 2>, <&coreclk 5>; 292 clock-names = "nbclk", "fixed"; 293 }; 294 295 watchdog@20300 { 296 compatible = "marvell,armada-380-wdt"; 297 reg = <0x20300 0x34>, <0x20704 0x4>, 298 <0x18260 0x4>; 299 clocks = <&coreclk 2>, <&refclk>; 300 clock-names = "nbclk", "fixed"; 301 }; 302 303 cpurst@20800 { 304 compatible = "marvell,armada-370-cpu-reset"; 305 reg = <0x20800 0x10>; 306 }; 307 308 mpcore-soc-ctrl@20d20 { 309 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 310 reg = <0x20d20 0x6c>; 311 }; 312 313 coherency-fabric@21010 { 314 compatible = "marvell,armada-380-coherency-fabric"; 315 reg = <0x21010 0x1c>; 316 }; 317 318 pmsu@22000 { 319 compatible = "marvell,armada-390-pmsu", 320 "marvell,armada-380-pmsu"; 321 reg = <0x22000 0x1000>; 322 }; 323 324 xor@60800 { 325 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 326 reg = <0x60800 0x100 327 0x60a00 0x100>; 328 clocks = <&gateclk 22>; 329 status = "okay"; 330 331 xor00 { 332 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 333 dmacap,memcpy; 334 dmacap,xor; 335 }; 336 xor01 { 337 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 338 dmacap,memcpy; 339 dmacap,xor; 340 dmacap,memset; 341 }; 342 }; 343 344 xor@60900 { 345 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 346 reg = <0x60900 0x100 347 0x60b00 0x100>; 348 clocks = <&gateclk 28>; 349 status = "okay"; 350 351 xor10 { 352 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 353 dmacap,memcpy; 354 dmacap,xor; 355 }; 356 xor11 { 357 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 358 dmacap,memcpy; 359 dmacap,xor; 360 dmacap,memset; 361 }; 362 }; 363 364 rtc@a3800 { 365 compatible = "marvell,armada-380-rtc"; 366 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 367 reg-names = "rtc", "rtc-soc"; 368 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 369 }; 370 371 nand_controller: nand-controller@d0000 { 372 compatible = "marvell,armada370-nand-controller"; 373 reg = <0xd0000 0x54>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&coredivclk 0>; 378 status = "disabled"; 379 }; 380 381 sdhci@d8000 { 382 compatible = "marvell,armada-380-sdhci"; 383 reg-names = "sdhci", "mbus", "conf-sdio3"; 384 reg = <0xd8000 0x1000>, 385 <0xdc000 0x100>, 386 <0x18454 0x4>; 387 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&gateclk 17>; 389 mrvl,clk-delay-cycles = <0x1F>; 390 status = "disabled"; 391 }; 392 393 coredivclk: clock@e4250 { 394 compatible = "marvell,armada-390-corediv-clock", 395 "marvell,armada-380-corediv-clock"; 396 reg = <0xe4250 0xc>; 397 #clock-cells = <1>; 398 clocks = <&mainpll>; 399 clock-output-names = "nand"; 400 }; 401 402 thermal@e8078 { 403 compatible = "marvell,armada380-thermal"; 404 reg = <0xe4078 0x4>, <0xe4074 0x4>; 405 status = "okay"; 406 }; 407 }; 408 409 pcie { 410 compatible = "marvell,armada-370-pcie"; 411 status = "disabled"; 412 device_type = "pci"; 413 414 #address-cells = <3>; 415 #size-cells = <2>; 416 417 msi-parent = <&mpic>; 418 bus-range = <0x00 0xff>; 419 420 ranges = 421 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 422 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 423 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 424 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 425 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 426 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 427 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 428 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 429 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 430 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 431 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 432 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 433 434 /* 435 * This port can be either x4 or x1. When 436 * configured in x4 by the bootloader, then 437 * pcie@4,0 is not available. 438 */ 439 pcie@1,0 { 440 device_type = "pci"; 441 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 442 reg = <0x0800 0 0 0 0>; 443 #address-cells = <3>; 444 #size-cells = <2>; 445 #interrupt-cells = <1>; 446 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 447 0x81000000 0 0 0x81000000 0x1 0 1 0>; 448 bus-range = <0x00 0xff>; 449 interrupt-map-mask = <0 0 0 0>; 450 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 451 marvell,pcie-port = <0>; 452 marvell,pcie-lane = <0>; 453 clocks = <&gateclk 8>; 454 status = "disabled"; 455 }; 456 457 /* x1 port */ 458 pcie@2,0 { 459 device_type = "pci"; 460 assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; 461 reg = <0x1000 0 0 0 0>; 462 #address-cells = <3>; 463 #size-cells = <2>; 464 #interrupt-cells = <1>; 465 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 466 0x81000000 0 0 0x81000000 0x2 0 1 0>; 467 bus-range = <0x00 0xff>; 468 interrupt-map-mask = <0 0 0 0>; 469 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 470 marvell,pcie-port = <1>; 471 marvell,pcie-lane = <0>; 472 clocks = <&gateclk 5>; 473 status = "disabled"; 474 }; 475 476 /* x1 port */ 477 pcie@3,0 { 478 device_type = "pci"; 479 assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; 480 reg = <0x1800 0 0 0 0>; 481 #address-cells = <3>; 482 #size-cells = <2>; 483 #interrupt-cells = <1>; 484 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 485 0x81000000 0 0 0x81000000 0x3 0 1 0>; 486 bus-range = <0x00 0xff>; 487 interrupt-map-mask = <0 0 0 0>; 488 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 489 marvell,pcie-port = <2>; 490 marvell,pcie-lane = <0>; 491 clocks = <&gateclk 6>; 492 status = "disabled"; 493 }; 494 495 /* 496 * x1 port only available when pcie@1,0 is 497 * configured as a x1 port 498 */ 499 pcie@4,0 { 500 device_type = "pci"; 501 assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; 502 reg = <0x2000 0 0 0 0>; 503 #address-cells = <3>; 504 #size-cells = <2>; 505 #interrupt-cells = <1>; 506 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 507 0x81000000 0 0 0x81000000 0x4 0 1 0>; 508 bus-range = <0x00 0xff>; 509 interrupt-map-mask = <0 0 0 0>; 510 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 511 marvell,pcie-port = <3>; 512 marvell,pcie-lane = <0>; 513 clocks = <&gateclk 7>; 514 status = "disabled"; 515 }; 516 }; 517 518 spi0: spi@10600 { 519 compatible = "marvell,armada-390-spi", 520 "marvell,orion-spi"; 521 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 cell-index = <0>; 525 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&coreclk 0>; 527 status = "disabled"; 528 }; 529 530 spi1: spi@10680 { 531 compatible = "marvell,armada-390-spi", 532 "marvell,orion-spi"; 533 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 cell-index = <1>; 537 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&coreclk 0>; 539 status = "disabled"; 540 }; 541 }; 542 543 clocks { 544 /* 1 GHz fixed main PLL */ 545 mainpll: mainpll { 546 compatible = "fixed-clock"; 547 #clock-cells = <0>; 548 clock-frequency = <1000000000>; 549 }; 550 551 /* 25 MHz reference crystal */ 552 refclk: oscillator { 553 compatible = "fixed-clock"; 554 #clock-cells = <0>; 555 clock-frequency = <25000000>; 556 }; 557 }; 558}; 559