1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include <dt-bindings/clock/imx6qdl-clock.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 /* 14 * The decompressor and also some bootloaders rely on a 15 * pre-existing /chosen node to be available to insert the 16 * command line and merge other ATAGS info. 17 */ 18 chosen {}; 19 20 aliases { 21 ethernet0 = &fec; 22 can0 = &can1; 23 can1 = &can2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 gpio5 = &gpio6; 30 gpio6 = &gpio7; 31 i2c0 = &i2c1; 32 i2c1 = &i2c2; 33 i2c2 = &i2c3; 34 ipu0 = &ipu1; 35 mmc0 = &usdhc1; 36 mmc1 = &usdhc2; 37 mmc2 = &usdhc3; 38 mmc3 = &usdhc4; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 spi0 = &ecspi1; 45 spi1 = &ecspi2; 46 spi2 = &ecspi3; 47 spi3 = &ecspi4; 48 usb0 = &usbotg; 49 usb1 = &usbh1; 50 usb2 = &usbh2; 51 usb3 = &usbh3; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 clocks { 57 ckil { 58 compatible = "fsl,imx-ckil", "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <32768>; 61 }; 62 63 ckih1 { 64 compatible = "fsl,imx-ckih1", "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 osc { 70 compatible = "fsl,imx-osc", "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <24000000>; 73 }; 74 }; 75 76 tempmon: tempmon { 77 compatible = "fsl,imx6q-tempmon"; 78 interrupt-parent = <&gpc>; 79 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 80 fsl,tempmon = <&anatop>; 81 fsl,tempmon-data = <&ocotp>; 82 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 83 #thermal-sensor-cells = <0>; 84 }; 85 86 ldb: ldb { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 90 gpr = <&gpr>; 91 status = "disabled"; 92 93 lvds-channel@0 { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 reg = <0>; 97 status = "disabled"; 98 99 port@0 { 100 reg = <0>; 101 102 lvds0_mux_0: endpoint { 103 remote-endpoint = <&ipu1_di0_lvds0>; 104 }; 105 }; 106 107 port@1 { 108 reg = <1>; 109 110 lvds0_mux_1: endpoint { 111 remote-endpoint = <&ipu1_di1_lvds0>; 112 }; 113 }; 114 }; 115 116 lvds-channel@1 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 reg = <1>; 120 status = "disabled"; 121 122 port@0 { 123 reg = <0>; 124 125 lvds1_mux_0: endpoint { 126 remote-endpoint = <&ipu1_di0_lvds1>; 127 }; 128 }; 129 130 port@1 { 131 reg = <1>; 132 133 lvds1_mux_1: endpoint { 134 remote-endpoint = <&ipu1_di1_lvds1>; 135 }; 136 }; 137 }; 138 }; 139 140 pmu: pmu { 141 compatible = "arm,cortex-a9-pmu"; 142 interrupt-parent = <&gpc>; 143 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 144 }; 145 146 usbphynop1: usbphynop1 { 147 compatible = "usb-nop-xceiv"; 148 #phy-cells = <0>; 149 }; 150 151 usbphynop2: usbphynop2 { 152 compatible = "usb-nop-xceiv"; 153 #phy-cells = <0>; 154 }; 155 156 soc { 157 #address-cells = <1>; 158 #size-cells = <1>; 159 compatible = "simple-bus"; 160 interrupt-parent = <&gpc>; 161 ranges; 162 163 dma_apbh: dma-controller@110000 { 164 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 165 reg = <0x00110000 0x2000>; 166 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 167 <0 13 IRQ_TYPE_LEVEL_HIGH>, 168 <0 13 IRQ_TYPE_LEVEL_HIGH>, 169 <0 13 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 171 #dma-cells = <1>; 172 dma-channels = <4>; 173 clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 174 }; 175 176 gpmi: gpmi-nand@112000 { 177 compatible = "fsl,imx6q-gpmi-nand"; 178 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 179 reg-names = "gpmi-nand", "bch"; 180 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "bch"; 182 clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 183 <&clks IMX6QDL_CLK_GPMI_APB>, 184 <&clks IMX6QDL_CLK_GPMI_BCH>, 185 <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 186 <&clks IMX6QDL_CLK_PER1_BCH>; 187 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 188 "gpmi_bch_apb", "per1_bch"; 189 dmas = <&dma_apbh 0>; 190 dma-names = "rx-tx"; 191 status = "disabled"; 192 }; 193 194 hdmi: hdmi@120000 { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 reg = <0x00120000 0x9000>; 198 interrupts = <0 115 0x04>; 199 gpr = <&gpr>; 200 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 201 <&clks IMX6QDL_CLK_HDMI_ISFR>; 202 clock-names = "iahb", "isfr"; 203 status = "disabled"; 204 205 port@0 { 206 reg = <0>; 207 208 hdmi_mux_0: endpoint { 209 remote-endpoint = <&ipu1_di0_hdmi>; 210 }; 211 }; 212 213 port@1 { 214 reg = <1>; 215 216 hdmi_mux_1: endpoint { 217 remote-endpoint = <&ipu1_di1_hdmi>; 218 }; 219 }; 220 }; 221 222 gpu_3d: gpu@130000 { 223 compatible = "vivante,gc"; 224 reg = <0x00130000 0x4000>; 225 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, 227 <&clks IMX6QDL_CLK_GPU3D_CORE>, 228 <&clks IMX6QDL_CLK_GPU3D_SHADER>; 229 clock-names = "bus", "core", "shader"; 230 power-domains = <&pd_pu>; 231 #cooling-cells = <2>; 232 }; 233 234 gpu_2d: gpu@134000 { 235 compatible = "vivante,gc"; 236 reg = <0x00134000 0x4000>; 237 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, 239 <&clks IMX6QDL_CLK_GPU2D_CORE>; 240 clock-names = "bus", "core"; 241 power-domains = <&pd_pu>; 242 #cooling-cells = <2>; 243 }; 244 245 timer@a00600 { 246 compatible = "arm,cortex-a9-twd-timer"; 247 reg = <0x00a00600 0x20>; 248 interrupts = <1 13 0xf01>; 249 interrupt-parent = <&intc>; 250 clocks = <&clks IMX6QDL_CLK_TWD>; 251 }; 252 253 intc: interrupt-controller@a01000 { 254 compatible = "arm,cortex-a9-gic"; 255 #interrupt-cells = <3>; 256 interrupt-controller; 257 reg = <0x00a01000 0x1000>, 258 <0x00a00100 0x100>; 259 interrupt-parent = <&intc>; 260 }; 261 262 L2: cache-controller@a02000 { 263 compatible = "arm,pl310-cache"; 264 reg = <0x00a02000 0x1000>; 265 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 266 cache-unified; 267 cache-level = <2>; 268 arm,tag-latency = <4 2 3>; 269 arm,data-latency = <4 2 3>; 270 arm,shared-override; 271 }; 272 273 pcie: pcie@1ffc000 { 274 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 275 reg = <0x01ffc000 0x04000>, 276 <0x01f00000 0x80000>; 277 reg-names = "dbi", "config"; 278 #address-cells = <3>; 279 #size-cells = <2>; 280 device_type = "pci"; 281 bus-range = <0x00 0xff>; 282 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 283 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 284 num-lanes = <1>; 285 num-viewport = <4>; 286 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-names = "msi"; 288 #interrupt-cells = <1>; 289 interrupt-map-mask = <0 0 0 0x7>; 290 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 291 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 292 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 293 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 295 <&clks IMX6QDL_CLK_LVDS1_GATE>, 296 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 297 clock-names = "pcie", "pcie_bus", "pcie_phy"; 298 status = "disabled"; 299 }; 300 301 aips-bus@2000000 { /* AIPS1 */ 302 compatible = "fsl,aips-bus", "simple-bus"; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 reg = <0x02000000 0x100000>; 306 ranges; 307 308 spba-bus@2000000 { 309 compatible = "fsl,spba-bus", "simple-bus"; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 reg = <0x02000000 0x40000>; 313 ranges; 314 315 spdif: spdif@2004000 { 316 compatible = "fsl,imx35-spdif"; 317 reg = <0x02004000 0x4000>; 318 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 319 dmas = <&sdma 14 18 0>, 320 <&sdma 15 18 0>; 321 dma-names = "rx", "tx"; 322 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, 323 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, 324 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, 325 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, 326 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; 327 clock-names = "core", "rxtx0", 328 "rxtx1", "rxtx2", 329 "rxtx3", "rxtx4", 330 "rxtx5", "rxtx6", 331 "rxtx7", "spba"; 332 status = "disabled"; 333 }; 334 335 ecspi1: spi@2008000 { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 339 reg = <0x02008000 0x4000>; 340 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clks IMX6QDL_CLK_ECSPI1>, 342 <&clks IMX6QDL_CLK_ECSPI1>; 343 clock-names = "ipg", "per"; 344 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; 345 dma-names = "rx", "tx"; 346 status = "disabled"; 347 }; 348 349 ecspi2: spi@200c000 { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 353 reg = <0x0200c000 0x4000>; 354 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&clks IMX6QDL_CLK_ECSPI2>, 356 <&clks IMX6QDL_CLK_ECSPI2>; 357 clock-names = "ipg", "per"; 358 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; 359 dma-names = "rx", "tx"; 360 status = "disabled"; 361 }; 362 363 ecspi3: spi@2010000 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 367 reg = <0x02010000 0x4000>; 368 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clks IMX6QDL_CLK_ECSPI3>, 370 <&clks IMX6QDL_CLK_ECSPI3>; 371 clock-names = "ipg", "per"; 372 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; 373 dma-names = "rx", "tx"; 374 status = "disabled"; 375 }; 376 377 ecspi4: spi@2014000 { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 381 reg = <0x02014000 0x4000>; 382 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&clks IMX6QDL_CLK_ECSPI4>, 384 <&clks IMX6QDL_CLK_ECSPI4>; 385 clock-names = "ipg", "per"; 386 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; 387 dma-names = "rx", "tx"; 388 status = "disabled"; 389 }; 390 391 uart1: serial@2020000 { 392 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 393 reg = <0x02020000 0x4000>; 394 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 396 <&clks IMX6QDL_CLK_UART_SERIAL>; 397 clock-names = "ipg", "per"; 398 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 399 dma-names = "rx", "tx"; 400 status = "disabled"; 401 }; 402 403 esai: esai@2024000 { 404 #sound-dai-cells = <0>; 405 compatible = "fsl,imx35-esai"; 406 reg = <0x02024000 0x4000>; 407 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, 409 <&clks IMX6QDL_CLK_ESAI_MEM>, 410 <&clks IMX6QDL_CLK_ESAI_EXTAL>, 411 <&clks IMX6QDL_CLK_ESAI_IPG>, 412 <&clks IMX6QDL_CLK_SPBA>; 413 clock-names = "core", "mem", "extal", "fsys", "spba"; 414 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 415 dma-names = "rx", "tx"; 416 status = "disabled"; 417 }; 418 419 ssi1: ssi@2028000 { 420 #sound-dai-cells = <0>; 421 compatible = "fsl,imx6q-ssi", 422 "fsl,imx51-ssi"; 423 reg = <0x02028000 0x4000>; 424 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 426 <&clks IMX6QDL_CLK_SSI1>; 427 clock-names = "ipg", "baud"; 428 dmas = <&sdma 37 1 0>, 429 <&sdma 38 1 0>; 430 dma-names = "rx", "tx"; 431 fsl,fifo-depth = <15>; 432 status = "disabled"; 433 }; 434 435 ssi2: ssi@202c000 { 436 #sound-dai-cells = <0>; 437 compatible = "fsl,imx6q-ssi", 438 "fsl,imx51-ssi"; 439 reg = <0x0202c000 0x4000>; 440 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, 442 <&clks IMX6QDL_CLK_SSI2>; 443 clock-names = "ipg", "baud"; 444 dmas = <&sdma 41 1 0>, 445 <&sdma 42 1 0>; 446 dma-names = "rx", "tx"; 447 fsl,fifo-depth = <15>; 448 status = "disabled"; 449 }; 450 451 ssi3: ssi@2030000 { 452 #sound-dai-cells = <0>; 453 compatible = "fsl,imx6q-ssi", 454 "fsl,imx51-ssi"; 455 reg = <0x02030000 0x4000>; 456 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, 458 <&clks IMX6QDL_CLK_SSI3>; 459 clock-names = "ipg", "baud"; 460 dmas = <&sdma 45 1 0>, 461 <&sdma 46 1 0>; 462 dma-names = "rx", "tx"; 463 fsl,fifo-depth = <15>; 464 status = "disabled"; 465 }; 466 467 asrc: asrc@2034000 { 468 compatible = "fsl,imx53-asrc"; 469 reg = <0x02034000 0x4000>; 470 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, 472 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, 473 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 474 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 475 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 476 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, 477 <&clks IMX6QDL_CLK_SPBA>; 478 clock-names = "mem", "ipg", "asrck_0", 479 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 480 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 481 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 482 "asrck_d", "asrck_e", "asrck_f", "spba"; 483 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 484 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 485 dma-names = "rxa", "rxb", "rxc", 486 "txa", "txb", "txc"; 487 fsl,asrc-rate = <48000>; 488 fsl,asrc-width = <16>; 489 status = "okay"; 490 }; 491 492 spba@203c000 { 493 reg = <0x0203c000 0x4000>; 494 }; 495 }; 496 497 vpu: vpu@2040000 { 498 compatible = "cnm,coda960"; 499 reg = <0x02040000 0x3c000>; 500 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, 501 <0 3 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "bit", "jpeg"; 503 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 504 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; 505 clock-names = "per", "ahb"; 506 power-domains = <&pd_pu>; 507 resets = <&src 1>; 508 iram = <&ocram>; 509 }; 510 511 aipstz@207c000 { /* AIPSTZ1 */ 512 reg = <0x0207c000 0x4000>; 513 }; 514 515 pwm1: pwm@2080000 { 516 #pwm-cells = <2>; 517 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 518 reg = <0x02080000 0x4000>; 519 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clks IMX6QDL_CLK_IPG>, 521 <&clks IMX6QDL_CLK_PWM1>; 522 clock-names = "ipg", "per"; 523 status = "disabled"; 524 }; 525 526 pwm2: pwm@2084000 { 527 #pwm-cells = <2>; 528 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 529 reg = <0x02084000 0x4000>; 530 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clks IMX6QDL_CLK_IPG>, 532 <&clks IMX6QDL_CLK_PWM2>; 533 clock-names = "ipg", "per"; 534 status = "disabled"; 535 }; 536 537 pwm3: pwm@2088000 { 538 #pwm-cells = <2>; 539 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 540 reg = <0x02088000 0x4000>; 541 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clks IMX6QDL_CLK_IPG>, 543 <&clks IMX6QDL_CLK_PWM3>; 544 clock-names = "ipg", "per"; 545 status = "disabled"; 546 }; 547 548 pwm4: pwm@208c000 { 549 #pwm-cells = <2>; 550 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 551 reg = <0x0208c000 0x4000>; 552 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clks IMX6QDL_CLK_IPG>, 554 <&clks IMX6QDL_CLK_PWM4>; 555 clock-names = "ipg", "per"; 556 status = "disabled"; 557 }; 558 559 can1: flexcan@2090000 { 560 compatible = "fsl,imx6q-flexcan"; 561 reg = <0x02090000 0x4000>; 562 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 564 <&clks IMX6QDL_CLK_CAN1_SERIAL>; 565 clock-names = "ipg", "per"; 566 fsl,stop-mode = <&gpr 0x34 28 0x10 17>; 567 status = "disabled"; 568 }; 569 570 can2: flexcan@2094000 { 571 compatible = "fsl,imx6q-flexcan"; 572 reg = <0x02094000 0x4000>; 573 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 575 <&clks IMX6QDL_CLK_CAN2_SERIAL>; 576 clock-names = "ipg", "per"; 577 fsl,stop-mode = <&gpr 0x34 29 0x10 18>; 578 status = "disabled"; 579 }; 580 581 gpt: timer@2098000 { 582 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 583 reg = <0x02098000 0x4000>; 584 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 586 <&clks IMX6QDL_CLK_GPT_IPG_PER>, 587 <&clks IMX6QDL_CLK_GPT_3M>; 588 clock-names = "ipg", "per", "osc_per"; 589 }; 590 591 gpio1: gpio@209c000 { 592 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 593 reg = <0x0209c000 0x4000>; 594 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 595 <0 67 IRQ_TYPE_LEVEL_HIGH>; 596 gpio-controller; 597 #gpio-cells = <2>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 602 gpio2: gpio@20a0000 { 603 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 604 reg = <0x020a0000 0x4000>; 605 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 606 <0 69 IRQ_TYPE_LEVEL_HIGH>; 607 gpio-controller; 608 #gpio-cells = <2>; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 613 gpio3: gpio@20a4000 { 614 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 615 reg = <0x020a4000 0x4000>; 616 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 617 <0 71 IRQ_TYPE_LEVEL_HIGH>; 618 gpio-controller; 619 #gpio-cells = <2>; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 624 gpio4: gpio@20a8000 { 625 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 626 reg = <0x020a8000 0x4000>; 627 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 628 <0 73 IRQ_TYPE_LEVEL_HIGH>; 629 gpio-controller; 630 #gpio-cells = <2>; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 635 gpio5: gpio@20ac000 { 636 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 637 reg = <0x020ac000 0x4000>; 638 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 639 <0 75 IRQ_TYPE_LEVEL_HIGH>; 640 gpio-controller; 641 #gpio-cells = <2>; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 646 gpio6: gpio@20b0000 { 647 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 648 reg = <0x020b0000 0x4000>; 649 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 650 <0 77 IRQ_TYPE_LEVEL_HIGH>; 651 gpio-controller; 652 #gpio-cells = <2>; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 }; 656 657 gpio7: gpio@20b4000 { 658 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 659 reg = <0x020b4000 0x4000>; 660 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 661 <0 79 IRQ_TYPE_LEVEL_HIGH>; 662 gpio-controller; 663 #gpio-cells = <2>; 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 }; 667 668 kpp: kpp@20b8000 { 669 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 670 reg = <0x020b8000 0x4000>; 671 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clks IMX6QDL_CLK_IPG>; 673 status = "disabled"; 674 }; 675 676 wdog1: wdog@20bc000 { 677 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 678 reg = <0x020bc000 0x4000>; 679 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&clks IMX6QDL_CLK_IPG>; 681 }; 682 683 wdog2: wdog@20c0000 { 684 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 685 reg = <0x020c0000 0x4000>; 686 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clks IMX6QDL_CLK_IPG>; 688 status = "disabled"; 689 }; 690 691 clks: ccm@20c4000 { 692 compatible = "fsl,imx6q-ccm"; 693 reg = <0x020c4000 0x4000>; 694 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 695 <0 88 IRQ_TYPE_LEVEL_HIGH>; 696 #clock-cells = <1>; 697 }; 698 699 anatop: anatop@20c8000 { 700 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; 701 reg = <0x020c8000 0x1000>; 702 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 703 <0 54 IRQ_TYPE_LEVEL_HIGH>, 704 <0 127 IRQ_TYPE_LEVEL_HIGH>; 705 706 reg_vdd1p1: regulator-1p1 { 707 compatible = "fsl,anatop-regulator"; 708 regulator-name = "vdd1p1"; 709 regulator-min-microvolt = <1000000>; 710 regulator-max-microvolt = <1200000>; 711 regulator-always-on; 712 anatop-reg-offset = <0x110>; 713 anatop-vol-bit-shift = <8>; 714 anatop-vol-bit-width = <5>; 715 anatop-min-bit-val = <4>; 716 anatop-min-voltage = <800000>; 717 anatop-max-voltage = <1375000>; 718 anatop-enable-bit = <0>; 719 }; 720 721 reg_vdd3p0: regulator-3p0 { 722 compatible = "fsl,anatop-regulator"; 723 regulator-name = "vdd3p0"; 724 regulator-min-microvolt = <2800000>; 725 regulator-max-microvolt = <3150000>; 726 regulator-always-on; 727 anatop-reg-offset = <0x120>; 728 anatop-vol-bit-shift = <8>; 729 anatop-vol-bit-width = <5>; 730 anatop-min-bit-val = <0>; 731 anatop-min-voltage = <2625000>; 732 anatop-max-voltage = <3400000>; 733 anatop-enable-bit = <0>; 734 }; 735 736 reg_vdd2p5: regulator-2p5 { 737 compatible = "fsl,anatop-regulator"; 738 regulator-name = "vdd2p5"; 739 regulator-min-microvolt = <2250000>; 740 regulator-max-microvolt = <2750000>; 741 regulator-always-on; 742 anatop-reg-offset = <0x130>; 743 anatop-vol-bit-shift = <8>; 744 anatop-vol-bit-width = <5>; 745 anatop-min-bit-val = <0>; 746 anatop-min-voltage = <2100000>; 747 anatop-max-voltage = <2875000>; 748 anatop-enable-bit = <0>; 749 }; 750 751 reg_arm: regulator-vddcore { 752 compatible = "fsl,anatop-regulator"; 753 regulator-name = "vddarm"; 754 regulator-min-microvolt = <725000>; 755 regulator-max-microvolt = <1450000>; 756 regulator-always-on; 757 anatop-reg-offset = <0x140>; 758 anatop-vol-bit-shift = <0>; 759 anatop-vol-bit-width = <5>; 760 anatop-delay-reg-offset = <0x170>; 761 anatop-delay-bit-shift = <24>; 762 anatop-delay-bit-width = <2>; 763 anatop-min-bit-val = <1>; 764 anatop-min-voltage = <725000>; 765 anatop-max-voltage = <1450000>; 766 }; 767 768 reg_pu: regulator-vddpu { 769 compatible = "fsl,anatop-regulator"; 770 regulator-name = "vddpu"; 771 regulator-min-microvolt = <725000>; 772 regulator-max-microvolt = <1450000>; 773 regulator-enable-ramp-delay = <380>; 774 anatop-reg-offset = <0x140>; 775 anatop-vol-bit-shift = <9>; 776 anatop-vol-bit-width = <5>; 777 anatop-delay-reg-offset = <0x170>; 778 anatop-delay-bit-shift = <26>; 779 anatop-delay-bit-width = <2>; 780 anatop-min-bit-val = <1>; 781 anatop-min-voltage = <725000>; 782 anatop-max-voltage = <1450000>; 783 }; 784 785 reg_soc: regulator-vddsoc { 786 compatible = "fsl,anatop-regulator"; 787 regulator-name = "vddsoc"; 788 regulator-min-microvolt = <725000>; 789 regulator-max-microvolt = <1450000>; 790 regulator-always-on; 791 anatop-reg-offset = <0x140>; 792 anatop-vol-bit-shift = <18>; 793 anatop-vol-bit-width = <5>; 794 anatop-delay-reg-offset = <0x170>; 795 anatop-delay-bit-shift = <28>; 796 anatop-delay-bit-width = <2>; 797 anatop-min-bit-val = <1>; 798 anatop-min-voltage = <725000>; 799 anatop-max-voltage = <1450000>; 800 }; 801 }; 802 803 usbphy1: usbphy@20c9000 { 804 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 805 reg = <0x020c9000 0x1000>; 806 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&clks IMX6QDL_CLK_USBPHY1>; 808 fsl,anatop = <&anatop>; 809 }; 810 811 usbphy2: usbphy@20ca000 { 812 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 813 reg = <0x020ca000 0x1000>; 814 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&clks IMX6QDL_CLK_USBPHY2>; 816 fsl,anatop = <&anatop>; 817 }; 818 819 snvs: snvs@20cc000 { 820 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 821 reg = <0x020cc000 0x4000>; 822 823 snvs_rtc: snvs-rtc-lp { 824 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 825 regmap = <&snvs>; 826 offset = <0x34>; 827 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 828 <0 20 IRQ_TYPE_LEVEL_HIGH>; 829 }; 830 831 snvs_poweroff: snvs-poweroff { 832 compatible = "syscon-poweroff"; 833 regmap = <&snvs>; 834 offset = <0x38>; 835 value = <0x60>; 836 mask = <0x60>; 837 status = "disabled"; 838 }; 839 840 snvs_pwrkey: snvs-powerkey { 841 compatible = "fsl,sec-v4.0-pwrkey"; 842 regmap = <&snvs>; 843 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 844 linux,keycode = <KEY_POWER>; 845 wakeup-source; 846 status = "disabled"; 847 }; 848 849 snvs_lpgpr: snvs-lpgpr { 850 compatible = "fsl,imx6q-snvs-lpgpr"; 851 }; 852 }; 853 854 epit1: epit@20d0000 { /* EPIT1 */ 855 reg = <0x020d0000 0x4000>; 856 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 857 }; 858 859 epit2: epit@20d4000 { /* EPIT2 */ 860 reg = <0x020d4000 0x4000>; 861 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 862 }; 863 864 src: src@20d8000 { 865 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 866 reg = <0x020d8000 0x4000>; 867 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 868 <0 96 IRQ_TYPE_LEVEL_HIGH>; 869 #reset-cells = <1>; 870 }; 871 872 gpc: gpc@20dc000 { 873 compatible = "fsl,imx6q-gpc"; 874 reg = <0x020dc000 0x4000>; 875 interrupt-controller; 876 #interrupt-cells = <3>; 877 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 878 <0 90 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-parent = <&intc>; 880 clocks = <&clks IMX6QDL_CLK_IPG>; 881 clock-names = "ipg"; 882 883 pgc { 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 power-domain@0 { 888 reg = <0>; 889 #power-domain-cells = <0>; 890 }; 891 pd_pu: power-domain@1 { 892 reg = <1>; 893 #power-domain-cells = <0>; 894 power-supply = <®_pu>; 895 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 896 <&clks IMX6QDL_CLK_GPU3D_SHADER>, 897 <&clks IMX6QDL_CLK_GPU2D_CORE>, 898 <&clks IMX6QDL_CLK_GPU2D_AXI>, 899 <&clks IMX6QDL_CLK_OPENVG_AXI>, 900 <&clks IMX6QDL_CLK_VPU_AXI>; 901 }; 902 }; 903 }; 904 905 gpr: iomuxc-gpr@20e0000 { 906 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 907 reg = <0x20e0000 0x38>; 908 909 mux: mux-controller { 910 compatible = "mmio-mux"; 911 #mux-control-cells = <1>; 912 }; 913 }; 914 915 iomuxc: iomuxc@20e0000 { 916 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 917 reg = <0x20e0000 0x4000>; 918 }; 919 920 dcic1: dcic@20e4000 { 921 reg = <0x020e4000 0x4000>; 922 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 923 }; 924 925 dcic2: dcic@20e8000 { 926 reg = <0x020e8000 0x4000>; 927 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 928 }; 929 930 sdma: sdma@20ec000 { 931 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 932 reg = <0x020ec000 0x4000>; 933 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&clks IMX6QDL_CLK_IPG>, 935 <&clks IMX6QDL_CLK_SDMA>; 936 clock-names = "ipg", "ahb"; 937 #dma-cells = <3>; 938 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 939 }; 940 }; 941 942 aips-bus@2100000 { /* AIPS2 */ 943 compatible = "fsl,aips-bus", "simple-bus"; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 reg = <0x02100000 0x100000>; 947 ranges; 948 949 crypto: caam@2100000 { 950 compatible = "fsl,sec-v4.0"; 951 #address-cells = <1>; 952 #size-cells = <1>; 953 reg = <0x2100000 0x10000>; 954 ranges = <0 0x2100000 0x10000>; 955 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 956 <&clks IMX6QDL_CLK_CAAM_ACLK>, 957 <&clks IMX6QDL_CLK_CAAM_IPG>, 958 <&clks IMX6QDL_CLK_EIM_SLOW>; 959 clock-names = "mem", "aclk", "ipg", "emi_slow"; 960 961 sec_jr0: jr0@1000 { 962 compatible = "fsl,sec-v4.0-job-ring"; 963 reg = <0x1000 0x1000>; 964 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 965 }; 966 967 sec_jr1: jr1@2000 { 968 compatible = "fsl,sec-v4.0-job-ring"; 969 reg = <0x2000 0x1000>; 970 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 971 }; 972 }; 973 974 aipstz@217c000 { /* AIPSTZ2 */ 975 reg = <0x0217c000 0x4000>; 976 }; 977 978 usbotg: usb@2184000 { 979 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 980 reg = <0x02184000 0x200>; 981 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clks IMX6QDL_CLK_USBOH3>; 983 fsl,usbphy = <&usbphy1>; 984 fsl,usbmisc = <&usbmisc 0>; 985 ahb-burst-config = <0x0>; 986 tx-burst-size-dword = <0x10>; 987 rx-burst-size-dword = <0x10>; 988 status = "disabled"; 989 }; 990 991 usbh1: usb@2184200 { 992 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 993 reg = <0x02184200 0x200>; 994 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&clks IMX6QDL_CLK_USBOH3>; 996 fsl,usbphy = <&usbphy2>; 997 fsl,usbmisc = <&usbmisc 1>; 998 dr_mode = "host"; 999 ahb-burst-config = <0x0>; 1000 tx-burst-size-dword = <0x10>; 1001 rx-burst-size-dword = <0x10>; 1002 status = "disabled"; 1003 }; 1004 1005 usbh2: usb@2184400 { 1006 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1007 reg = <0x02184400 0x200>; 1008 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1010 fsl,usbphy = <&usbphynop1>; 1011 phy_type = "hsic"; 1012 fsl,usbmisc = <&usbmisc 2>; 1013 dr_mode = "host"; 1014 ahb-burst-config = <0x0>; 1015 tx-burst-size-dword = <0x10>; 1016 rx-burst-size-dword = <0x10>; 1017 status = "disabled"; 1018 }; 1019 1020 usbh3: usb@2184600 { 1021 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1022 reg = <0x02184600 0x200>; 1023 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1025 fsl,usbphy = <&usbphynop2>; 1026 phy_type = "hsic"; 1027 fsl,usbmisc = <&usbmisc 3>; 1028 dr_mode = "host"; 1029 ahb-burst-config = <0x0>; 1030 tx-burst-size-dword = <0x10>; 1031 rx-burst-size-dword = <0x10>; 1032 status = "disabled"; 1033 }; 1034 1035 usbmisc: usbmisc@2184800 { 1036 #index-cells = <1>; 1037 compatible = "fsl,imx6q-usbmisc"; 1038 reg = <0x02184800 0x200>; 1039 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1040 }; 1041 1042 fec: ethernet@2188000 { 1043 compatible = "fsl,imx6q-fec"; 1044 reg = <0x02188000 0x4000>; 1045 interrupt-names = "int0", "pps"; 1046 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, 1047 <0 119 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clks IMX6QDL_CLK_ENET>, 1049 <&clks IMX6QDL_CLK_ENET>, 1050 <&clks IMX6QDL_CLK_ENET_REF>; 1051 clock-names = "ipg", "ahb", "ptp"; 1052 status = "disabled"; 1053 }; 1054 1055 mlb@218c000 { 1056 reg = <0x0218c000 0x4000>; 1057 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 1058 <0 117 IRQ_TYPE_LEVEL_HIGH>, 1059 <0 126 IRQ_TYPE_LEVEL_HIGH>; 1060 }; 1061 1062 usdhc1: usdhc@2190000 { 1063 compatible = "fsl,imx6q-usdhc"; 1064 reg = <0x02190000 0x4000>; 1065 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&clks IMX6QDL_CLK_USDHC1>, 1067 <&clks IMX6QDL_CLK_USDHC1>, 1068 <&clks IMX6QDL_CLK_USDHC1>; 1069 clock-names = "ipg", "ahb", "per"; 1070 bus-width = <4>; 1071 status = "disabled"; 1072 }; 1073 1074 usdhc2: usdhc@2194000 { 1075 compatible = "fsl,imx6q-usdhc"; 1076 reg = <0x02194000 0x4000>; 1077 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&clks IMX6QDL_CLK_USDHC2>, 1079 <&clks IMX6QDL_CLK_USDHC2>, 1080 <&clks IMX6QDL_CLK_USDHC2>; 1081 clock-names = "ipg", "ahb", "per"; 1082 bus-width = <4>; 1083 status = "disabled"; 1084 }; 1085 1086 usdhc3: usdhc@2198000 { 1087 compatible = "fsl,imx6q-usdhc"; 1088 reg = <0x02198000 0x4000>; 1089 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&clks IMX6QDL_CLK_USDHC3>, 1091 <&clks IMX6QDL_CLK_USDHC3>, 1092 <&clks IMX6QDL_CLK_USDHC3>; 1093 clock-names = "ipg", "ahb", "per"; 1094 bus-width = <4>; 1095 status = "disabled"; 1096 }; 1097 1098 usdhc4: usdhc@219c000 { 1099 compatible = "fsl,imx6q-usdhc"; 1100 reg = <0x0219c000 0x4000>; 1101 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&clks IMX6QDL_CLK_USDHC4>, 1103 <&clks IMX6QDL_CLK_USDHC4>, 1104 <&clks IMX6QDL_CLK_USDHC4>; 1105 clock-names = "ipg", "ahb", "per"; 1106 bus-width = <4>; 1107 status = "disabled"; 1108 }; 1109 1110 i2c1: i2c@21a0000 { 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1114 reg = <0x021a0000 0x4000>; 1115 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&clks IMX6QDL_CLK_I2C1>; 1117 status = "disabled"; 1118 }; 1119 1120 i2c2: i2c@21a4000 { 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1124 reg = <0x021a4000 0x4000>; 1125 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&clks IMX6QDL_CLK_I2C2>; 1127 status = "disabled"; 1128 }; 1129 1130 i2c3: i2c@21a8000 { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1134 reg = <0x021a8000 0x4000>; 1135 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&clks IMX6QDL_CLK_I2C3>; 1137 status = "disabled"; 1138 }; 1139 1140 romcp@21ac000 { 1141 reg = <0x021ac000 0x4000>; 1142 }; 1143 1144 mmdc0: memory-controller@21b0000 { /* MMDC0 */ 1145 compatible = "fsl,imx6q-mmdc"; 1146 reg = <0x021b0000 0x4000>; 1147 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 1148 }; 1149 1150 mmdc1: memory-controller@21b4000 { /* MMDC1 */ 1151 compatible = "fsl,imx6q-mmdc"; 1152 reg = <0x021b4000 0x4000>; 1153 status = "disabled"; 1154 }; 1155 1156 weim: weim@21b8000 { 1157 #address-cells = <2>; 1158 #size-cells = <1>; 1159 compatible = "fsl,imx6q-weim"; 1160 reg = <0x021b8000 0x4000>; 1161 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 1163 fsl,weim-cs-gpr = <&gpr>; 1164 status = "disabled"; 1165 }; 1166 1167 ocotp: ocotp@21bc000 { 1168 compatible = "fsl,imx6q-ocotp", "syscon"; 1169 reg = <0x021bc000 0x4000>; 1170 clocks = <&clks IMX6QDL_CLK_IIM>; 1171 }; 1172 1173 tzasc@21d0000 { /* TZASC1 */ 1174 reg = <0x021d0000 0x4000>; 1175 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1176 }; 1177 1178 tzasc@21d4000 { /* TZASC2 */ 1179 reg = <0x021d4000 0x4000>; 1180 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 1181 }; 1182 1183 audmux: audmux@21d8000 { 1184 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 1185 reg = <0x021d8000 0x4000>; 1186 status = "disabled"; 1187 }; 1188 1189 mipi_csi: mipi@21dc000 { 1190 compatible = "fsl,imx6-mipi-csi2"; 1191 reg = <0x021dc000 0x4000>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 interrupts = <0 100 0x04>, <0 101 0x04>; 1195 clocks = <&clks IMX6QDL_CLK_HSI_TX>, 1196 <&clks IMX6QDL_CLK_VIDEO_27M>, 1197 <&clks IMX6QDL_CLK_EIM_PODF>; 1198 clock-names = "dphy", "ref", "pix"; 1199 status = "disabled"; 1200 }; 1201 1202 mipi_dsi: mipi@21e0000 { 1203 reg = <0x021e0000 0x4000>; 1204 status = "disabled"; 1205 1206 ports { 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 1210 port@0 { 1211 reg = <0>; 1212 1213 mipi_mux_0: endpoint { 1214 remote-endpoint = <&ipu1_di0_mipi>; 1215 }; 1216 }; 1217 1218 port@1 { 1219 reg = <1>; 1220 1221 mipi_mux_1: endpoint { 1222 remote-endpoint = <&ipu1_di1_mipi>; 1223 }; 1224 }; 1225 }; 1226 }; 1227 1228 vdoa@21e4000 { 1229 compatible = "fsl,imx6q-vdoa"; 1230 reg = <0x021e4000 0x4000>; 1231 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&clks IMX6QDL_CLK_VDOA>; 1233 }; 1234 1235 uart2: serial@21e8000 { 1236 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1237 reg = <0x021e8000 0x4000>; 1238 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1240 <&clks IMX6QDL_CLK_UART_SERIAL>; 1241 clock-names = "ipg", "per"; 1242 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1243 dma-names = "rx", "tx"; 1244 status = "disabled"; 1245 }; 1246 1247 uart3: serial@21ec000 { 1248 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1249 reg = <0x021ec000 0x4000>; 1250 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1252 <&clks IMX6QDL_CLK_UART_SERIAL>; 1253 clock-names = "ipg", "per"; 1254 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1255 dma-names = "rx", "tx"; 1256 status = "disabled"; 1257 }; 1258 1259 uart4: serial@21f0000 { 1260 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1261 reg = <0x021f0000 0x4000>; 1262 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1264 <&clks IMX6QDL_CLK_UART_SERIAL>; 1265 clock-names = "ipg", "per"; 1266 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1267 dma-names = "rx", "tx"; 1268 status = "disabled"; 1269 }; 1270 1271 uart5: serial@21f4000 { 1272 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1273 reg = <0x021f4000 0x4000>; 1274 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1276 <&clks IMX6QDL_CLK_UART_SERIAL>; 1277 clock-names = "ipg", "per"; 1278 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1279 dma-names = "rx", "tx"; 1280 status = "disabled"; 1281 }; 1282 }; 1283 1284 ipu1: ipu@2400000 { 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 compatible = "fsl,imx6q-ipu"; 1288 reg = <0x02400000 0x400000>; 1289 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1290 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&clks IMX6QDL_CLK_IPU1>, 1292 <&clks IMX6QDL_CLK_IPU1_DI0>, 1293 <&clks IMX6QDL_CLK_IPU1_DI1>; 1294 clock-names = "bus", "di0", "di1"; 1295 resets = <&src 2>; 1296 1297 ipu1_csi0: port@0 { 1298 reg = <0>; 1299 1300 ipu1_csi0_from_ipu1_csi0_mux: endpoint { 1301 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; 1302 }; 1303 }; 1304 1305 ipu1_csi1: port@1 { 1306 reg = <1>; 1307 }; 1308 1309 ipu1_di0: port@2 { 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 reg = <2>; 1313 1314 ipu1_di0_disp0: endpoint@0 { 1315 reg = <0>; 1316 }; 1317 1318 ipu1_di0_hdmi: endpoint@1 { 1319 reg = <1>; 1320 remote-endpoint = <&hdmi_mux_0>; 1321 }; 1322 1323 ipu1_di0_mipi: endpoint@2 { 1324 reg = <2>; 1325 remote-endpoint = <&mipi_mux_0>; 1326 }; 1327 1328 ipu1_di0_lvds0: endpoint@3 { 1329 reg = <3>; 1330 remote-endpoint = <&lvds0_mux_0>; 1331 }; 1332 1333 ipu1_di0_lvds1: endpoint@4 { 1334 reg = <4>; 1335 remote-endpoint = <&lvds1_mux_0>; 1336 }; 1337 }; 1338 1339 ipu1_di1: port@3 { 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 reg = <3>; 1343 1344 ipu1_di1_disp1: endpoint@0 { 1345 reg = <0>; 1346 }; 1347 1348 ipu1_di1_hdmi: endpoint@1 { 1349 reg = <1>; 1350 remote-endpoint = <&hdmi_mux_1>; 1351 }; 1352 1353 ipu1_di1_mipi: endpoint@2 { 1354 reg = <2>; 1355 remote-endpoint = <&mipi_mux_1>; 1356 }; 1357 1358 ipu1_di1_lvds0: endpoint@3 { 1359 reg = <3>; 1360 remote-endpoint = <&lvds0_mux_1>; 1361 }; 1362 1363 ipu1_di1_lvds1: endpoint@4 { 1364 reg = <4>; 1365 remote-endpoint = <&lvds1_mux_1>; 1366 }; 1367 }; 1368 }; 1369 }; 1370}; 1371