1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP. 5 * 6 */ 7 8#include <dt-bindings/clock/imx6sll-clock.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include "imx6sll-pinfunc.h" 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 aliases { 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 gpio3 = &gpio4; 22 gpio4 = &gpio5; 23 gpio5 = &gpio6; 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 mmc0 = &usdhc1; 28 mmc1 = &usdhc2; 29 mmc2 = &usdhc3; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 spi0 = &ecspi1; 36 spi1 = &ecspi2; 37 spi3 = &ecspi3; 38 spi4 = &ecspi4; 39 usb0 = &usbotg1; 40 usb1 = &usbotg2; 41 usbphy0 = &usbphy1; 42 usbphy1 = &usbphy2; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a9"; 51 device_type = "cpu"; 52 reg = <0>; 53 next-level-cache = <&L2>; 54 operating-points = 55 /* kHz uV */ 56 <996000 1275000>, 57 <792000 1175000>, 58 <396000 1075000>, 59 <198000 975000>; 60 fsl,soc-operating-points = 61 /* ARM kHz SOC-PU uV */ 62 <996000 1175000>, 63 <792000 1175000>, 64 <396000 1175000>, 65 <198000 1175000>; 66 clock-latency = <61036>; /* two CLK32 periods */ 67 #cooling-cells = <2>; 68 clocks = <&clks IMX6SLL_CLK_ARM>, 69 <&clks IMX6SLL_CLK_PLL2_PFD2>, 70 <&clks IMX6SLL_CLK_STEP>, 71 <&clks IMX6SLL_CLK_PLL1_SW>, 72 <&clks IMX6SLL_CLK_PLL1_SYS>; 73 clock-names = "arm", "pll2_pfd2_396m", "step", 74 "pll1_sw", "pll1_sys"; 75 }; 76 }; 77 78 ckil: clock-ckil { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <32768>; 82 clock-output-names = "ckil"; 83 }; 84 85 osc: clock-osc-24m { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <24000000>; 89 clock-output-names = "osc"; 90 }; 91 92 ipp_di0: clock-ipp-di0 { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <0>; 96 clock-output-names = "ipp_di0"; 97 }; 98 99 ipp_di1: clock-ipp-di1 { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <0>; 103 clock-output-names = "ipp_di1"; 104 }; 105 106 tempmon: temperature-sensor { 107 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; 108 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-parent = <&gpc>; 110 fsl,tempmon = <&anatop>; 111 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 112 nvmem-cell-names = "calib", "temp_grade"; 113 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; 114 }; 115 116 soc { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 compatible = "simple-bus"; 120 interrupt-parent = <&gpc>; 121 ranges; 122 123 ocram: sram@900000 { 124 compatible = "mmio-sram"; 125 reg = <0x00900000 0x20000>; 126 ranges = <0 0x00900000 0x20000>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 }; 130 131 intc: interrupt-controller@a01000 { 132 compatible = "arm,cortex-a9-gic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x00a01000 0x1000>, 136 <0x00a00100 0x100>; 137 interrupt-parent = <&intc>; 138 }; 139 140 L2: cache-controller@a02000 { 141 compatible = "arm,pl310-cache"; 142 reg = <0x00a02000 0x1000>; 143 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 144 cache-unified; 145 cache-level = <2>; 146 arm,tag-latency = <4 2 3>; 147 arm,data-latency = <4 2 3>; 148 }; 149 150 aips1: aips-bus@2000000 { 151 compatible = "fsl,aips-bus", "simple-bus"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 reg = <0x02000000 0x100000>; 155 ranges; 156 157 spba: spba-bus@2000000 { 158 compatible = "fsl,spba-bus", "simple-bus"; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 reg = <0x02000000 0x40000>; 162 ranges; 163 164 spdif: spdif@2004000 { 165 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; 166 reg = <0x02004000 0x4000>; 167 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 168 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; 169 dma-names = "rx", "tx"; 170 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, 171 <&clks IMX6SLL_CLK_OSC>, 172 <&clks IMX6SLL_CLK_SPDIF>, 173 <&clks IMX6SLL_CLK_DUMMY>, 174 <&clks IMX6SLL_CLK_DUMMY>, 175 <&clks IMX6SLL_CLK_DUMMY>, 176 <&clks IMX6SLL_CLK_IPG>, 177 <&clks IMX6SLL_CLK_DUMMY>, 178 <&clks IMX6SLL_CLK_DUMMY>, 179 <&clks IMX6SLL_CLK_SPBA>; 180 clock-names = "core", "rxtx0", 181 "rxtx1", "rxtx2", 182 "rxtx3", "rxtx4", 183 "rxtx5", "rxtx6", 184 "rxtx7", "dma"; 185 status = "disabled"; 186 }; 187 188 ecspi1: spi@2008000 { 189 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 190 reg = <0x02008000 0x4000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 193 dma-names = "rx", "tx"; 194 clocks = <&clks IMX6SLL_CLK_ECSPI1>, 195 <&clks IMX6SLL_CLK_ECSPI1>; 196 clock-names = "ipg", "per"; 197 status = "disabled"; 198 }; 199 200 ecspi2: spi@200c000 { 201 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 202 reg = <0x0200c000 0x4000>; 203 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 204 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 205 dma-names = "rx", "tx"; 206 clocks = <&clks IMX6SLL_CLK_ECSPI2>, 207 <&clks IMX6SLL_CLK_ECSPI2>; 208 clock-names = "ipg", "per"; 209 status = "disabled"; 210 }; 211 212 ecspi3: spi@2010000 { 213 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 214 reg = <0x02010000 0x4000>; 215 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 216 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 217 dma-names = "rx", "tx"; 218 clocks = <&clks IMX6SLL_CLK_ECSPI3>, 219 <&clks IMX6SLL_CLK_ECSPI3>; 220 clock-names = "ipg", "per"; 221 status = "disabled"; 222 }; 223 224 ecspi4: spi@2014000 { 225 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 226 reg = <0x02014000 0x4000>; 227 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 228 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 229 dma-names = "rx", "tx"; 230 clocks = <&clks IMX6SLL_CLK_ECSPI4>, 231 <&clks IMX6SLL_CLK_ECSPI4>; 232 clock-names = "ipg", "per"; 233 status = "disabled"; 234 }; 235 236 uart4: serial@2018000 { 237 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 238 "fsl,imx21-uart"; 239 reg = <0x02018000 0x4000>; 240 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 241 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 242 dma-names = "rx", "tx"; 243 clocks = <&clks IMX6SLL_CLK_UART4_IPG>, 244 <&clks IMX6SLL_CLK_UART4_SERIAL>; 245 clock-names = "ipg", "per"; 246 status = "disabled"; 247 }; 248 249 uart1: serial@2020000 { 250 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 251 "fsl,imx21-uart"; 252 reg = <0x02020000 0x4000>; 253 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 254 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 255 dma-names = "rx", "tx"; 256 clocks = <&clks IMX6SLL_CLK_UART1_IPG>, 257 <&clks IMX6SLL_CLK_UART1_SERIAL>; 258 clock-names = "ipg", "per"; 259 status = "disabled"; 260 }; 261 262 uart2: serial@2024000 { 263 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 264 "fsl,imx21-uart"; 265 reg = <0x02024000 0x4000>; 266 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 267 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 268 dma-names = "rx", "tx"; 269 clocks = <&clks IMX6SLL_CLK_UART2_IPG>, 270 <&clks IMX6SLL_CLK_UART2_SERIAL>; 271 clock-names = "ipg", "per"; 272 status = "disabled"; 273 }; 274 275 ssi1: ssi@2028000 { 276 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 277 reg = <0x02028000 0x4000>; 278 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 279 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; 280 dma-names = "rx", "tx"; 281 fsl,fifo-depth = <15>; 282 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, 283 <&clks IMX6SLL_CLK_SSI1>; 284 clock-names = "ipg", "baud"; 285 status = "disabled"; 286 }; 287 288 ssi2: ssi@202c000 { 289 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 290 reg = <0x0202c000 0x4000>; 291 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 292 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; 293 dma-names = "rx", "tx"; 294 fsl,fifo-depth = <15>; 295 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, 296 <&clks IMX6SLL_CLK_SSI2>; 297 clock-names = "ipg", "baud"; 298 status = "disabled"; 299 }; 300 301 ssi3: ssi@2030000 { 302 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 303 reg = <0x02030000 0x4000>; 304 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 305 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; 306 dma-names = "rx", "tx"; 307 fsl,fifo-depth = <15>; 308 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, 309 <&clks IMX6SLL_CLK_SSI3>; 310 clock-names = "ipg", "baud"; 311 status = "disabled"; 312 }; 313 314 uart3: serial@2034000 { 315 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 316 "fsl,imx21-uart"; 317 reg = <0x02034000 0x4000>; 318 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 319 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 320 dma-name = "rx", "tx"; 321 clocks = <&clks IMX6SLL_CLK_UART3_IPG>, 322 <&clks IMX6SLL_CLK_UART3_SERIAL>; 323 clock-names = "ipg", "per"; 324 status = "disabled"; 325 }; 326 }; 327 328 pwm1: pwm@2080000 { 329 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 330 reg = <0x02080000 0x4000>; 331 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clks IMX6SLL_CLK_PWM1>, 333 <&clks IMX6SLL_CLK_PWM1>; 334 clock-names = "ipg", "per"; 335 #pwm-cells = <2>; 336 }; 337 338 pwm2: pwm@2084000 { 339 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 340 reg = <0x02084000 0x4000>; 341 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&clks IMX6SLL_CLK_PWM2>, 343 <&clks IMX6SLL_CLK_PWM2>; 344 clock-names = "ipg", "per"; 345 #pwm-cells = <2>; 346 }; 347 348 pwm3: pwm@2088000 { 349 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 350 reg = <0x02088000 0x4000>; 351 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&clks IMX6SLL_CLK_PWM3>, 353 <&clks IMX6SLL_CLK_PWM3>; 354 clock-names = "ipg", "per"; 355 #pwm-cells = <2>; 356 }; 357 358 pwm4: pwm@208c000 { 359 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 360 reg = <0x0208c000 0x4000>; 361 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clks IMX6SLL_CLK_PWM4>, 363 <&clks IMX6SLL_CLK_PWM4>; 364 clock-names = "ipg", "per"; 365 #pwm-cells = <2>; 366 }; 367 368 gpt1: timer@2098000 { 369 compatible = "fsl,imx6sl-gpt"; 370 reg = <0x02098000 0x4000>; 371 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clks IMX6SLL_CLK_GPT_BUS>, 373 <&clks IMX6SLL_CLK_GPT_SERIAL>; 374 clock-names = "ipg", "per"; 375 }; 376 377 gpio1: gpio@209c000 { 378 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 379 reg = <0x0209c000 0x4000>; 380 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clks IMX6SLL_CLK_GPIO1>; 383 gpio-controller; 384 #gpio-cells = <2>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>; 388 }; 389 390 gpio2: gpio@20a0000 { 391 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 392 reg = <0x020a0000 0x4000>; 393 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&clks IMX6SLL_CLK_GPIO2>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 gpio-ranges = <&iomuxc 0 50 32>; 401 }; 402 403 gpio3: gpio@20a4000 { 404 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 405 reg = <0x020a4000 0x4000>; 406 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clks IMX6SLL_CLK_GPIO3>; 409 gpio-controller; 410 #gpio-cells = <2>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>, 414 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>, 415 <&iomuxc 21 6 11>; 416 }; 417 418 gpio4: gpio@20a8000 { 419 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 420 reg = <0x020a8000 0x4000>; 421 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&clks IMX6SLL_CLK_GPIO4>; 424 gpio-controller; 425 #gpio-cells = <2>; 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>, 429 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>, 430 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>, 431 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>, 432 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>, 433 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>, 434 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>, 435 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>, 436 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>; 437 }; 438 439 gpio5: gpio@20ac000 { 440 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 441 reg = <0x020ac000 0x4000>; 442 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&clks IMX6SLL_CLK_GPIO5>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 interrupt-controller; 448 #interrupt-cells = <2>; 449 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>, 450 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>, 451 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>, 452 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>, 453 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>, 454 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>, 455 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>, 456 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>, 457 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>, 458 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>, 459 <&iomuxc 21 137 1>; 460 }; 461 462 gpio6: gpio@20b0000 { 463 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 464 reg = <0x020b0000 0x4000>; 465 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&clks IMX6SLL_CLK_GPIO6>; 468 gpio-controller; 469 #gpio-cells = <2>; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 }; 473 474 kpp: keypad@20b8000 { 475 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; 476 reg = <0x020b8000 0x4000>; 477 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clks IMX6SLL_CLK_KPP>; 479 status = "disabled"; 480 }; 481 482 wdog1: watchdog@20bc000 { 483 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; 484 reg = <0x020bc000 0x4000>; 485 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clks IMX6SLL_CLK_WDOG1>; 487 }; 488 489 wdog2: watchdog@20c0000 { 490 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; 491 reg = <0x020c0000 0x4000>; 492 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clks IMX6SLL_CLK_WDOG2>; 494 status = "disabled"; 495 }; 496 497 clks: clock-controller@20c4000 { 498 compatible = "fsl,imx6sll-ccm"; 499 reg = <0x020c4000 0x4000>; 500 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 502 #clock-cells = <1>; 503 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 504 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 505 506 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; 507 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; 508 }; 509 510 anatop: anatop@20c8000 { 511 compatible = "fsl,imx6sll-anatop", 512 "fsl,imx6q-anatop", 513 "syscon", "simple-bus"; 514 reg = <0x020c8000 0x4000>; 515 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 521 reg_3p0: regulator-3p0@20c8120 { 522 compatible = "fsl,anatop-regulator"; 523 reg = <0x20c8120>; 524 regulator-name = "vdd3p0"; 525 regulator-min-microvolt = <2625000>; 526 regulator-max-microvolt = <3400000>; 527 anatop-reg-offset = <0x120>; 528 anatop-vol-bit-shift = <8>; 529 anatop-vol-bit-width = <5>; 530 anatop-min-bit-val = <0>; 531 anatop-min-voltage = <2625000>; 532 anatop-max-voltage = <3400000>; 533 anatop-enable-bit = <0>; 534 }; 535 }; 536 537 usbphy1: usb-phy@20c9000 { 538 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", 539 "fsl,imx23-usbphy"; 540 reg = <0x020c9000 0x1000>; 541 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clks IMX6SLL_CLK_USBPHY1>; 543 phy-3p0-supply = <®_3p0>; 544 fsl,anatop = <&anatop>; 545 }; 546 547 usbphy2: usb-phy@20ca000 { 548 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", 549 "fsl,imx23-usbphy"; 550 reg = <0x020ca000 0x1000>; 551 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clks IMX6SLL_CLK_USBPHY2>; 553 phy-3p0-supply = <®_3p0>; 554 fsl,anatop = <&anatop>; 555 }; 556 557 snvs: snvs@20cc000 { 558 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 559 reg = <0x020cc000 0x4000>; 560 561 snvs_rtc: snvs-rtc-lp { 562 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 563 regmap = <&snvs>; 564 offset = <0x34>; 565 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 567 }; 568 569 snvs_poweroff: snvs-poweroff { 570 compatible = "syscon-poweroff"; 571 regmap = <&snvs>; 572 offset = <0x38>; 573 mask = <0x61>; 574 status = "disabled"; 575 }; 576 577 snvs_pwrkey: snvs-powerkey { 578 compatible = "fsl,sec-v4.0-pwrkey"; 579 regmap = <&snvs>; 580 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 581 linux,keycode = <KEY_POWER>; 582 wakeup-source; 583 status = "disabled"; 584 }; 585 }; 586 587 src: reset-controller@20d8000 { 588 compatible = "fsl,imx6sll-src", "fsl,imx51-src"; 589 reg = <0x020d8000 0x4000>; 590 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 592 #reset-cells = <1>; 593 }; 594 595 gpc: interrupt-controller@20dc000 { 596 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; 597 reg = <0x020dc000 0x4000>; 598 interrupt-controller; 599 #interrupt-cells = <3>; 600 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-parent = <&intc>; 602 }; 603 604 iomuxc: pinctrl@20e0000 { 605 compatible = "fsl,imx6sll-iomuxc"; 606 reg = <0x020e0000 0x4000>; 607 }; 608 609 gpr: iomuxc-gpr@20e4000 { 610 compatible = "fsl,imx6sll-iomuxc-gpr", 611 "fsl,imx6q-iomuxc-gpr", "syscon"; 612 reg = <0x020e4000 0x4000>; 613 }; 614 615 csi: csi@20e8000 { 616 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; 617 reg = <0x020e8000 0x4000>; 618 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clks IMX6SLL_CLK_DUMMY>, 620 <&clks IMX6SLL_CLK_CSI>, 621 <&clks IMX6SLL_CLK_DUMMY>; 622 clock-names = "disp-axi", "csi_mclk", "disp_dcic"; 623 status = "disabled"; 624 }; 625 626 sdma: dma-controller@20ec000 { 627 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; 628 reg = <0x020ec000 0x4000>; 629 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&clks IMX6SLL_CLK_IPG>, 631 <&clks IMX6SLL_CLK_SDMA>; 632 clock-names = "ipg", "ahb"; 633 #dma-cells = <3>; 634 iram = <&ocram>; 635 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 636 }; 637 638 lcdif: lcd-controller@20f8000 { 639 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; 640 reg = <0x020f8000 0x4000>; 641 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, 643 <&clks IMX6SLL_CLK_LCDIF_APB>, 644 <&clks IMX6SLL_CLK_DUMMY>; 645 clock-names = "pix", "axi", "disp_axi"; 646 status = "disabled"; 647 }; 648 649 dcp: dcp@20fc000 { 650 compatible = "fsl,imx28-dcp"; 651 reg = <0x020fc000 0x4000>; 652 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&clks IMX6SLL_CLK_DCP>; 656 clock-names = "dcp"; 657 }; 658 }; 659 660 aips2: aips-bus@2100000 { 661 compatible = "fsl,aips-bus", "simple-bus"; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 reg = <0x02100000 0x100000>; 665 ranges; 666 667 usbotg1: usb@2184000 { 668 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", 669 "fsl,imx27-usb"; 670 reg = <0x02184000 0x200>; 671 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clks IMX6SLL_CLK_USBOH3>; 673 fsl,usbphy = <&usbphy1>; 674 fsl,usbmisc = <&usbmisc 0>; 675 fsl,anatop = <&anatop>; 676 ahb-burst-config = <0x0>; 677 tx-burst-size-dword = <0x10>; 678 rx-burst-size-dword = <0x10>; 679 status = "disabled"; 680 }; 681 682 usbotg2: usb@2184200 { 683 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", 684 "fsl,imx27-usb"; 685 reg = <0x02184200 0x200>; 686 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clks IMX6SLL_CLK_USBOH3>; 688 fsl,usbphy = <&usbphy2>; 689 fsl,usbmisc = <&usbmisc 1>; 690 ahb-burst-config = <0x0>; 691 tx-burst-size-dword = <0x10>; 692 rx-burst-size-dword = <0x10>; 693 status = "disabled"; 694 }; 695 696 usbmisc: usbmisc@2184800 { 697 #index-cells = <1>; 698 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", 699 "fsl,imx6q-usbmisc"; 700 reg = <0x02184800 0x200>; 701 }; 702 703 usdhc1: mmc@2190000 { 704 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 705 reg = <0x02190000 0x4000>; 706 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&clks IMX6SLL_CLK_USDHC1>, 708 <&clks IMX6SLL_CLK_USDHC1>, 709 <&clks IMX6SLL_CLK_USDHC1>; 710 clock-names = "ipg", "ahb", "per"; 711 bus-width = <4>; 712 fsl,tuning-step = <2>; 713 fsl,tuning-start-tap = <20>; 714 status = "disabled"; 715 }; 716 717 usdhc2: mmc@2194000 { 718 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 719 reg = <0x02194000 0x4000>; 720 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&clks IMX6SLL_CLK_USDHC2>, 722 <&clks IMX6SLL_CLK_USDHC2>, 723 <&clks IMX6SLL_CLK_USDHC2>; 724 clock-names = "ipg", "ahb", "per"; 725 bus-width = <4>; 726 fsl,tuning-step = <2>; 727 fsl,tuning-start-tap = <20>; 728 status = "disabled"; 729 }; 730 731 usdhc3: mmc@2198000 { 732 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 733 reg = <0x02198000 0x4000>; 734 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&clks IMX6SLL_CLK_USDHC3>, 736 <&clks IMX6SLL_CLK_USDHC3>, 737 <&clks IMX6SLL_CLK_USDHC3>; 738 clock-names = "ipg", "ahb", "per"; 739 bus-width = <4>; 740 fsl,tuning-step = <2>; 741 fsl,tuning-start-tap = <20>; 742 status = "disabled"; 743 }; 744 745 i2c1: i2c@21a0000 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 749 reg = <0x021a0000 0x4000>; 750 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&clks IMX6SLL_CLK_I2C1>; 752 status = "disabled"; 753 }; 754 755 i2c2: i2c@21a4000 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 759 reg = <0x021a4000 0x4000>; 760 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clks IMX6SLL_CLK_I2C2>; 762 status = "disabled"; 763 }; 764 765 i2c3: i2c@21a8000 { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 769 reg = <0x021a8000 0x4000>; 770 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&clks IMX6SLL_CLK_I2C3>; 772 status = "disabled"; 773 }; 774 775 mmdc: memory-controller@21b0000 { 776 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; 777 reg = <0x021b0000 0x4000>; 778 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; 779 }; 780 781 ocotp: ocotp-ctrl@21bc000 { 782 #address-cells = <1>; 783 #size-cells = <1>; 784 compatible = "fsl,imx6sll-ocotp", "syscon"; 785 reg = <0x021bc000 0x4000>; 786 clocks = <&clks IMX6SLL_CLK_OCOTP>; 787 788 tempmon_calib: calib@38 { 789 reg = <0x38 4>; 790 }; 791 792 tempmon_temp_grade: temp-grade@20 { 793 reg = <0x20 4>; 794 }; 795 }; 796 797 audmux: audmux@21d8000 { 798 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; 799 reg = <0x021d8000 0x4000>; 800 status = "disabled"; 801 }; 802 803 uart5: serial@21f4000 { 804 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", 805 "fsl,imx21-uart"; 806 reg = <0x021f4000 0x4000>; 807 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 808 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 809 dma-names = "rx", "tx"; 810 clocks = <&clks IMX6SLL_CLK_UART5_IPG>, 811 <&clks IMX6SLL_CLK_UART5_SERIAL>; 812 clock-names = "ipg", "per"; 813 status = "disabled"; 814 }; 815 }; 816 }; 817}; 818