1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2014 Carlo Caione <carlo@caione.org> 4 */ 5 6#include <dt-bindings/clock/meson8b-clkc.h> 7#include <dt-bindings/gpio/meson8-gpio.h> 8#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 9#include <dt-bindings/reset/amlogic,meson8b-reset.h> 10#include "meson.dtsi" 11 12/ { 13 model = "Amlogic Meson8 SoC"; 14 compatible = "amlogic,meson8"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@200 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a9"; 23 next-level-cache = <&L2>; 24 reg = <0x200>; 25 enable-method = "amlogic,meson8-smp"; 26 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 27 operating-points-v2 = <&cpu_opp_table>; 28 clocks = <&clkc CLKID_CPUCLK>; 29 }; 30 31 cpu1: cpu@201 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 next-level-cache = <&L2>; 35 reg = <0x201>; 36 enable-method = "amlogic,meson8-smp"; 37 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 38 operating-points-v2 = <&cpu_opp_table>; 39 clocks = <&clkc CLKID_CPUCLK>; 40 }; 41 42 cpu2: cpu@202 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a9"; 45 next-level-cache = <&L2>; 46 reg = <0x202>; 47 enable-method = "amlogic,meson8-smp"; 48 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 49 operating-points-v2 = <&cpu_opp_table>; 50 clocks = <&clkc CLKID_CPUCLK>; 51 }; 52 53 cpu3: cpu@203 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 next-level-cache = <&L2>; 57 reg = <0x203>; 58 enable-method = "amlogic,meson8-smp"; 59 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 60 operating-points-v2 = <&cpu_opp_table>; 61 clocks = <&clkc CLKID_CPUCLK>; 62 }; 63 }; 64 65 cpu_opp_table: opp-table { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp-96000000 { 70 opp-hz = /bits/ 64 <96000000>; 71 opp-microvolt = <825000>; 72 }; 73 opp-192000000 { 74 opp-hz = /bits/ 64 <192000000>; 75 opp-microvolt = <825000>; 76 }; 77 opp-312000000 { 78 opp-hz = /bits/ 64 <312000000>; 79 opp-microvolt = <825000>; 80 }; 81 opp-408000000 { 82 opp-hz = /bits/ 64 <408000000>; 83 opp-microvolt = <825000>; 84 }; 85 opp-504000000 { 86 opp-hz = /bits/ 64 <504000000>; 87 opp-microvolt = <825000>; 88 }; 89 opp-600000000 { 90 opp-hz = /bits/ 64 <600000000>; 91 opp-microvolt = <850000>; 92 }; 93 opp-720000000 { 94 opp-hz = /bits/ 64 <720000000>; 95 opp-microvolt = <850000>; 96 }; 97 opp-816000000 { 98 opp-hz = /bits/ 64 <816000000>; 99 opp-microvolt = <875000>; 100 }; 101 opp-1008000000 { 102 opp-hz = /bits/ 64 <1008000000>; 103 opp-microvolt = <925000>; 104 }; 105 opp-1200000000 { 106 opp-hz = /bits/ 64 <1200000000>; 107 opp-microvolt = <975000>; 108 }; 109 opp-1416000000 { 110 opp-hz = /bits/ 64 <1416000000>; 111 opp-microvolt = <1025000>; 112 }; 113 opp-1608000000 { 114 opp-hz = /bits/ 64 <1608000000>; 115 opp-microvolt = <1100000>; 116 }; 117 opp-1800000000 { 118 status = "disabled"; 119 opp-hz = /bits/ 64 <1800000000>; 120 opp-microvolt = <1125000>; 121 }; 122 opp-1992000000 { 123 status = "disabled"; 124 opp-hz = /bits/ 64 <1992000000>; 125 opp-microvolt = <1150000>; 126 }; 127 }; 128 129 gpu_opp_table: gpu-opp-table { 130 compatible = "operating-points-v2"; 131 132 opp-182142857 { 133 opp-hz = /bits/ 64 <182142857>; 134 opp-microvolt = <1150000>; 135 }; 136 opp-318750000 { 137 opp-hz = /bits/ 64 <318750000>; 138 opp-microvolt = <1150000>; 139 }; 140 opp-425000000 { 141 opp-hz = /bits/ 64 <425000000>; 142 opp-microvolt = <1150000>; 143 }; 144 opp-510000000 { 145 opp-hz = /bits/ 64 <510000000>; 146 opp-microvolt = <1150000>; 147 }; 148 opp-637500000 { 149 opp-hz = /bits/ 64 <637500000>; 150 opp-microvolt = <1150000>; 151 turbo-mode; 152 }; 153 }; 154 155 pmu { 156 compatible = "arm,cortex-a9-pmu"; 157 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 161 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 162 }; 163 164 reserved-memory { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges; 168 169 /* 2 MiB reserved for Hardware ROM Firmware? */ 170 hwrom@0 { 171 reg = <0x0 0x200000>; 172 no-map; 173 }; 174 175 /* 176 * 1 MiB reserved for the "ARM Power Firmware": this is ARM 177 * code which is responsible for system suspend. It loads a 178 * piece of ARC code ("arc_power" in the vendor u-boot tree) 179 * into SRAM, executes that and shuts down the (last) ARM core. 180 * The arc_power firmware then checks various wakeup sources 181 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or 182 * simply the power key) and re-starts the ARM core once it 183 * detects a wakeup request. 184 */ 185 power-firmware@4f00000 { 186 reg = <0x4f00000 0x100000>; 187 no-map; 188 }; 189 }; 190 191 mmcbus: bus@c8000000 { 192 compatible = "simple-bus"; 193 reg = <0xc8000000 0x8000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges = <0x0 0xc8000000 0x8000>; 197 198 dmcbus: bus@6000 { 199 compatible = "simple-bus"; 200 reg = <0x6000 0x400>; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges = <0x0 0x6000 0x400>; 204 205 canvas: video-lut@20 { 206 compatible = "amlogic,meson8-canvas", 207 "amlogic,canvas"; 208 reg = <0x20 0x14>; 209 }; 210 }; 211 }; 212 213 apb: bus@d0000000 { 214 compatible = "simple-bus"; 215 reg = <0xd0000000 0x200000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges = <0x0 0xd0000000 0x200000>; 219 220 mali: gpu@c0000 { 221 compatible = "amlogic,meson8-mali", "arm,mali-450"; 222 reg = <0xc0000 0x40000>; 223 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 239 interrupt-names = "gp", "gpmmu", "pp", "pmu", 240 "pp0", "ppmmu0", "pp1", "ppmmu1", 241 "pp2", "ppmmu2", "pp4", "ppmmu4", 242 "pp5", "ppmmu5", "pp6", "ppmmu6"; 243 resets = <&reset RESET_MALI>; 244 245 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 246 clock-names = "bus", "core"; 247 248 assigned-clocks = <&clkc CLKID_MALI>; 249 assigned-clock-rates = <318750000>; 250 251 operating-points-v2 = <&gpu_opp_table>; 252 }; 253 }; 254}; /* end of / */ 255 256&aobus { 257 pmu: pmu@e0 { 258 compatible = "amlogic,meson8-pmu", "syscon"; 259 reg = <0xe0 0x18>; 260 }; 261 262 pinctrl_aobus: pinctrl@84 { 263 compatible = "amlogic,meson8-aobus-pinctrl"; 264 reg = <0x84 0xc>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges; 268 269 gpio_ao: ao-bank@14 { 270 reg = <0x14 0x4>, 271 <0x2c 0x4>, 272 <0x24 0x8>; 273 reg-names = "mux", "pull", "gpio"; 274 gpio-controller; 275 #gpio-cells = <2>; 276 gpio-ranges = <&pinctrl_aobus 0 0 16>; 277 }; 278 279 uart_ao_a_pins: uart_ao_a { 280 mux { 281 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 282 function = "uart_ao"; 283 bias-disable; 284 }; 285 }; 286 287 i2c_ao_pins: i2c_mst_ao { 288 mux { 289 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; 290 function = "i2c_mst_ao"; 291 bias-disable; 292 }; 293 }; 294 295 ir_recv_pins: remote { 296 mux { 297 groups = "remote_input"; 298 function = "remote"; 299 bias-disable; 300 }; 301 }; 302 303 pwm_f_ao_pins: pwm-f-ao { 304 mux { 305 groups = "pwm_f_ao"; 306 function = "pwm_f_ao"; 307 bias-disable; 308 }; 309 }; 310 }; 311}; 312 313&cbus { 314 reset: reset-controller@4404 { 315 compatible = "amlogic,meson8b-reset"; 316 reg = <0x4404 0x9c>; 317 #reset-cells = <1>; 318 }; 319 320 analog_top: analog-top@81a8 { 321 compatible = "amlogic,meson8-analog-top", "syscon"; 322 reg = <0x81a8 0x14>; 323 }; 324 325 pwm_ef: pwm@86c0 { 326 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 327 reg = <0x86c0 0x10>; 328 #pwm-cells = <3>; 329 status = "disabled"; 330 }; 331 332 clock-measure@8758 { 333 compatible = "amlogic,meson8-clk-measure"; 334 reg = <0x8758 0x1c>; 335 }; 336 337 pinctrl_cbus: pinctrl@9880 { 338 compatible = "amlogic,meson8-cbus-pinctrl"; 339 reg = <0x9880 0x10>; 340 #address-cells = <1>; 341 #size-cells = <1>; 342 ranges; 343 344 gpio: banks@80b0 { 345 reg = <0x80b0 0x28>, 346 <0x80e8 0x18>, 347 <0x8120 0x18>, 348 <0x8030 0x30>; 349 reg-names = "mux", "pull", "pull-enable", "gpio"; 350 gpio-controller; 351 #gpio-cells = <2>; 352 gpio-ranges = <&pinctrl_cbus 0 0 120>; 353 }; 354 355 sd_a_pins: sd-a { 356 mux { 357 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", 358 "sd_d3_a", "sd_clk_a", "sd_cmd_a"; 359 function = "sd_a"; 360 bias-disable; 361 }; 362 }; 363 364 sd_b_pins: sd-b { 365 mux { 366 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 367 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 368 function = "sd_b"; 369 bias-disable; 370 }; 371 }; 372 373 sd_c_pins: sd-c { 374 mux { 375 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", 376 "sd_d3_c", "sd_clk_c", "sd_cmd_c"; 377 function = "sd_c"; 378 bias-disable; 379 }; 380 }; 381 382 spi_nor_pins: nor { 383 mux { 384 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 385 function = "nor"; 386 bias-disable; 387 }; 388 }; 389 390 eth_pins: ethernet { 391 mux { 392 groups = "eth_tx_clk_50m", "eth_tx_en", 393 "eth_txd1", "eth_txd0", 394 "eth_rx_clk_in", "eth_rx_dv", 395 "eth_rxd1", "eth_rxd0", "eth_mdio", 396 "eth_mdc"; 397 function = "ethernet"; 398 bias-disable; 399 }; 400 }; 401 402 pwm_e_pins: pwm-e { 403 mux { 404 groups = "pwm_e"; 405 function = "pwm_e"; 406 bias-disable; 407 }; 408 }; 409 410 uart_a1_pins: uart-a1 { 411 mux { 412 groups = "uart_tx_a1", 413 "uart_rx_a1"; 414 function = "uart_a"; 415 bias-disable; 416 }; 417 }; 418 419 uart_a1_cts_rts_pins: uart-a1-cts-rts { 420 mux { 421 groups = "uart_cts_a1", 422 "uart_rts_a1"; 423 function = "uart_a"; 424 bias-disable; 425 }; 426 }; 427 }; 428}; 429 430&ahb_sram { 431 smp-sram@1ff80 { 432 compatible = "amlogic,meson8-smp-sram"; 433 reg = <0x1ff80 0x8>; 434 }; 435}; 436 437&efuse { 438 compatible = "amlogic,meson8-efuse"; 439 clocks = <&clkc CLKID_EFUSE>; 440 clock-names = "core"; 441 442 temperature_calib: calib@1f4 { 443 /* only the upper two bytes are relevant */ 444 reg = <0x1f4 0x4>; 445 }; 446}; 447 448ðmac { 449 clocks = <&clkc CLKID_ETH>; 450 clock-names = "stmmaceth"; 451}; 452 453&gpio_intc { 454 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; 455 status = "okay"; 456}; 457 458&hhi { 459 clkc: clock-controller { 460 compatible = "amlogic,meson8-clkc"; 461 #clock-cells = <1>; 462 #reset-cells = <1>; 463 }; 464}; 465 466&hwrng { 467 compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; 468 clocks = <&clkc CLKID_RNG0>; 469 clock-names = "core"; 470}; 471 472&i2c_AO { 473 clocks = <&clkc CLKID_CLK81>; 474}; 475 476&i2c_A { 477 clocks = <&clkc CLKID_CLK81>; 478}; 479 480&i2c_B { 481 clocks = <&clkc CLKID_CLK81>; 482}; 483 484&L2 { 485 arm,data-latency = <3 3 3>; 486 arm,tag-latency = <2 2 2>; 487 arm,filter-ranges = <0x100000 0xc0000000>; 488 prefetch-data = <1>; 489 prefetch-instr = <1>; 490 arm,shared-override; 491}; 492 493&periph { 494 scu@0 { 495 compatible = "arm,cortex-a9-scu"; 496 reg = <0x0 0x100>; 497 }; 498 499 timer@200 { 500 compatible = "arm,cortex-a9-global-timer"; 501 reg = <0x200 0x20>; 502 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 503 clocks = <&clkc CLKID_PERIPH>; 504 505 /* 506 * the arm_global_timer driver currently does not handle clock 507 * rate changes. Keep it disabled for now. 508 */ 509 status = "disabled"; 510 }; 511 512 timer@600 { 513 compatible = "arm,cortex-a9-twd-timer"; 514 reg = <0x600 0x20>; 515 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 516 clocks = <&clkc CLKID_PERIPH>; 517 }; 518}; 519 520&pwm_ab { 521 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 522}; 523 524&pwm_cd { 525 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 526}; 527 528&rtc { 529 compatible = "amlogic,meson8-rtc"; 530 resets = <&reset RESET_RTC>; 531}; 532 533&saradc { 534 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; 535 clocks = <&clkc CLKID_XTAL>, 536 <&clkc CLKID_SAR_ADC>; 537 clock-names = "clkin", "core"; 538 amlogic,hhi-sysctrl = <&hhi>; 539 nvmem-cells = <&temperature_calib>; 540 nvmem-cell-names = "temperature_calib"; 541}; 542 543&sdio { 544 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; 545 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 546 clock-names = "core", "clkin"; 547}; 548 549&spifc { 550 clocks = <&clkc CLKID_CLK81>; 551}; 552 553&timer_abcde { 554 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; 555 clock-names = "xtal", "pclk"; 556}; 557 558&uart_AO { 559 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 560 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; 561 clock-names = "baud", "xtal", "pclk"; 562}; 563 564&uart_A { 565 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 566 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; 567 clock-names = "baud", "xtal", "pclk"; 568}; 569 570&uart_B { 571 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 572 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; 573 clock-names = "baud", "xtal", "pclk"; 574}; 575 576&uart_C { 577 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 578 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; 579 clock-names = "baud", "xtal", "pclk"; 580}; 581 582&usb0 { 583 compatible = "amlogic,meson8-usb", "snps,dwc2"; 584 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 585 clock-names = "otg"; 586}; 587 588&usb1 { 589 compatible = "amlogic,meson8-usb", "snps,dwc2"; 590 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 591 clock-names = "otg"; 592}; 593 594&usb0_phy { 595 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 596 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 597 clock-names = "usb_general", "usb"; 598 resets = <&reset RESET_USB_OTG>; 599}; 600 601&usb1_phy { 602 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 603 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 604 clock-names = "usb_general", "usb"; 605 resets = <&reset RESET_USB_OTG>; 606}; 607