1/* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/omap.h> 14 15/ { 16 compatible = "ti,omap3430", "ti,omap3"; 17 interrupt-parent = <&intc>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 chosen { }; 21 22 aliases { 23 i2c0 = &i2c1; 24 i2c1 = &i2c2; 25 i2c2 = &i2c3; 26 mmc0 = &mmc1; 27 mmc1 = &mmc2; 28 mmc2 = &mmc3; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,cortex-a8"; 40 device_type = "cpu"; 41 reg = <0x0>; 42 43 clocks = <&dpll1_ck>; 44 clock-names = "cpu"; 45 46 clock-latency = <300000>; /* From omap-cpufreq driver */ 47 }; 48 }; 49 50 pmu@54000000 { 51 compatible = "arm,cortex-a8-pmu"; 52 reg = <0x54000000 0x800000>; 53 interrupts = <3>; 54 ti,hwmods = "debugss"; 55 }; 56 57 /* 58 * The soc node represents the soc top level view. It is used for IPs 59 * that are not memory mapped in the MPU view or for the MPU itself. 60 */ 61 soc { 62 compatible = "ti,omap-infra"; 63 mpu { 64 compatible = "ti,omap3-mpu"; 65 ti,hwmods = "mpu"; 66 }; 67 68 iva: iva { 69 compatible = "ti,iva2.2"; 70 ti,hwmods = "iva"; 71 72 dsp { 73 compatible = "ti,omap3-c64"; 74 }; 75 }; 76 }; 77 78 /* 79 * XXX: Use a flat representation of the OMAP3 interconnect. 80 * The real OMAP interconnect network is quite complex. 81 * Since it will not bring real advantage to represent that in DT for 82 * the moment, just use a fake OCP bus entry to represent the whole bus 83 * hierarchy. 84 */ 85 ocp@68000000 { 86 compatible = "ti,omap3-l3-smx", "simple-bus"; 87 reg = <0x68000000 0x10000>; 88 interrupts = <9 10>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 ti,hwmods = "l3_main"; 93 94 l4_core: l4@48000000 { 95 compatible = "ti,omap3-l4-core", "simple-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges = <0 0x48000000 0x1000000>; 99 100 scm: scm@2000 { 101 compatible = "ti,omap3-scm", "simple-bus"; 102 reg = <0x2000 0x2000>; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 ranges = <0 0x2000 0x2000>; 106 107 omap3_pmx_core: pinmux@30 { 108 compatible = "ti,omap3-padconf", 109 "pinctrl-single"; 110 reg = <0x30 0x238>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 #pinctrl-cells = <1>; 114 #interrupt-cells = <1>; 115 interrupt-controller; 116 pinctrl-single,register-width = <16>; 117 pinctrl-single,function-mask = <0xff1f>; 118 }; 119 120 scm_conf: scm_conf@270 { 121 compatible = "syscon", "simple-bus"; 122 reg = <0x270 0x330>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0x270 0x330>; 126 127 pbias_regulator: pbias_regulator@2b0 { 128 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 129 reg = <0x2b0 0x4>; 130 syscon = <&scm_conf>; 131 pbias_mmc_reg: pbias_mmc_omap2430 { 132 regulator-name = "pbias_mmc_omap2430"; 133 regulator-min-microvolt = <1800000>; 134 regulator-max-microvolt = <3000000>; 135 }; 136 }; 137 138 scm_clocks: clocks { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 }; 142 }; 143 144 scm_clockdomains: clockdomains { 145 }; 146 147 omap3_pmx_wkup: pinmux@a00 { 148 compatible = "ti,omap3-padconf", 149 "pinctrl-single"; 150 reg = <0xa00 0x5c>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 #pinctrl-cells = <1>; 154 #interrupt-cells = <1>; 155 interrupt-controller; 156 pinctrl-single,register-width = <16>; 157 pinctrl-single,function-mask = <0xff1f>; 158 }; 159 }; 160 }; 161 162 aes: aes@480c5000 { 163 compatible = "ti,omap3-aes"; 164 ti,hwmods = "aes"; 165 reg = <0x480c5000 0x50>; 166 interrupts = <0>; 167 dmas = <&sdma 65 &sdma 66>; 168 dma-names = "tx", "rx"; 169 }; 170 171 prm: prm@48306000 { 172 compatible = "ti,omap3-prm"; 173 reg = <0x48306000 0x4000>; 174 interrupts = <11>; 175 176 prm_clocks: clocks { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 }; 180 181 prm_clockdomains: clockdomains { 182 }; 183 }; 184 185 cm: cm@48004000 { 186 compatible = "ti,omap3-cm"; 187 reg = <0x48004000 0x4000>; 188 189 cm_clocks: clocks { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 }; 193 194 cm_clockdomains: clockdomains { 195 }; 196 }; 197 198 counter32k: counter@48320000 { 199 compatible = "ti,omap-counter32k"; 200 reg = <0x48320000 0x20>; 201 ti,hwmods = "counter_32k"; 202 }; 203 204 intc: interrupt-controller@48200000 { 205 compatible = "ti,omap3-intc"; 206 interrupt-controller; 207 #interrupt-cells = <1>; 208 reg = <0x48200000 0x1000>; 209 }; 210 211 sdma: dma-controller@48056000 { 212 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; 213 reg = <0x48056000 0x1000>; 214 interrupts = <12>, 215 <13>, 216 <14>, 217 <15>; 218 #dma-cells = <1>; 219 dma-channels = <32>; 220 dma-requests = <96>; 221 ti,hwmods = "dma"; 222 }; 223 224 gpio1: gpio@48310000 { 225 compatible = "ti,omap3-gpio"; 226 reg = <0x48310000 0x200>; 227 interrupts = <29>; 228 ti,hwmods = "gpio1"; 229 ti,gpio-always-on; 230 gpio-controller; 231 #gpio-cells = <2>; 232 interrupt-controller; 233 #interrupt-cells = <2>; 234 }; 235 236 gpio2: gpio@49050000 { 237 compatible = "ti,omap3-gpio"; 238 reg = <0x49050000 0x200>; 239 interrupts = <30>; 240 ti,hwmods = "gpio2"; 241 gpio-controller; 242 #gpio-cells = <2>; 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 }; 246 247 gpio3: gpio@49052000 { 248 compatible = "ti,omap3-gpio"; 249 reg = <0x49052000 0x200>; 250 interrupts = <31>; 251 ti,hwmods = "gpio3"; 252 gpio-controller; 253 #gpio-cells = <2>; 254 interrupt-controller; 255 #interrupt-cells = <2>; 256 }; 257 258 gpio4: gpio@49054000 { 259 compatible = "ti,omap3-gpio"; 260 reg = <0x49054000 0x200>; 261 interrupts = <32>; 262 ti,hwmods = "gpio4"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 }; 268 269 gpio5: gpio@49056000 { 270 compatible = "ti,omap3-gpio"; 271 reg = <0x49056000 0x200>; 272 interrupts = <33>; 273 ti,hwmods = "gpio5"; 274 gpio-controller; 275 #gpio-cells = <2>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 }; 279 280 gpio6: gpio@49058000 { 281 compatible = "ti,omap3-gpio"; 282 reg = <0x49058000 0x200>; 283 interrupts = <34>; 284 ti,hwmods = "gpio6"; 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 }; 290 291 uart1: serial@4806a000 { 292 compatible = "ti,omap3-uart"; 293 reg = <0x4806a000 0x2000>; 294 interrupts-extended = <&intc 72>; 295 dmas = <&sdma 49 &sdma 50>; 296 dma-names = "tx", "rx"; 297 ti,hwmods = "uart1"; 298 clock-frequency = <48000000>; 299 }; 300 301 uart2: serial@4806c000 { 302 compatible = "ti,omap3-uart"; 303 reg = <0x4806c000 0x400>; 304 interrupts-extended = <&intc 73>; 305 dmas = <&sdma 51 &sdma 52>; 306 dma-names = "tx", "rx"; 307 ti,hwmods = "uart2"; 308 clock-frequency = <48000000>; 309 }; 310 311 uart3: serial@49020000 { 312 compatible = "ti,omap3-uart"; 313 reg = <0x49020000 0x400>; 314 interrupts-extended = <&intc 74>; 315 dmas = <&sdma 53 &sdma 54>; 316 dma-names = "tx", "rx"; 317 ti,hwmods = "uart3"; 318 clock-frequency = <48000000>; 319 }; 320 321 i2c1: i2c@48070000 { 322 compatible = "ti,omap3-i2c"; 323 reg = <0x48070000 0x80>; 324 interrupts = <56>; 325 dmas = <&sdma 27 &sdma 28>; 326 dma-names = "tx", "rx"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 ti,hwmods = "i2c1"; 330 }; 331 332 i2c2: i2c@48072000 { 333 compatible = "ti,omap3-i2c"; 334 reg = <0x48072000 0x80>; 335 interrupts = <57>; 336 dmas = <&sdma 29 &sdma 30>; 337 dma-names = "tx", "rx"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 ti,hwmods = "i2c2"; 341 }; 342 343 i2c3: i2c@48060000 { 344 compatible = "ti,omap3-i2c"; 345 reg = <0x48060000 0x80>; 346 interrupts = <61>; 347 dmas = <&sdma 25 &sdma 26>; 348 dma-names = "tx", "rx"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 ti,hwmods = "i2c3"; 352 }; 353 354 mailbox: mailbox@48094000 { 355 compatible = "ti,omap3-mailbox"; 356 ti,hwmods = "mailbox"; 357 reg = <0x48094000 0x200>; 358 interrupts = <26>; 359 #mbox-cells = <1>; 360 ti,mbox-num-users = <2>; 361 ti,mbox-num-fifos = <2>; 362 mbox_dsp: dsp { 363 ti,mbox-tx = <0 0 0>; 364 ti,mbox-rx = <1 0 0>; 365 }; 366 }; 367 368 mcspi1: spi@48098000 { 369 compatible = "ti,omap2-mcspi"; 370 reg = <0x48098000 0x100>; 371 interrupts = <65>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 ti,hwmods = "mcspi1"; 375 ti,spi-num-cs = <4>; 376 dmas = <&sdma 35>, 377 <&sdma 36>, 378 <&sdma 37>, 379 <&sdma 38>, 380 <&sdma 39>, 381 <&sdma 40>, 382 <&sdma 41>, 383 <&sdma 42>; 384 dma-names = "tx0", "rx0", "tx1", "rx1", 385 "tx2", "rx2", "tx3", "rx3"; 386 }; 387 388 mcspi2: spi@4809a000 { 389 compatible = "ti,omap2-mcspi"; 390 reg = <0x4809a000 0x100>; 391 interrupts = <66>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 ti,hwmods = "mcspi2"; 395 ti,spi-num-cs = <2>; 396 dmas = <&sdma 43>, 397 <&sdma 44>, 398 <&sdma 45>, 399 <&sdma 46>; 400 dma-names = "tx0", "rx0", "tx1", "rx1"; 401 }; 402 403 mcspi3: spi@480b8000 { 404 compatible = "ti,omap2-mcspi"; 405 reg = <0x480b8000 0x100>; 406 interrupts = <91>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 ti,hwmods = "mcspi3"; 410 ti,spi-num-cs = <2>; 411 dmas = <&sdma 15>, 412 <&sdma 16>, 413 <&sdma 23>, 414 <&sdma 24>; 415 dma-names = "tx0", "rx0", "tx1", "rx1"; 416 }; 417 418 mcspi4: spi@480ba000 { 419 compatible = "ti,omap2-mcspi"; 420 reg = <0x480ba000 0x100>; 421 interrupts = <48>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 ti,hwmods = "mcspi4"; 425 ti,spi-num-cs = <1>; 426 dmas = <&sdma 70>, <&sdma 71>; 427 dma-names = "tx0", "rx0"; 428 }; 429 430 hdqw1w: 1w@480b2000 { 431 compatible = "ti,omap3-1w"; 432 reg = <0x480b2000 0x1000>; 433 interrupts = <58>; 434 ti,hwmods = "hdq1w"; 435 }; 436 437 mmc1: mmc@4809c000 { 438 compatible = "ti,omap3-hsmmc"; 439 reg = <0x4809c000 0x200>; 440 interrupts = <83>; 441 ti,hwmods = "mmc1"; 442 ti,dual-volt; 443 dmas = <&sdma 61>, <&sdma 62>; 444 dma-names = "tx", "rx"; 445 pbias-supply = <&pbias_mmc_reg>; 446 }; 447 448 mmc2: mmc@480b4000 { 449 compatible = "ti,omap3-hsmmc"; 450 reg = <0x480b4000 0x200>; 451 interrupts = <86>; 452 ti,hwmods = "mmc2"; 453 dmas = <&sdma 47>, <&sdma 48>; 454 dma-names = "tx", "rx"; 455 }; 456 457 mmc3: mmc@480ad000 { 458 compatible = "ti,omap3-hsmmc"; 459 reg = <0x480ad000 0x200>; 460 interrupts = <94>; 461 ti,hwmods = "mmc3"; 462 dmas = <&sdma 77>, <&sdma 78>; 463 dma-names = "tx", "rx"; 464 }; 465 466 mmu_isp: mmu@480bd400 { 467 #iommu-cells = <0>; 468 compatible = "ti,omap2-iommu"; 469 reg = <0x480bd400 0x80>; 470 interrupts = <24>; 471 ti,hwmods = "mmu_isp"; 472 ti,#tlb-entries = <8>; 473 }; 474 475 mmu_iva: mmu@5d000000 { 476 #iommu-cells = <0>; 477 compatible = "ti,omap2-iommu"; 478 reg = <0x5d000000 0x80>; 479 interrupts = <28>; 480 ti,hwmods = "mmu_iva"; 481 status = "disabled"; 482 }; 483 484 wdt2: wdt@48314000 { 485 compatible = "ti,omap3-wdt"; 486 reg = <0x48314000 0x80>; 487 ti,hwmods = "wd_timer2"; 488 }; 489 490 mcbsp1: mcbsp@48074000 { 491 compatible = "ti,omap3-mcbsp"; 492 reg = <0x48074000 0xff>; 493 reg-names = "mpu"; 494 interrupts = <16>, /* OCP compliant interrupt */ 495 <59>, /* TX interrupt */ 496 <60>; /* RX interrupt */ 497 interrupt-names = "common", "tx", "rx"; 498 ti,buffer-size = <128>; 499 ti,hwmods = "mcbsp1"; 500 dmas = <&sdma 31>, 501 <&sdma 32>; 502 dma-names = "tx", "rx"; 503 clocks = <&mcbsp1_fck>; 504 clock-names = "fck"; 505 status = "disabled"; 506 }; 507 508 mcbsp2: mcbsp@49022000 { 509 compatible = "ti,omap3-mcbsp"; 510 reg = <0x49022000 0xff>, 511 <0x49028000 0xff>; 512 reg-names = "mpu", "sidetone"; 513 interrupts = <17>, /* OCP compliant interrupt */ 514 <62>, /* TX interrupt */ 515 <63>, /* RX interrupt */ 516 <4>; /* Sidetone */ 517 interrupt-names = "common", "tx", "rx", "sidetone"; 518 ti,buffer-size = <1280>; 519 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 520 dmas = <&sdma 33>, 521 <&sdma 34>; 522 dma-names = "tx", "rx"; 523 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; 524 clock-names = "fck", "ick"; 525 status = "disabled"; 526 }; 527 528 mcbsp3: mcbsp@49024000 { 529 compatible = "ti,omap3-mcbsp"; 530 reg = <0x49024000 0xff>, 531 <0x4902a000 0xff>; 532 reg-names = "mpu", "sidetone"; 533 interrupts = <22>, /* OCP compliant interrupt */ 534 <89>, /* TX interrupt */ 535 <90>, /* RX interrupt */ 536 <5>; /* Sidetone */ 537 interrupt-names = "common", "tx", "rx", "sidetone"; 538 ti,buffer-size = <128>; 539 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 540 dmas = <&sdma 17>, 541 <&sdma 18>; 542 dma-names = "tx", "rx"; 543 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; 544 clock-names = "fck", "ick"; 545 status = "disabled"; 546 }; 547 548 mcbsp4: mcbsp@49026000 { 549 compatible = "ti,omap3-mcbsp"; 550 reg = <0x49026000 0xff>; 551 reg-names = "mpu"; 552 interrupts = <23>, /* OCP compliant interrupt */ 553 <54>, /* TX interrupt */ 554 <55>; /* RX interrupt */ 555 interrupt-names = "common", "tx", "rx"; 556 ti,buffer-size = <128>; 557 ti,hwmods = "mcbsp4"; 558 dmas = <&sdma 19>, 559 <&sdma 20>; 560 dma-names = "tx", "rx"; 561 clocks = <&mcbsp4_fck>; 562 clock-names = "fck"; 563 #sound-dai-cells = <0>; 564 status = "disabled"; 565 }; 566 567 mcbsp5: mcbsp@48096000 { 568 compatible = "ti,omap3-mcbsp"; 569 reg = <0x48096000 0xff>; 570 reg-names = "mpu"; 571 interrupts = <27>, /* OCP compliant interrupt */ 572 <81>, /* TX interrupt */ 573 <82>; /* RX interrupt */ 574 interrupt-names = "common", "tx", "rx"; 575 ti,buffer-size = <128>; 576 ti,hwmods = "mcbsp5"; 577 dmas = <&sdma 21>, 578 <&sdma 22>; 579 dma-names = "tx", "rx"; 580 clocks = <&mcbsp5_fck>; 581 clock-names = "fck"; 582 status = "disabled"; 583 }; 584 585 sham: sham@480c3000 { 586 compatible = "ti,omap3-sham"; 587 ti,hwmods = "sham"; 588 reg = <0x480c3000 0x64>; 589 interrupts = <49>; 590 dmas = <&sdma 69>; 591 dma-names = "rx"; 592 }; 593 594 timer1: timer@48318000 { 595 compatible = "ti,omap3430-timer"; 596 reg = <0x48318000 0x400>; 597 interrupts = <37>; 598 ti,hwmods = "timer1"; 599 ti,timer-alwon; 600 }; 601 602 timer2: timer@49032000 { 603 compatible = "ti,omap3430-timer"; 604 reg = <0x49032000 0x400>; 605 interrupts = <38>; 606 ti,hwmods = "timer2"; 607 }; 608 609 timer3: timer@49034000 { 610 compatible = "ti,omap3430-timer"; 611 reg = <0x49034000 0x400>; 612 interrupts = <39>; 613 ti,hwmods = "timer3"; 614 }; 615 616 timer4: timer@49036000 { 617 compatible = "ti,omap3430-timer"; 618 reg = <0x49036000 0x400>; 619 interrupts = <40>; 620 ti,hwmods = "timer4"; 621 }; 622 623 timer5: timer@49038000 { 624 compatible = "ti,omap3430-timer"; 625 reg = <0x49038000 0x400>; 626 interrupts = <41>; 627 ti,hwmods = "timer5"; 628 ti,timer-dsp; 629 }; 630 631 timer6: timer@4903a000 { 632 compatible = "ti,omap3430-timer"; 633 reg = <0x4903a000 0x400>; 634 interrupts = <42>; 635 ti,hwmods = "timer6"; 636 ti,timer-dsp; 637 }; 638 639 timer7: timer@4903c000 { 640 compatible = "ti,omap3430-timer"; 641 reg = <0x4903c000 0x400>; 642 interrupts = <43>; 643 ti,hwmods = "timer7"; 644 ti,timer-dsp; 645 }; 646 647 timer8: timer@4903e000 { 648 compatible = "ti,omap3430-timer"; 649 reg = <0x4903e000 0x400>; 650 interrupts = <44>; 651 ti,hwmods = "timer8"; 652 ti,timer-pwm; 653 ti,timer-dsp; 654 }; 655 656 timer9: timer@49040000 { 657 compatible = "ti,omap3430-timer"; 658 reg = <0x49040000 0x400>; 659 interrupts = <45>; 660 ti,hwmods = "timer9"; 661 ti,timer-pwm; 662 }; 663 664 timer10: timer@48086000 { 665 compatible = "ti,omap3430-timer"; 666 reg = <0x48086000 0x400>; 667 interrupts = <46>; 668 ti,hwmods = "timer10"; 669 ti,timer-pwm; 670 }; 671 672 timer11: timer@48088000 { 673 compatible = "ti,omap3430-timer"; 674 reg = <0x48088000 0x400>; 675 interrupts = <47>; 676 ti,hwmods = "timer11"; 677 ti,timer-pwm; 678 }; 679 680 timer12: timer@48304000 { 681 compatible = "ti,omap3430-timer"; 682 reg = <0x48304000 0x400>; 683 interrupts = <95>; 684 ti,hwmods = "timer12"; 685 ti,timer-alwon; 686 ti,timer-secure; 687 }; 688 689 usbhstll: usbhstll@48062000 { 690 compatible = "ti,usbhs-tll"; 691 reg = <0x48062000 0x1000>; 692 interrupts = <78>; 693 ti,hwmods = "usb_tll_hs"; 694 }; 695 696 usbhshost: usbhshost@48064000 { 697 compatible = "ti,usbhs-host"; 698 reg = <0x48064000 0x400>; 699 ti,hwmods = "usb_host_hs"; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges; 703 704 usbhsohci: ohci@48064400 { 705 compatible = "ti,ohci-omap3"; 706 reg = <0x48064400 0x400>; 707 interrupts = <76>; 708 remote-wakeup-connected; 709 }; 710 711 usbhsehci: ehci@48064800 { 712 compatible = "ti,ehci-omap"; 713 reg = <0x48064800 0x400>; 714 interrupts = <77>; 715 }; 716 }; 717 718 gpmc: gpmc@6e000000 { 719 compatible = "ti,omap3430-gpmc"; 720 ti,hwmods = "gpmc"; 721 reg = <0x6e000000 0x02d0>; 722 interrupts = <20>; 723 dmas = <&sdma 4>; 724 dma-names = "rxtx"; 725 gpmc,num-cs = <8>; 726 gpmc,num-waitpins = <4>; 727 #address-cells = <2>; 728 #size-cells = <1>; 729 interrupt-controller; 730 #interrupt-cells = <2>; 731 gpio-controller; 732 #gpio-cells = <2>; 733 }; 734 735 usb_otg_hs: usb_otg_hs@480ab000 { 736 compatible = "ti,omap3-musb"; 737 reg = <0x480ab000 0x1000>; 738 interrupts = <92>, <93>; 739 interrupt-names = "mc", "dma"; 740 ti,hwmods = "usb_otg_hs"; 741 multipoint = <1>; 742 num-eps = <16>; 743 ram-bits = <12>; 744 }; 745 746 dss: dss@48050000 { 747 compatible = "ti,omap3-dss"; 748 reg = <0x48050000 0x200>; 749 status = "disabled"; 750 ti,hwmods = "dss_core"; 751 clocks = <&dss1_alwon_fck>; 752 clock-names = "fck"; 753 #address-cells = <1>; 754 #size-cells = <1>; 755 ranges; 756 757 dispc@48050400 { 758 compatible = "ti,omap3-dispc"; 759 reg = <0x48050400 0x400>; 760 interrupts = <25>; 761 ti,hwmods = "dss_dispc"; 762 clocks = <&dss1_alwon_fck>; 763 clock-names = "fck"; 764 }; 765 766 dsi: encoder@4804fc00 { 767 compatible = "ti,omap3-dsi"; 768 reg = <0x4804fc00 0x200>, 769 <0x4804fe00 0x40>, 770 <0x4804ff00 0x20>; 771 reg-names = "proto", "phy", "pll"; 772 interrupts = <25>; 773 status = "disabled"; 774 ti,hwmods = "dss_dsi1"; 775 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 776 clock-names = "fck", "sys_clk"; 777 }; 778 779 rfbi: encoder@48050800 { 780 compatible = "ti,omap3-rfbi"; 781 reg = <0x48050800 0x100>; 782 status = "disabled"; 783 ti,hwmods = "dss_rfbi"; 784 clocks = <&dss1_alwon_fck>, <&dss_ick>; 785 clock-names = "fck", "ick"; 786 }; 787 788 venc: encoder@48050c00 { 789 compatible = "ti,omap3-venc"; 790 reg = <0x48050c00 0x100>; 791 status = "disabled"; 792 ti,hwmods = "dss_venc"; 793 clocks = <&dss_tv_fck>; 794 clock-names = "fck"; 795 }; 796 }; 797 798 ssi: ssi-controller@48058000 { 799 compatible = "ti,omap3-ssi"; 800 ti,hwmods = "ssi"; 801 802 status = "disabled"; 803 804 reg = <0x48058000 0x1000>, 805 <0x48059000 0x1000>; 806 reg-names = "sys", 807 "gdd"; 808 809 interrupts = <71>; 810 interrupt-names = "gdd_mpu"; 811 812 #address-cells = <1>; 813 #size-cells = <1>; 814 ranges; 815 816 ssi_port1: ssi-port@4805a000 { 817 compatible = "ti,omap3-ssi-port"; 818 819 reg = <0x4805a000 0x800>, 820 <0x4805a800 0x800>; 821 reg-names = "tx", 822 "rx"; 823 824 interrupts = <67>, 825 <68>; 826 }; 827 828 ssi_port2: ssi-port@4805b000 { 829 compatible = "ti,omap3-ssi-port"; 830 831 reg = <0x4805b000 0x800>, 832 <0x4805b800 0x800>; 833 reg-names = "tx", 834 "rx"; 835 836 interrupts = <69>, 837 <70>; 838 }; 839 }; 840 }; 841}; 842 843/include/ "omap3xxx-clocks.dtsi" 844