1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Marvell Technology Group Ltd. 4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 5 */ 6 7#include <dt-bindings/clock/marvell,pxa168.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 aliases { 14 serial0 = &uart1; 15 serial1 = &uart2; 16 serial2 = &uart3; 17 i2c0 = &twsi1; 18 i2c1 = &twsi2; 19 }; 20 21 soc { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 compatible = "simple-bus"; 25 interrupt-parent = <&intc>; 26 ranges; 27 28 axi@d4200000 { /* AXI */ 29 compatible = "mrvl,axi-bus", "simple-bus"; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 reg = <0xd4200000 0x00200000>; 33 ranges; 34 35 intc: interrupt-controller@d4282000 { 36 compatible = "mrvl,mmp-intc"; 37 interrupt-controller; 38 #interrupt-cells = <1>; 39 reg = <0xd4282000 0x1000>; 40 mrvl,intc-nr-irqs = <64>; 41 }; 42 43 }; 44 45 apb@d4000000 { /* APB */ 46 compatible = "mrvl,apb-bus", "simple-bus"; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 reg = <0xd4000000 0x00200000>; 50 ranges; 51 52 timer0: timer@d4014000 { 53 compatible = "mrvl,mmp-timer"; 54 reg = <0xd4014000 0x100>; 55 interrupts = <13>; 56 }; 57 58 uart1: uart@d4017000 { 59 compatible = "mrvl,mmp-uart"; 60 reg = <0xd4017000 0x1000>; 61 interrupts = <27>; 62 clocks = <&soc_clocks PXA168_CLK_UART0>; 63 resets = <&soc_clocks PXA168_CLK_UART0>; 64 status = "disabled"; 65 }; 66 67 uart2: uart@d4018000 { 68 compatible = "mrvl,mmp-uart"; 69 reg = <0xd4018000 0x1000>; 70 interrupts = <28>; 71 clocks = <&soc_clocks PXA168_CLK_UART1>; 72 resets = <&soc_clocks PXA168_CLK_UART1>; 73 status = "disabled"; 74 }; 75 76 uart3: uart@d4026000 { 77 compatible = "mrvl,mmp-uart"; 78 reg = <0xd4026000 0x1000>; 79 interrupts = <29>; 80 clocks = <&soc_clocks PXA168_CLK_UART2>; 81 resets = <&soc_clocks PXA168_CLK_UART2>; 82 status = "disabled"; 83 }; 84 85 gpio@d4019000 { 86 compatible = "marvell,mmp-gpio"; 87 #address-cells = <1>; 88 #size-cells = <1>; 89 reg = <0xd4019000 0x1000>; 90 gpio-controller; 91 #gpio-cells = <2>; 92 interrupts = <49>; 93 clocks = <&soc_clocks PXA168_CLK_GPIO>; 94 resets = <&soc_clocks PXA168_CLK_GPIO>; 95 interrupt-names = "gpio_mux"; 96 interrupt-controller; 97 #interrupt-cells = <1>; 98 ranges; 99 100 gcb0: gpio@d4019000 { 101 reg = <0xd4019000 0x4>; 102 }; 103 104 gcb1: gpio@d4019004 { 105 reg = <0xd4019004 0x4>; 106 }; 107 108 gcb2: gpio@d4019008 { 109 reg = <0xd4019008 0x4>; 110 }; 111 112 gcb3: gpio@d4019100 { 113 reg = <0xd4019100 0x4>; 114 }; 115 }; 116 117 twsi1: i2c@d4011000 { 118 compatible = "mrvl,mmp-twsi"; 119 reg = <0xd4011000 0x1000>; 120 interrupts = <7>; 121 clocks = <&soc_clocks PXA168_CLK_TWSI0>; 122 resets = <&soc_clocks PXA168_CLK_TWSI0>; 123 mrvl,i2c-fast-mode; 124 status = "disabled"; 125 }; 126 127 twsi2: i2c@d4025000 { 128 compatible = "mrvl,mmp-twsi"; 129 reg = <0xd4025000 0x1000>; 130 interrupts = <58>; 131 clocks = <&soc_clocks PXA168_CLK_TWSI1>; 132 resets = <&soc_clocks PXA168_CLK_TWSI1>; 133 status = "disabled"; 134 }; 135 136 rtc: rtc@d4010000 { 137 compatible = "mrvl,mmp-rtc"; 138 reg = <0xd4010000 0x1000>; 139 interrupts = <5 6>; 140 interrupt-names = "rtc 1Hz", "rtc alarm"; 141 clocks = <&soc_clocks PXA168_CLK_RTC>; 142 resets = <&soc_clocks PXA168_CLK_RTC>; 143 status = "disabled"; 144 }; 145 }; 146 147 soc_clocks: clocks{ 148 compatible = "marvell,pxa168-clock"; 149 reg = <0xd4050000 0x1000>, 150 <0xd4282800 0x400>, 151 <0xd4015000 0x1000>; 152 reg-names = "mpmu", "apmu", "apbc"; 153 #clock-cells = <1>; 154 #reset-cells = <1>; 155 }; 156 }; 157}; 158