1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Marvell Technology Group Ltd. 4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 5 */ 6 7#include <dt-bindings/clock/marvell,pxa910.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 aliases { 14 serial0 = &uart1; 15 serial1 = &uart2; 16 serial2 = &uart3; 17 i2c0 = &twsi1; 18 i2c1 = &twsi2; 19 }; 20 21 soc { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 compatible = "simple-bus"; 25 interrupt-parent = <&intc>; 26 ranges; 27 28 L2: l2-cache { 29 compatible = "marvell,tauros2-cache"; 30 marvell,tauros2-cache-features = <0x3>; 31 }; 32 33 axi@d4200000 { /* AXI */ 34 compatible = "mrvl,axi-bus", "simple-bus"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 reg = <0xd4200000 0x00200000>; 38 ranges; 39 40 intc: interrupt-controller@d4282000 { 41 compatible = "mrvl,mmp-intc"; 42 interrupt-controller; 43 #interrupt-cells = <1>; 44 reg = <0xd4282000 0x1000>; 45 mrvl,intc-nr-irqs = <64>; 46 }; 47 48 }; 49 50 apb@d4000000 { /* APB */ 51 compatible = "mrvl,apb-bus", "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 reg = <0xd4000000 0x00200000>; 55 ranges; 56 57 timer0: timer@d4014000 { 58 compatible = "mrvl,mmp-timer"; 59 reg = <0xd4014000 0x100>; 60 interrupts = <13>; 61 }; 62 63 timer1: timer@d4016000 { 64 compatible = "mrvl,mmp-timer"; 65 reg = <0xd4016000 0x100>; 66 interrupts = <29>; 67 status = "disabled"; 68 }; 69 70 uart1: uart@d4017000 { 71 compatible = "mrvl,mmp-uart"; 72 reg = <0xd4017000 0x1000>; 73 interrupts = <27>; 74 clocks = <&soc_clocks PXA910_CLK_UART0>; 75 resets = <&soc_clocks PXA910_CLK_UART0>; 76 status = "disabled"; 77 }; 78 79 uart2: uart@d4018000 { 80 compatible = "mrvl,mmp-uart"; 81 reg = <0xd4018000 0x1000>; 82 interrupts = <28>; 83 clocks = <&soc_clocks PXA910_CLK_UART1>; 84 resets = <&soc_clocks PXA910_CLK_UART1>; 85 status = "disabled"; 86 }; 87 88 uart3: uart@d4036000 { 89 compatible = "mrvl,mmp-uart"; 90 reg = <0xd4036000 0x1000>; 91 interrupts = <59>; 92 clocks = <&soc_clocks PXA910_CLK_UART2>; 93 resets = <&soc_clocks PXA910_CLK_UART2>; 94 status = "disabled"; 95 }; 96 97 gpio@d4019000 { 98 compatible = "marvell,mmp-gpio"; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 reg = <0xd4019000 0x1000>; 102 gpio-controller; 103 #gpio-cells = <2>; 104 interrupts = <49>; 105 interrupt-names = "gpio_mux"; 106 clocks = <&soc_clocks PXA910_CLK_GPIO>; 107 resets = <&soc_clocks PXA910_CLK_GPIO>; 108 interrupt-controller; 109 #interrupt-cells = <1>; 110 ranges; 111 112 gcb0: gpio@d4019000 { 113 reg = <0xd4019000 0x4>; 114 }; 115 116 gcb1: gpio@d4019004 { 117 reg = <0xd4019004 0x4>; 118 }; 119 120 gcb2: gpio@d4019008 { 121 reg = <0xd4019008 0x4>; 122 }; 123 124 gcb3: gpio@d4019100 { 125 reg = <0xd4019100 0x4>; 126 }; 127 }; 128 129 twsi1: i2c@d4011000 { 130 compatible = "mrvl,mmp-twsi"; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 reg = <0xd4011000 0x1000>; 134 interrupts = <7>; 135 clocks = <&soc_clocks PXA910_CLK_TWSI0>; 136 resets = <&soc_clocks PXA910_CLK_TWSI0>; 137 mrvl,i2c-fast-mode; 138 status = "disabled"; 139 }; 140 141 twsi2: i2c@d4037000 { 142 compatible = "mrvl,mmp-twsi"; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 reg = <0xd4037000 0x1000>; 146 interrupts = <54>; 147 clocks = <&soc_clocks PXA910_CLK_TWSI1>; 148 resets = <&soc_clocks PXA910_CLK_TWSI1>; 149 status = "disabled"; 150 }; 151 152 rtc: rtc@d4010000 { 153 compatible = "mrvl,mmp-rtc"; 154 reg = <0xd4010000 0x1000>; 155 interrupts = <5 6>; 156 interrupt-names = "rtc 1Hz", "rtc alarm"; 157 clocks = <&soc_clocks PXA910_CLK_RTC>; 158 resets = <&soc_clocks PXA910_CLK_RTC>; 159 status = "disabled"; 160 }; 161 }; 162 163 soc_clocks: clocks{ 164 compatible = "marvell,pxa910-clock"; 165 reg = <0xd4050000 0x1000>, 166 <0xd4282800 0x400>, 167 <0xd4015000 0x1000>, 168 <0xd403b000 0x1000>; 169 reg-names = "mpmu", "apmu", "apbc", "apbcp"; 170 #clock-cells = <1>; 171 #reset-cells = <1>; 172 }; 173 }; 174}; 175