1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/reset/qcom,gcc-msm8960.h> 6#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/soc/qcom,gsbi.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 model = "Qualcomm APQ8064"; 15 compatible = "qcom,apq8064"; 16 interrupt-parent = <&intc>; 17 18 reserved-memory { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges; 22 23 smem_region: smem@80000000 { 24 reg = <0x80000000 0x200000>; 25 no-map; 26 }; 27 28 wcnss_mem: wcnss@8f000000 { 29 reg = <0x8f000000 0x700000>; 30 no-map; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 compatible = "qcom,krait"; 40 enable-method = "qcom,kpss-acc-v1"; 41 device_type = "cpu"; 42 reg = <0>; 43 next-level-cache = <&L2>; 44 qcom,acc = <&acc0>; 45 qcom,saw = <&saw0>; 46 cpu-idle-states = <&CPU_SPC>; 47 }; 48 49 CPU1: cpu@1 { 50 compatible = "qcom,krait"; 51 enable-method = "qcom,kpss-acc-v1"; 52 device_type = "cpu"; 53 reg = <1>; 54 next-level-cache = <&L2>; 55 qcom,acc = <&acc1>; 56 qcom,saw = <&saw1>; 57 cpu-idle-states = <&CPU_SPC>; 58 }; 59 60 CPU2: cpu@2 { 61 compatible = "qcom,krait"; 62 enable-method = "qcom,kpss-acc-v1"; 63 device_type = "cpu"; 64 reg = <2>; 65 next-level-cache = <&L2>; 66 qcom,acc = <&acc2>; 67 qcom,saw = <&saw2>; 68 cpu-idle-states = <&CPU_SPC>; 69 }; 70 71 CPU3: cpu@3 { 72 compatible = "qcom,krait"; 73 enable-method = "qcom,kpss-acc-v1"; 74 device_type = "cpu"; 75 reg = <3>; 76 next-level-cache = <&L2>; 77 qcom,acc = <&acc3>; 78 qcom,saw = <&saw3>; 79 cpu-idle-states = <&CPU_SPC>; 80 }; 81 82 L2: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 }; 86 87 idle-states { 88 CPU_SPC: spc { 89 compatible = "qcom,idle-state-spc", 90 "arm,idle-state"; 91 entry-latency-us = <400>; 92 exit-latency-us = <900>; 93 min-residency-us = <3000>; 94 }; 95 }; 96 }; 97 98 memory { 99 device_type = "memory"; 100 reg = <0x0 0x0>; 101 }; 102 103 thermal-zones { 104 cpu-thermal0 { 105 polling-delay-passive = <250>; 106 polling-delay = <1000>; 107 108 thermal-sensors = <&gcc 7>; 109 coefficients = <1199 0>; 110 111 trips { 112 cpu_alert0: trip0 { 113 temperature = <75000>; 114 hysteresis = <2000>; 115 type = "passive"; 116 }; 117 cpu_crit0: trip1 { 118 temperature = <110000>; 119 hysteresis = <2000>; 120 type = "critical"; 121 }; 122 }; 123 }; 124 125 cpu-thermal1 { 126 polling-delay-passive = <250>; 127 polling-delay = <1000>; 128 129 thermal-sensors = <&gcc 8>; 130 coefficients = <1132 0>; 131 132 trips { 133 cpu_alert1: trip0 { 134 temperature = <75000>; 135 hysteresis = <2000>; 136 type = "passive"; 137 }; 138 cpu_crit1: trip1 { 139 temperature = <110000>; 140 hysteresis = <2000>; 141 type = "critical"; 142 }; 143 }; 144 }; 145 146 cpu-thermal2 { 147 polling-delay-passive = <250>; 148 polling-delay = <1000>; 149 150 thermal-sensors = <&gcc 9>; 151 coefficients = <1199 0>; 152 153 trips { 154 cpu_alert2: trip0 { 155 temperature = <75000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 cpu_crit2: trip1 { 160 temperature = <110000>; 161 hysteresis = <2000>; 162 type = "critical"; 163 }; 164 }; 165 }; 166 167 cpu-thermal3 { 168 polling-delay-passive = <250>; 169 polling-delay = <1000>; 170 171 thermal-sensors = <&gcc 10>; 172 coefficients = <1132 0>; 173 174 trips { 175 cpu_alert3: trip0 { 176 temperature = <75000>; 177 hysteresis = <2000>; 178 type = "passive"; 179 }; 180 cpu_crit3: trip1 { 181 temperature = <110000>; 182 hysteresis = <2000>; 183 type = "critical"; 184 }; 185 }; 186 }; 187 }; 188 189 cpu-pmu { 190 compatible = "qcom,krait-pmu"; 191 interrupts = <1 10 0x304>; 192 }; 193 194 clocks { 195 cxo_board: cxo_board { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <19200000>; 199 }; 200 201 pxo_board: pxo_board { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <27000000>; 205 }; 206 207 sleep_clk: sleep_clk { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <32768>; 211 }; 212 }; 213 214 sfpb_mutex: hwmutex { 215 compatible = "qcom,sfpb-mutex"; 216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 217 #hwlock-cells = <1>; 218 }; 219 220 smem { 221 compatible = "qcom,smem"; 222 memory-region = <&smem_region>; 223 224 hwlocks = <&sfpb_mutex 3>; 225 }; 226 227 smd { 228 compatible = "qcom,smd"; 229 230 modem@0 { 231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; 232 233 qcom,ipc = <&l2cc 8 3>; 234 qcom,smd-edge = <0>; 235 236 status = "disabled"; 237 }; 238 239 q6@1 { 240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; 241 242 qcom,ipc = <&l2cc 8 15>; 243 qcom,smd-edge = <1>; 244 245 status = "disabled"; 246 }; 247 248 dsps@3 { 249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; 250 251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>; 252 qcom,smd-edge = <3>; 253 254 status = "disabled"; 255 }; 256 257 riva@6 { 258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; 259 260 qcom,ipc = <&l2cc 8 25>; 261 qcom,smd-edge = <6>; 262 263 status = "disabled"; 264 }; 265 }; 266 267 smsm { 268 compatible = "qcom,smsm"; 269 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 qcom,ipc-1 = <&l2cc 8 4>; 274 qcom,ipc-2 = <&l2cc 8 14>; 275 qcom,ipc-3 = <&l2cc 8 23>; 276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 277 278 apps_smsm: apps@0 { 279 reg = <0>; 280 #qcom,smem-state-cells = <1>; 281 }; 282 283 modem_smsm: modem@1 { 284 reg = <1>; 285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 286 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 }; 290 291 q6_smsm: q6@2 { 292 reg = <2>; 293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 294 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 299 wcnss_smsm: wcnss@3 { 300 reg = <3>; 301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 302 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 307 dsps_smsm: dsps@4 { 308 reg = <4>; 309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 310 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 }; 314 }; 315 316 firmware { 317 scm { 318 compatible = "qcom,scm-apq8064"; 319 320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 321 clock-names = "core"; 322 }; 323 }; 324 325 326 /* 327 * These channels from the ADC are simply hardware monitors. 328 * That is why the ADC is referred to as "HKADC" - HouseKeeping 329 * ADC. 330 */ 331 iio-hwmon { 332 compatible = "iio-hwmon"; 333 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 334 <&xoadc 0x00 0x02>, /* DC in (charger) */ 335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 336 <&xoadc 0x00 0x0b>, /* Die temperature */ 337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 339 <&xoadc 0x00 0x0e>; /* Charger temperature */ 340 }; 341 342 soc: soc { 343 #address-cells = <1>; 344 #size-cells = <1>; 345 ranges; 346 compatible = "simple-bus"; 347 348 tlmm_pinmux: pinctrl@800000 { 349 compatible = "qcom,apq8064-pinctrl"; 350 reg = <0x800000 0x4000>; 351 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 357 358 pinctrl-names = "default"; 359 pinctrl-0 = <&ps_hold>; 360 }; 361 362 sfpb_wrapper_mutex: syscon@1200000 { 363 compatible = "syscon"; 364 reg = <0x01200000 0x8000>; 365 }; 366 367 intc: interrupt-controller@2000000 { 368 compatible = "qcom,msm-qgic2"; 369 interrupt-controller; 370 #interrupt-cells = <3>; 371 reg = <0x02000000 0x1000>, 372 <0x02002000 0x1000>; 373 }; 374 375 timer@200a000 { 376 compatible = "qcom,kpss-timer", 377 "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; 378 interrupts = <1 1 0x301>, 379 <1 2 0x301>, 380 <1 3 0x301>; 381 reg = <0x0200a000 0x100>; 382 clock-frequency = <27000000>, 383 <32768>; 384 cpu-offset = <0x80000>; 385 }; 386 387 acc0: clock-controller@2088000 { 388 compatible = "qcom,kpss-acc-v1"; 389 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 390 }; 391 392 acc1: clock-controller@2098000 { 393 compatible = "qcom,kpss-acc-v1"; 394 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 395 }; 396 397 acc2: clock-controller@20a8000 { 398 compatible = "qcom,kpss-acc-v1"; 399 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 400 }; 401 402 acc3: clock-controller@20b8000 { 403 compatible = "qcom,kpss-acc-v1"; 404 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 405 }; 406 407 saw0: power-controller@2089000 { 408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 409 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 410 regulator; 411 }; 412 413 saw1: power-controller@2099000 { 414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 415 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 416 regulator; 417 }; 418 419 saw2: power-controller@20a9000 { 420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 422 regulator; 423 }; 424 425 saw3: power-controller@20b9000 { 426 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 427 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 428 regulator; 429 }; 430 431 sps_sic_non_secure: sps-sic-non-secure@12100000 { 432 compatible = "syscon"; 433 reg = <0x12100000 0x10000>; 434 }; 435 436 gsbi1: gsbi@12440000 { 437 status = "disabled"; 438 compatible = "qcom,gsbi-v1.0.0"; 439 cell-index = <1>; 440 reg = <0x12440000 0x100>; 441 clocks = <&gcc GSBI1_H_CLK>; 442 clock-names = "iface"; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 ranges; 446 447 syscon-tcsr = <&tcsr>; 448 449 gsbi1_serial: serial@12450000 { 450 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 451 reg = <0x12450000 0x100>, 452 <0x12400000 0x03>; 453 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 455 clock-names = "core", "iface"; 456 status = "disabled"; 457 }; 458 459 gsbi1_i2c: i2c@12460000 { 460 compatible = "qcom,i2c-qup-v1.1.1"; 461 pinctrl-0 = <&i2c1_pins>; 462 pinctrl-1 = <&i2c1_pins_sleep>; 463 pinctrl-names = "default", "sleep"; 464 reg = <0x12460000 0x1000>; 465 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 467 clock-names = "core", "iface"; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 }; 474 475 gsbi2: gsbi@12480000 { 476 status = "disabled"; 477 compatible = "qcom,gsbi-v1.0.0"; 478 cell-index = <2>; 479 reg = <0x12480000 0x100>; 480 clocks = <&gcc GSBI2_H_CLK>; 481 clock-names = "iface"; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 ranges; 485 486 syscon-tcsr = <&tcsr>; 487 488 gsbi2_i2c: i2c@124a0000 { 489 compatible = "qcom,i2c-qup-v1.1.1"; 490 reg = <0x124a0000 0x1000>; 491 pinctrl-0 = <&i2c2_pins>; 492 pinctrl-1 = <&i2c2_pins_sleep>; 493 pinctrl-names = "default", "sleep"; 494 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 496 clock-names = "core", "iface"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 }; 502 503 gsbi3: gsbi@16200000 { 504 status = "disabled"; 505 compatible = "qcom,gsbi-v1.0.0"; 506 cell-index = <3>; 507 reg = <0x16200000 0x100>; 508 clocks = <&gcc GSBI3_H_CLK>; 509 clock-names = "iface"; 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges; 513 gsbi3_i2c: i2c@16280000 { 514 compatible = "qcom,i2c-qup-v1.1.1"; 515 pinctrl-0 = <&i2c3_pins>; 516 pinctrl-1 = <&i2c3_pins_sleep>; 517 pinctrl-names = "default", "sleep"; 518 reg = <0x16280000 0x1000>; 519 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&gcc GSBI3_QUP_CLK>, 521 <&gcc GSBI3_H_CLK>; 522 clock-names = "core", "iface"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 }; 527 }; 528 529 gsbi4: gsbi@16300000 { 530 status = "disabled"; 531 compatible = "qcom,gsbi-v1.0.0"; 532 cell-index = <4>; 533 reg = <0x16300000 0x03>; 534 clocks = <&gcc GSBI4_H_CLK>; 535 clock-names = "iface"; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 ranges; 539 540 gsbi4_i2c: i2c@16380000 { 541 compatible = "qcom,i2c-qup-v1.1.1"; 542 pinctrl-0 = <&i2c4_pins>; 543 pinctrl-1 = <&i2c4_pins_sleep>; 544 pinctrl-names = "default", "sleep"; 545 reg = <0x16380000 0x1000>; 546 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&gcc GSBI4_QUP_CLK>, 548 <&gcc GSBI4_H_CLK>; 549 clock-names = "core", "iface"; 550 status = "disabled"; 551 }; 552 }; 553 554 gsbi5: gsbi@1a200000 { 555 status = "disabled"; 556 compatible = "qcom,gsbi-v1.0.0"; 557 cell-index = <5>; 558 reg = <0x1a200000 0x03>; 559 clocks = <&gcc GSBI5_H_CLK>; 560 clock-names = "iface"; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 ranges; 564 565 gsbi5_serial: serial@1a240000 { 566 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 567 reg = <0x1a240000 0x100>, 568 <0x1a200000 0x03>; 569 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 571 clock-names = "core", "iface"; 572 status = "disabled"; 573 }; 574 575 gsbi5_spi: spi@1a280000 { 576 compatible = "qcom,spi-qup-v1.1.1"; 577 reg = <0x1a280000 0x1000>; 578 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 579 pinctrl-0 = <&spi5_default>; 580 pinctrl-1 = <&spi5_sleep>; 581 pinctrl-names = "default", "sleep"; 582 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 583 clock-names = "core", "iface"; 584 status = "disabled"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 }; 588 }; 589 590 gsbi6: gsbi@16500000 { 591 status = "disabled"; 592 compatible = "qcom,gsbi-v1.0.0"; 593 cell-index = <6>; 594 reg = <0x16500000 0x03>; 595 clocks = <&gcc GSBI6_H_CLK>; 596 clock-names = "iface"; 597 #address-cells = <1>; 598 #size-cells = <1>; 599 ranges; 600 601 gsbi6_serial: serial@16540000 { 602 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 603 reg = <0x16540000 0x100>, 604 <0x16500000 0x03>; 605 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 607 clock-names = "core", "iface"; 608 status = "disabled"; 609 }; 610 611 gsbi6_i2c: i2c@16580000 { 612 compatible = "qcom,i2c-qup-v1.1.1"; 613 pinctrl-0 = <&i2c6_pins>; 614 pinctrl-1 = <&i2c6_pins_sleep>; 615 pinctrl-names = "default", "sleep"; 616 reg = <0x16580000 0x1000>; 617 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&gcc GSBI6_QUP_CLK>, 619 <&gcc GSBI6_H_CLK>; 620 clock-names = "core", "iface"; 621 status = "disabled"; 622 }; 623 }; 624 625 gsbi7: gsbi@16600000 { 626 status = "disabled"; 627 compatible = "qcom,gsbi-v1.0.0"; 628 cell-index = <7>; 629 reg = <0x16600000 0x100>; 630 clocks = <&gcc GSBI7_H_CLK>; 631 clock-names = "iface"; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges; 635 syscon-tcsr = <&tcsr>; 636 637 gsbi7_serial: serial@16640000 { 638 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 639 reg = <0x16640000 0x1000>, 640 <0x16600000 0x1000>; 641 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 643 clock-names = "core", "iface"; 644 status = "disabled"; 645 }; 646 647 gsbi7_i2c: i2c@16680000 { 648 compatible = "qcom,i2c-qup-v1.1.1"; 649 pinctrl-0 = <&i2c7_pins>; 650 pinctrl-1 = <&i2c7_pins_sleep>; 651 pinctrl-names = "default", "sleep"; 652 reg = <0x16680000 0x1000>; 653 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&gcc GSBI7_QUP_CLK>, 655 <&gcc GSBI7_H_CLK>; 656 clock-names = "core", "iface"; 657 status = "disabled"; 658 }; 659 }; 660 661 rng@1a500000 { 662 compatible = "qcom,prng"; 663 reg = <0x1a500000 0x200>; 664 clocks = <&gcc PRNG_CLK>; 665 clock-names = "core"; 666 }; 667 668 ssbi@c00000 { 669 compatible = "qcom,ssbi"; 670 reg = <0x00c00000 0x1000>; 671 qcom,controller-type = "pmic-arbiter"; 672 673 pm8821: pmic@1 { 674 compatible = "qcom,pm8821"; 675 interrupt-parent = <&tlmm_pinmux>; 676 interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 677 #interrupt-cells = <2>; 678 interrupt-controller; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 682 pm8821_mpps: mpps@50 { 683 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; 684 reg = <0x50>; 685 interrupts = <24 IRQ_TYPE_NONE>, 686 <25 IRQ_TYPE_NONE>, 687 <26 IRQ_TYPE_NONE>, 688 <27 IRQ_TYPE_NONE>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 }; 692 }; 693 }; 694 695 qcom,ssbi@500000 { 696 compatible = "qcom,ssbi"; 697 reg = <0x00500000 0x1000>; 698 qcom,controller-type = "pmic-arbiter"; 699 700 pmicintc: pmic@0 { 701 compatible = "qcom,pm8921"; 702 interrupt-parent = <&tlmm_pinmux>; 703 interrupts = <74 8>; 704 #interrupt-cells = <2>; 705 interrupt-controller; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 pm8921_gpio: gpio@150 { 710 711 compatible = "qcom,pm8921-gpio", 712 "qcom,ssbi-gpio"; 713 reg = <0x150>; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 gpio-controller; 717 gpio-ranges = <&pm8921_gpio 0 0 44>; 718 #gpio-cells = <2>; 719 720 }; 721 722 pm8921_mpps: mpps@50 { 723 compatible = "qcom,pm8921-mpp", 724 "qcom,ssbi-mpp"; 725 reg = <0x50>; 726 gpio-controller; 727 #gpio-cells = <2>; 728 interrupts = 729 <128 IRQ_TYPE_NONE>, 730 <129 IRQ_TYPE_NONE>, 731 <130 IRQ_TYPE_NONE>, 732 <131 IRQ_TYPE_NONE>, 733 <132 IRQ_TYPE_NONE>, 734 <133 IRQ_TYPE_NONE>, 735 <134 IRQ_TYPE_NONE>, 736 <135 IRQ_TYPE_NONE>, 737 <136 IRQ_TYPE_NONE>, 738 <137 IRQ_TYPE_NONE>, 739 <138 IRQ_TYPE_NONE>, 740 <139 IRQ_TYPE_NONE>; 741 }; 742 743 rtc@11d { 744 compatible = "qcom,pm8921-rtc"; 745 interrupt-parent = <&pmicintc>; 746 interrupts = <39 1>; 747 reg = <0x11d>; 748 allow-set-time; 749 }; 750 751 pwrkey@1c { 752 compatible = "qcom,pm8921-pwrkey"; 753 reg = <0x1c>; 754 interrupt-parent = <&pmicintc>; 755 interrupts = <50 1>, <51 1>; 756 debounce = <15625>; 757 pull-up; 758 }; 759 760 xoadc: xoadc@197 { 761 compatible = "qcom,pm8921-adc"; 762 reg = <0x197>; 763 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; 764 #address-cells = <2>; 765 #size-cells = <0>; 766 #io-channel-cells = <2>; 767 768 vcoin: adc-channel@00 { 769 reg = <0x00 0x00>; 770 }; 771 vbat: adc-channel@01 { 772 reg = <0x00 0x01>; 773 }; 774 dcin: adc-channel@02 { 775 reg = <0x00 0x02>; 776 }; 777 vph_pwr: adc-channel@04 { 778 reg = <0x00 0x04>; 779 }; 780 batt_therm: adc-channel@08 { 781 reg = <0x00 0x08>; 782 }; 783 batt_id: adc-channel@09 { 784 reg = <0x00 0x09>; 785 }; 786 usb_vbus: adc-channel@0a { 787 reg = <0x00 0x0a>; 788 }; 789 die_temp: adc-channel@0b { 790 reg = <0x00 0x0b>; 791 }; 792 ref_625mv: adc-channel@0c { 793 reg = <0x00 0x0c>; 794 }; 795 ref_1250mv: adc-channel@0d { 796 reg = <0x00 0x0d>; 797 }; 798 chg_temp: adc-channel@0e { 799 reg = <0x00 0x0e>; 800 }; 801 ref_muxoff: adc-channel@0f { 802 reg = <0x00 0x0f>; 803 }; 804 }; 805 }; 806 }; 807 808 qfprom: qfprom@700000 { 809 compatible = "qcom,qfprom"; 810 reg = <0x00700000 0x1000>; 811 #address-cells = <1>; 812 #size-cells = <1>; 813 ranges; 814 tsens_calib: calib { 815 reg = <0x404 0x10>; 816 }; 817 tsens_backup: backup_calib { 818 reg = <0x414 0x10>; 819 }; 820 }; 821 822 gcc: clock-controller@900000 { 823 compatible = "qcom,gcc-apq8064"; 824 reg = <0x00900000 0x4000>; 825 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 826 nvmem-cell-names = "calib", "calib_backup"; 827 #clock-cells = <1>; 828 #reset-cells = <1>; 829 #thermal-sensor-cells = <1>; 830 }; 831 832 lcc: clock-controller@28000000 { 833 compatible = "qcom,lcc-apq8064"; 834 reg = <0x28000000 0x1000>; 835 #clock-cells = <1>; 836 #reset-cells = <1>; 837 }; 838 839 mmcc: clock-controller@4000000 { 840 compatible = "qcom,mmcc-apq8064"; 841 reg = <0x4000000 0x1000>; 842 #clock-cells = <1>; 843 #reset-cells = <1>; 844 }; 845 846 l2cc: clock-controller@2011000 { 847 compatible = "syscon"; 848 reg = <0x2011000 0x1000>; 849 }; 850 851 rpm@108000 { 852 compatible = "qcom,rpm-apq8064"; 853 reg = <0x108000 0x1000>; 854 qcom,ipc = <&l2cc 0x8 2>; 855 856 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 857 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 858 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 859 interrupt-names = "ack", "err", "wakeup"; 860 861 rpmcc: clock-controller { 862 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 863 #clock-cells = <1>; 864 }; 865 866 regulators { 867 compatible = "qcom,rpm-pm8921-regulators"; 868 869 pm8921_s1: s1 {}; 870 pm8921_s2: s2 {}; 871 pm8921_s3: s3 {}; 872 pm8921_s4: s4 {}; 873 pm8921_s7: s7 {}; 874 pm8921_s8: s8 {}; 875 876 pm8921_l1: l1 {}; 877 pm8921_l2: l2 {}; 878 pm8921_l3: l3 {}; 879 pm8921_l4: l4 {}; 880 pm8921_l5: l5 {}; 881 pm8921_l6: l6 {}; 882 pm8921_l7: l7 {}; 883 pm8921_l8: l8 {}; 884 pm8921_l9: l9 {}; 885 pm8921_l10: l10 {}; 886 pm8921_l11: l11 {}; 887 pm8921_l12: l12 {}; 888 pm8921_l14: l14 {}; 889 pm8921_l15: l15 {}; 890 pm8921_l16: l16 {}; 891 pm8921_l17: l17 {}; 892 pm8921_l18: l18 {}; 893 pm8921_l21: l21 {}; 894 pm8921_l22: l22 {}; 895 pm8921_l23: l23 {}; 896 pm8921_l24: l24 {}; 897 pm8921_l25: l25 {}; 898 pm8921_l26: l26 {}; 899 pm8921_l27: l27 {}; 900 pm8921_l28: l28 {}; 901 pm8921_l29: l29 {}; 902 903 pm8921_lvs1: lvs1 {}; 904 pm8921_lvs2: lvs2 {}; 905 pm8921_lvs3: lvs3 {}; 906 pm8921_lvs4: lvs4 {}; 907 pm8921_lvs5: lvs5 {}; 908 pm8921_lvs6: lvs6 {}; 909 pm8921_lvs7: lvs7 {}; 910 911 pm8921_usb_switch: usb-switch {}; 912 913 pm8921_hdmi_switch: hdmi-switch { 914 bias-pull-down; 915 }; 916 917 pm8921_ncp: ncp {}; 918 }; 919 }; 920 921 usb1: usb@12500000 { 922 compatible = "qcom,ci-hdrc"; 923 reg = <0x12500000 0x200>, 924 <0x12500200 0x200>; 925 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 927 clock-names = "core", "iface"; 928 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 929 assigned-clock-rates = <60000000>; 930 resets = <&gcc USB_HS1_RESET>; 931 reset-names = "core"; 932 phy_type = "ulpi"; 933 ahb-burst-config = <0>; 934 phys = <&usb_hs1_phy>; 935 phy-names = "usb-phy"; 936 status = "disabled"; 937 #reset-cells = <1>; 938 939 ulpi { 940 usb_hs1_phy: phy { 941 compatible = "qcom,usb-hs-phy-apq8064", 942 "qcom,usb-hs-phy"; 943 clocks = <&sleep_clk>, <&cxo_board>; 944 clock-names = "sleep", "ref"; 945 resets = <&usb1 0>; 946 reset-names = "por"; 947 #phy-cells = <0>; 948 }; 949 }; 950 }; 951 952 usb3: usb@12520000 { 953 compatible = "qcom,ci-hdrc"; 954 reg = <0x12520000 0x200>, 955 <0x12520200 0x200>; 956 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 958 clock-names = "core", "iface"; 959 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 960 assigned-clock-rates = <60000000>; 961 resets = <&gcc USB_HS3_RESET>; 962 reset-names = "core"; 963 phy_type = "ulpi"; 964 ahb-burst-config = <0>; 965 phys = <&usb_hs3_phy>; 966 phy-names = "usb-phy"; 967 status = "disabled"; 968 #reset-cells = <1>; 969 970 ulpi { 971 usb_hs3_phy: phy { 972 compatible = "qcom,usb-hs-phy-apq8064", 973 "qcom,usb-hs-phy"; 974 #phy-cells = <0>; 975 clocks = <&sleep_clk>, <&cxo_board>; 976 clock-names = "sleep", "ref"; 977 resets = <&usb3 0>; 978 reset-names = "por"; 979 }; 980 }; 981 }; 982 983 usb4: usb@12530000 { 984 compatible = "qcom,ci-hdrc"; 985 reg = <0x12530000 0x200>, 986 <0x12530200 0x200>; 987 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 989 clock-names = "core", "iface"; 990 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 991 assigned-clock-rates = <60000000>; 992 resets = <&gcc USB_HS4_RESET>; 993 reset-names = "core"; 994 phy_type = "ulpi"; 995 ahb-burst-config = <0>; 996 phys = <&usb_hs4_phy>; 997 phy-names = "usb-phy"; 998 status = "disabled"; 999 #reset-cells = <1>; 1000 1001 ulpi { 1002 usb_hs4_phy: phy { 1003 compatible = "qcom,usb-hs-phy-apq8064", 1004 "qcom,usb-hs-phy"; 1005 #phy-cells = <0>; 1006 clocks = <&sleep_clk>, <&cxo_board>; 1007 clock-names = "sleep", "ref"; 1008 resets = <&usb4 0>; 1009 reset-names = "por"; 1010 }; 1011 }; 1012 }; 1013 1014 sata_phy0: phy@1b400000 { 1015 compatible = "qcom,apq8064-sata-phy"; 1016 status = "disabled"; 1017 reg = <0x1b400000 0x200>; 1018 reg-names = "phy_mem"; 1019 clocks = <&gcc SATA_PHY_CFG_CLK>; 1020 clock-names = "cfg"; 1021 #phy-cells = <0>; 1022 }; 1023 1024 sata0: sata@29000000 { 1025 compatible = "qcom,apq8064-ahci", "generic-ahci"; 1026 status = "disabled"; 1027 reg = <0x29000000 0x180>; 1028 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1029 1030 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1031 <&gcc SATA_H_CLK>, 1032 <&gcc SATA_A_CLK>, 1033 <&gcc SATA_RXOOB_CLK>, 1034 <&gcc SATA_PMALIVE_CLK>; 1035 clock-names = "slave_iface", 1036 "iface", 1037 "bus", 1038 "rxoob", 1039 "core_pmalive"; 1040 1041 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1042 <&gcc SATA_PMALIVE_CLK>; 1043 assigned-clock-rates = <100000000>, <100000000>; 1044 1045 phys = <&sata_phy0>; 1046 phy-names = "sata-phy"; 1047 ports-implemented = <0x1>; 1048 }; 1049 1050 /* Temporary fixed regulator */ 1051 sdcc1bam:dma@12402000{ 1052 compatible = "qcom,bam-v1.3.0"; 1053 reg = <0x12402000 0x8000>; 1054 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&gcc SDC1_H_CLK>; 1056 clock-names = "bam_clk"; 1057 #dma-cells = <1>; 1058 qcom,ee = <0>; 1059 }; 1060 1061 sdcc3bam:dma@12182000{ 1062 compatible = "qcom,bam-v1.3.0"; 1063 reg = <0x12182000 0x8000>; 1064 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&gcc SDC3_H_CLK>; 1066 clock-names = "bam_clk"; 1067 #dma-cells = <1>; 1068 qcom,ee = <0>; 1069 }; 1070 1071 sdcc4bam:dma@121c2000{ 1072 compatible = "qcom,bam-v1.3.0"; 1073 reg = <0x121c2000 0x8000>; 1074 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&gcc SDC4_H_CLK>; 1076 clock-names = "bam_clk"; 1077 #dma-cells = <1>; 1078 qcom,ee = <0>; 1079 }; 1080 1081 amba { 1082 compatible = "simple-bus"; 1083 #address-cells = <1>; 1084 #size-cells = <1>; 1085 ranges; 1086 sdcc1: sdcc@12400000 { 1087 status = "disabled"; 1088 compatible = "arm,pl18x", "arm,primecell"; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&sdcc1_pins>; 1091 arm,primecell-periphid = <0x00051180>; 1092 reg = <0x12400000 0x2000>; 1093 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1094 interrupt-names = "cmd_irq"; 1095 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1096 clock-names = "mclk", "apb_pclk"; 1097 bus-width = <8>; 1098 max-frequency = <96000000>; 1099 non-removable; 1100 cap-sd-highspeed; 1101 cap-mmc-highspeed; 1102 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1103 dma-names = "tx", "rx"; 1104 }; 1105 1106 sdcc3: sdcc@12180000 { 1107 compatible = "arm,pl18x", "arm,primecell"; 1108 arm,primecell-periphid = <0x00051180>; 1109 status = "disabled"; 1110 reg = <0x12180000 0x2000>; 1111 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1112 interrupt-names = "cmd_irq"; 1113 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1114 clock-names = "mclk", "apb_pclk"; 1115 bus-width = <4>; 1116 cap-sd-highspeed; 1117 cap-mmc-highspeed; 1118 max-frequency = <192000000>; 1119 no-1-8-v; 1120 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1121 dma-names = "tx", "rx"; 1122 }; 1123 1124 sdcc4: sdcc@121c0000 { 1125 compatible = "arm,pl18x", "arm,primecell"; 1126 arm,primecell-periphid = <0x00051180>; 1127 status = "disabled"; 1128 reg = <0x121c0000 0x2000>; 1129 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1130 interrupt-names = "cmd_irq"; 1131 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1132 clock-names = "mclk", "apb_pclk"; 1133 bus-width = <4>; 1134 cap-sd-highspeed; 1135 cap-mmc-highspeed; 1136 max-frequency = <48000000>; 1137 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1138 dma-names = "tx", "rx"; 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&sdc4_gpios>; 1141 }; 1142 }; 1143 1144 tcsr: syscon@1a400000 { 1145 compatible = "qcom,tcsr-apq8064", "syscon"; 1146 reg = <0x1a400000 0x100>; 1147 }; 1148 1149 gpu: adreno-3xx@4300000 { 1150 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1151 reg = <0x04300000 0x20000>; 1152 reg-names = "kgsl_3d0_reg_memory"; 1153 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1154 interrupt-names = "kgsl_3d0_irq"; 1155 clock-names = 1156 "core_clk", 1157 "iface_clk", 1158 "mem_clk", 1159 "mem_iface_clk"; 1160 clocks = 1161 <&mmcc GFX3D_CLK>, 1162 <&mmcc GFX3D_AHB_CLK>, 1163 <&mmcc GFX3D_AXI_CLK>, 1164 <&mmcc MMSS_IMEM_AHB_CLK>; 1165 1166 iommus = <&gfx3d 0 1167 &gfx3d 1 1168 &gfx3d 2 1169 &gfx3d 3 1170 &gfx3d 4 1171 &gfx3d 5 1172 &gfx3d 6 1173 &gfx3d 7 1174 &gfx3d 8 1175 &gfx3d 9 1176 &gfx3d 10 1177 &gfx3d 11 1178 &gfx3d 12 1179 &gfx3d 13 1180 &gfx3d 14 1181 &gfx3d 15 1182 &gfx3d 16 1183 &gfx3d 17 1184 &gfx3d 18 1185 &gfx3d 19 1186 &gfx3d 20 1187 &gfx3d 21 1188 &gfx3d 22 1189 &gfx3d 23 1190 &gfx3d 24 1191 &gfx3d 25 1192 &gfx3d 26 1193 &gfx3d 27 1194 &gfx3d 28 1195 &gfx3d 29 1196 &gfx3d 30 1197 &gfx3d 31 1198 &gfx3d1 0 1199 &gfx3d1 1 1200 &gfx3d1 2 1201 &gfx3d1 3 1202 &gfx3d1 4 1203 &gfx3d1 5 1204 &gfx3d1 6 1205 &gfx3d1 7 1206 &gfx3d1 8 1207 &gfx3d1 9 1208 &gfx3d1 10 1209 &gfx3d1 11 1210 &gfx3d1 12 1211 &gfx3d1 13 1212 &gfx3d1 14 1213 &gfx3d1 15 1214 &gfx3d1 16 1215 &gfx3d1 17 1216 &gfx3d1 18 1217 &gfx3d1 19 1218 &gfx3d1 20 1219 &gfx3d1 21 1220 &gfx3d1 22 1221 &gfx3d1 23 1222 &gfx3d1 24 1223 &gfx3d1 25 1224 &gfx3d1 26 1225 &gfx3d1 27 1226 &gfx3d1 28 1227 &gfx3d1 29 1228 &gfx3d1 30 1229 &gfx3d1 31>; 1230 1231 qcom,gpu-pwrlevels { 1232 compatible = "qcom,gpu-pwrlevels"; 1233 qcom,gpu-pwrlevel@0 { 1234 qcom,gpu-freq = <450000000>; 1235 }; 1236 qcom,gpu-pwrlevel@1 { 1237 qcom,gpu-freq = <27000000>; 1238 }; 1239 }; 1240 }; 1241 1242 mmss_sfpb: syscon@5700000 { 1243 compatible = "syscon"; 1244 reg = <0x5700000 0x70>; 1245 }; 1246 1247 dsi0: mdss_dsi@4700000 { 1248 compatible = "qcom,mdss-dsi-ctrl"; 1249 label = "MDSS DSI CTRL->0"; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1253 reg = <0x04700000 0x200>; 1254 reg-names = "dsi_ctrl"; 1255 1256 clocks = <&mmcc DSI_M_AHB_CLK>, 1257 <&mmcc DSI_S_AHB_CLK>, 1258 <&mmcc AMP_AHB_CLK>, 1259 <&mmcc DSI_CLK>, 1260 <&mmcc DSI1_BYTE_CLK>, 1261 <&mmcc DSI_PIXEL_CLK>, 1262 <&mmcc DSI1_ESC_CLK>; 1263 clock-names = "iface", "bus", "core_mmss", 1264 "src", "byte", "pixel", 1265 "core"; 1266 1267 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1268 <&mmcc DSI1_ESC_SRC>, 1269 <&mmcc DSI_SRC>, 1270 <&mmcc DSI_PIXEL_SRC>; 1271 assigned-clock-parents = <&dsi0_phy 0>, 1272 <&dsi0_phy 0>, 1273 <&dsi0_phy 1>, 1274 <&dsi0_phy 1>; 1275 syscon-sfpb = <&mmss_sfpb>; 1276 phys = <&dsi0_phy>; 1277 ports { 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 1281 port@0 { 1282 reg = <0>; 1283 dsi0_in: endpoint { 1284 }; 1285 }; 1286 1287 port@1 { 1288 reg = <1>; 1289 dsi0_out: endpoint { 1290 }; 1291 }; 1292 }; 1293 }; 1294 1295 1296 dsi0_phy: dsi-phy@4700200 { 1297 compatible = "qcom,dsi-phy-28nm-8960"; 1298 #clock-cells = <1>; 1299 #phy-cells = <0>; 1300 1301 reg = <0x04700200 0x100>, 1302 <0x04700300 0x200>, 1303 <0x04700500 0x5c>; 1304 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1305 clock-names = "iface_clk", "ref"; 1306 clocks = <&mmcc DSI_M_AHB_CLK>, 1307 <&pxo_board>; 1308 }; 1309 1310 1311 mdp_port0: iommu@7500000 { 1312 compatible = "qcom,apq8064-iommu"; 1313 #iommu-cells = <1>; 1314 clock-names = 1315 "smmu_pclk", 1316 "iommu_clk"; 1317 clocks = 1318 <&mmcc SMMU_AHB_CLK>, 1319 <&mmcc MDP_AXI_CLK>; 1320 reg = <0x07500000 0x100000>; 1321 interrupts = 1322 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1324 qcom,ncb = <2>; 1325 }; 1326 1327 mdp_port1: iommu@7600000 { 1328 compatible = "qcom,apq8064-iommu"; 1329 #iommu-cells = <1>; 1330 clock-names = 1331 "smmu_pclk", 1332 "iommu_clk"; 1333 clocks = 1334 <&mmcc SMMU_AHB_CLK>, 1335 <&mmcc MDP_AXI_CLK>; 1336 reg = <0x07600000 0x100000>; 1337 interrupts = 1338 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1340 qcom,ncb = <2>; 1341 }; 1342 1343 gfx3d: iommu@7c00000 { 1344 compatible = "qcom,apq8064-iommu"; 1345 #iommu-cells = <1>; 1346 clock-names = 1347 "smmu_pclk", 1348 "iommu_clk"; 1349 clocks = 1350 <&mmcc SMMU_AHB_CLK>, 1351 <&mmcc GFX3D_AXI_CLK>; 1352 reg = <0x07c00000 0x100000>; 1353 interrupts = 1354 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1356 qcom,ncb = <3>; 1357 }; 1358 1359 gfx3d1: iommu@7d00000 { 1360 compatible = "qcom,apq8064-iommu"; 1361 #iommu-cells = <1>; 1362 clock-names = 1363 "smmu_pclk", 1364 "iommu_clk"; 1365 clocks = 1366 <&mmcc SMMU_AHB_CLK>, 1367 <&mmcc GFX3D_AXI_CLK>; 1368 reg = <0x07d00000 0x100000>; 1369 interrupts = 1370 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1372 qcom,ncb = <3>; 1373 }; 1374 1375 pcie: pci@1b500000 { 1376 compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; 1377 reg = <0x1b500000 0x1000 1378 0x1b502000 0x80 1379 0x1b600000 0x100 1380 0x0ff00000 0x100000>; 1381 reg-names = "dbi", "elbi", "parf", "config"; 1382 device_type = "pci"; 1383 linux,pci-domain = <0>; 1384 bus-range = <0x00 0xff>; 1385 num-lanes = <1>; 1386 #address-cells = <3>; 1387 #size-cells = <2>; 1388 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ 1389 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ 1390 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1391 interrupt-names = "msi"; 1392 #interrupt-cells = <1>; 1393 interrupt-map-mask = <0 0 0 0x7>; 1394 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1395 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1396 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1397 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1398 clocks = <&gcc PCIE_A_CLK>, 1399 <&gcc PCIE_H_CLK>, 1400 <&gcc PCIE_PHY_REF_CLK>; 1401 clock-names = "core", "iface", "phy"; 1402 resets = <&gcc PCIE_ACLK_RESET>, 1403 <&gcc PCIE_HCLK_RESET>, 1404 <&gcc PCIE_POR_RESET>, 1405 <&gcc PCIE_PCI_RESET>, 1406 <&gcc PCIE_PHY_RESET>; 1407 reset-names = "axi", "ahb", "por", "pci", "phy"; 1408 status = "disabled"; 1409 }; 1410 1411 hdmi: hdmi-tx@4a00000 { 1412 compatible = "qcom,hdmi-tx-8960"; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&hdmi_pinctrl>; 1415 reg = <0x04a00000 0x2f0>; 1416 reg-names = "core_physical"; 1417 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&mmcc HDMI_APP_CLK>, 1419 <&mmcc HDMI_M_AHB_CLK>, 1420 <&mmcc HDMI_S_AHB_CLK>; 1421 clock-names = "core_clk", 1422 "master_iface_clk", 1423 "slave_iface_clk"; 1424 1425 phys = <&hdmi_phy>; 1426 phy-names = "hdmi-phy"; 1427 1428 ports { 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 1432 port@0 { 1433 reg = <0>; 1434 hdmi_in: endpoint { 1435 }; 1436 }; 1437 1438 port@1 { 1439 reg = <1>; 1440 hdmi_out: endpoint { 1441 }; 1442 }; 1443 }; 1444 }; 1445 1446 hdmi_phy: hdmi-phy@4a00400 { 1447 compatible = "qcom,hdmi-phy-8960"; 1448 reg = <0x4a00400 0x60>, 1449 <0x4a00500 0x100>; 1450 reg-names = "hdmi_phy", 1451 "hdmi_pll"; 1452 1453 clocks = <&mmcc HDMI_S_AHB_CLK>; 1454 clock-names = "slave_iface_clk"; 1455 #phy-cells = <0>; 1456 }; 1457 1458 mdp: mdp@5100000 { 1459 compatible = "qcom,mdp4"; 1460 reg = <0x05100000 0xf0000>; 1461 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&mmcc MDP_CLK>, 1463 <&mmcc MDP_AHB_CLK>, 1464 <&mmcc MDP_AXI_CLK>, 1465 <&mmcc MDP_LUT_CLK>, 1466 <&mmcc HDMI_TV_CLK>, 1467 <&mmcc MDP_TV_CLK>; 1468 clock-names = "core_clk", 1469 "iface_clk", 1470 "bus_clk", 1471 "lut_clk", 1472 "hdmi_clk", 1473 "tv_clk"; 1474 1475 iommus = <&mdp_port0 0 1476 &mdp_port0 2 1477 &mdp_port1 0 1478 &mdp_port1 2>; 1479 1480 ports { 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 1484 port@0 { 1485 reg = <0>; 1486 mdp_lvds_out: endpoint { 1487 }; 1488 }; 1489 1490 port@1 { 1491 reg = <1>; 1492 mdp_dsi1_out: endpoint { 1493 }; 1494 }; 1495 1496 port@2 { 1497 reg = <2>; 1498 mdp_dsi2_out: endpoint { 1499 }; 1500 }; 1501 1502 port@3 { 1503 reg = <3>; 1504 mdp_dtv_out: endpoint { 1505 }; 1506 }; 1507 }; 1508 }; 1509 1510 riva: riva-pil@3204000 { 1511 compatible = "qcom,riva-pil"; 1512 1513 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1514 reg-names = "ccu", "dxe", "pmu"; 1515 1516 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1517 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1518 interrupt-names = "wdog", "fatal"; 1519 1520 memory-region = <&wcnss_mem>; 1521 1522 vddcx-supply = <&pm8921_s3>; 1523 vddmx-supply = <&pm8921_l24>; 1524 vddpx-supply = <&pm8921_s4>; 1525 1526 status = "disabled"; 1527 1528 iris { 1529 compatible = "qcom,wcn3660"; 1530 1531 clocks = <&cxo_board>; 1532 clock-names = "xo"; 1533 1534 vddxo-supply = <&pm8921_l4>; 1535 vddrfa-supply = <&pm8921_s2>; 1536 vddpa-supply = <&pm8921_l10>; 1537 vdddig-supply = <&pm8921_lvs2>; 1538 }; 1539 1540 smd-edge { 1541 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1542 1543 qcom,ipc = <&l2cc 8 25>; 1544 qcom,smd-edge = <6>; 1545 1546 label = "riva"; 1547 1548 wcnss { 1549 compatible = "qcom,wcnss"; 1550 qcom,smd-channels = "WCNSS_CTRL"; 1551 1552 qcom,mmio = <&riva>; 1553 1554 bt { 1555 compatible = "qcom,wcnss-bt"; 1556 }; 1557 1558 wifi { 1559 compatible = "qcom,wcnss-wlan"; 1560 1561 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1563 interrupt-names = "tx", "rx"; 1564 1565 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1566 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1567 }; 1568 }; 1569 }; 1570 }; 1571 1572 etb@1a01000 { 1573 compatible = "arm,coresight-etb10", "arm,primecell"; 1574 reg = <0x1a01000 0x1000>; 1575 1576 clocks = <&rpmcc RPM_QDSS_CLK>; 1577 clock-names = "apb_pclk"; 1578 1579 in-ports { 1580 port { 1581 etb_in: endpoint { 1582 remote-endpoint = <&replicator_out0>; 1583 }; 1584 }; 1585 }; 1586 }; 1587 1588 tpiu@1a03000 { 1589 compatible = "arm,coresight-tpiu", "arm,primecell"; 1590 reg = <0x1a03000 0x1000>; 1591 1592 clocks = <&rpmcc RPM_QDSS_CLK>; 1593 clock-names = "apb_pclk"; 1594 1595 in-ports { 1596 port { 1597 tpiu_in: endpoint { 1598 remote-endpoint = <&replicator_out1>; 1599 }; 1600 }; 1601 }; 1602 }; 1603 1604 replicator { 1605 compatible = "arm,coresight-static-replicator"; 1606 1607 clocks = <&rpmcc RPM_QDSS_CLK>; 1608 clock-names = "apb_pclk"; 1609 1610 out-ports { 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 1614 port@0 { 1615 reg = <0>; 1616 replicator_out0: endpoint { 1617 remote-endpoint = <&etb_in>; 1618 }; 1619 }; 1620 port@1 { 1621 reg = <1>; 1622 replicator_out1: endpoint { 1623 remote-endpoint = <&tpiu_in>; 1624 }; 1625 }; 1626 }; 1627 1628 in-ports { 1629 port { 1630 replicator_in: endpoint { 1631 remote-endpoint = <&funnel_out>; 1632 }; 1633 }; 1634 }; 1635 }; 1636 1637 funnel@1a04000 { 1638 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1639 reg = <0x1a04000 0x1000>; 1640 1641 clocks = <&rpmcc RPM_QDSS_CLK>; 1642 clock-names = "apb_pclk"; 1643 1644 in-ports { 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 1648 /* 1649 * Not described input ports: 1650 * 2 - connected to STM component 1651 * 3 - not-connected 1652 * 6 - not-connected 1653 * 7 - not-connected 1654 */ 1655 port@0 { 1656 reg = <0>; 1657 funnel_in0: endpoint { 1658 remote-endpoint = <&etm0_out>; 1659 }; 1660 }; 1661 port@1 { 1662 reg = <1>; 1663 funnel_in1: endpoint { 1664 remote-endpoint = <&etm1_out>; 1665 }; 1666 }; 1667 port@4 { 1668 reg = <4>; 1669 funnel_in4: endpoint { 1670 remote-endpoint = <&etm2_out>; 1671 }; 1672 }; 1673 port@5 { 1674 reg = <5>; 1675 funnel_in5: endpoint { 1676 remote-endpoint = <&etm3_out>; 1677 }; 1678 }; 1679 }; 1680 1681 out-ports { 1682 port { 1683 funnel_out: endpoint { 1684 remote-endpoint = <&replicator_in>; 1685 }; 1686 }; 1687 }; 1688 }; 1689 1690 etm@1a1c000 { 1691 compatible = "arm,coresight-etm3x", "arm,primecell"; 1692 reg = <0x1a1c000 0x1000>; 1693 1694 clocks = <&rpmcc RPM_QDSS_CLK>; 1695 clock-names = "apb_pclk"; 1696 1697 cpu = <&CPU0>; 1698 1699 out-ports { 1700 port { 1701 etm0_out: endpoint { 1702 remote-endpoint = <&funnel_in0>; 1703 }; 1704 }; 1705 }; 1706 }; 1707 1708 etm@1a1d000 { 1709 compatible = "arm,coresight-etm3x", "arm,primecell"; 1710 reg = <0x1a1d000 0x1000>; 1711 1712 clocks = <&rpmcc RPM_QDSS_CLK>; 1713 clock-names = "apb_pclk"; 1714 1715 cpu = <&CPU1>; 1716 1717 out-ports { 1718 port { 1719 etm1_out: endpoint { 1720 remote-endpoint = <&funnel_in1>; 1721 }; 1722 }; 1723 }; 1724 }; 1725 1726 etm@1a1e000 { 1727 compatible = "arm,coresight-etm3x", "arm,primecell"; 1728 reg = <0x1a1e000 0x1000>; 1729 1730 clocks = <&rpmcc RPM_QDSS_CLK>; 1731 clock-names = "apb_pclk"; 1732 1733 cpu = <&CPU2>; 1734 1735 out-ports { 1736 port { 1737 etm2_out: endpoint { 1738 remote-endpoint = <&funnel_in4>; 1739 }; 1740 }; 1741 }; 1742 }; 1743 1744 etm@1a1f000 { 1745 compatible = "arm,coresight-etm3x", "arm,primecell"; 1746 reg = <0x1a1f000 0x1000>; 1747 1748 clocks = <&rpmcc RPM_QDSS_CLK>; 1749 clock-names = "apb_pclk"; 1750 1751 cpu = <&CPU3>; 1752 1753 out-ports { 1754 port { 1755 etm3_out: endpoint { 1756 remote-endpoint = <&funnel_in5>; 1757 }; 1758 }; 1759 }; 1760 }; 1761 }; 1762}; 1763#include "qcom-apq8064-pins.dtsi" 1764