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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Simon Horman
7 */
8
9#include <dt-bindings/clock/r8a7779-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/power/r8a7779-sysc.h>
13
14/ {
15	compatible = "renesas,r8a7779";
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu@0 {
25			device_type = "cpu";
26			compatible = "arm,cortex-a9";
27			reg = <0>;
28			clock-frequency = <1000000000>;
29			clocks = <&cpg_clocks R8A7779_CLK_Z>;
30		};
31		cpu@1 {
32			device_type = "cpu";
33			compatible = "arm,cortex-a9";
34			reg = <1>;
35			clock-frequency = <1000000000>;
36			clocks = <&cpg_clocks R8A7779_CLK_Z>;
37			power-domains = <&sysc R8A7779_PD_ARM1>;
38		};
39		cpu@2 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a9";
42			reg = <2>;
43			clock-frequency = <1000000000>;
44			clocks = <&cpg_clocks R8A7779_CLK_Z>;
45			power-domains = <&sysc R8A7779_PD_ARM2>;
46		};
47		cpu@3 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a9";
50			reg = <3>;
51			clock-frequency = <1000000000>;
52			clocks = <&cpg_clocks R8A7779_CLK_Z>;
53			power-domains = <&sysc R8A7779_PD_ARM3>;
54		};
55	};
56
57	aliases {
58		spi0 = &hspi0;
59		spi1 = &hspi1;
60		spi2 = &hspi2;
61	};
62
63	gic: interrupt-controller@f0001000 {
64		compatible = "arm,cortex-a9-gic";
65		#interrupt-cells = <3>;
66		interrupt-controller;
67		reg = <0xf0001000 0x1000>,
68		      <0xf0000100 0x100>;
69	};
70
71	timer@f0000200 {
72		compatible = "arm,cortex-a9-global-timer";
73		reg = <0xf0000200 0x100>;
74		interrupts = <GIC_PPI 11
75			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
76		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
77	};
78
79	timer@f0000600 {
80		compatible = "arm,cortex-a9-twd-timer";
81		reg = <0xf0000600 0x20>;
82		interrupts = <GIC_PPI 13
83			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
84		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
85	};
86
87	gpio0: gpio@ffc40000 {
88		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
89		reg = <0xffc40000 0x2c>;
90		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
91		#gpio-cells = <2>;
92		gpio-controller;
93		gpio-ranges = <&pfc 0 0 32>;
94		#interrupt-cells = <2>;
95		interrupt-controller;
96	};
97
98	gpio1: gpio@ffc41000 {
99		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
100		reg = <0xffc41000 0x2c>;
101		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
102		#gpio-cells = <2>;
103		gpio-controller;
104		gpio-ranges = <&pfc 0 32 32>;
105		#interrupt-cells = <2>;
106		interrupt-controller;
107	};
108
109	gpio2: gpio@ffc42000 {
110		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
111		reg = <0xffc42000 0x2c>;
112		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
113		#gpio-cells = <2>;
114		gpio-controller;
115		gpio-ranges = <&pfc 0 64 32>;
116		#interrupt-cells = <2>;
117		interrupt-controller;
118	};
119
120	gpio3: gpio@ffc43000 {
121		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
122		reg = <0xffc43000 0x2c>;
123		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
124		#gpio-cells = <2>;
125		gpio-controller;
126		gpio-ranges = <&pfc 0 96 32>;
127		#interrupt-cells = <2>;
128		interrupt-controller;
129	};
130
131	gpio4: gpio@ffc44000 {
132		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
133		reg = <0xffc44000 0x2c>;
134		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
135		#gpio-cells = <2>;
136		gpio-controller;
137		gpio-ranges = <&pfc 0 128 32>;
138		#interrupt-cells = <2>;
139		interrupt-controller;
140	};
141
142	gpio5: gpio@ffc45000 {
143		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
144		reg = <0xffc45000 0x2c>;
145		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
146		#gpio-cells = <2>;
147		gpio-controller;
148		gpio-ranges = <&pfc 0 160 32>;
149		#interrupt-cells = <2>;
150		interrupt-controller;
151	};
152
153	gpio6: gpio@ffc46000 {
154		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
155		reg = <0xffc46000 0x2c>;
156		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
157		#gpio-cells = <2>;
158		gpio-controller;
159		gpio-ranges = <&pfc 0 192 9>;
160		#interrupt-cells = <2>;
161		interrupt-controller;
162	};
163
164	irqpin0: interrupt-controller@fe78001c {
165		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
166		#interrupt-cells = <2>;
167		status = "disabled";
168		interrupt-controller;
169		reg = <0xfe78001c 4>,
170			<0xfe780010 4>,
171			<0xfe780024 4>,
172			<0xfe780044 4>,
173			<0xfe780064 4>,
174			<0xfe780000 4>;
175		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
176			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
177			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
178			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
179		sense-bitfield-width = <2>;
180	};
181
182	i2c0: i2c@ffc70000 {
183		#address-cells = <1>;
184		#size-cells = <0>;
185		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
186		reg = <0xffc70000 0x1000>;
187		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
188		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
189		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
190		status = "disabled";
191	};
192
193	i2c1: i2c@ffc71000 {
194		#address-cells = <1>;
195		#size-cells = <0>;
196		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
197		reg = <0xffc71000 0x1000>;
198		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
199		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
200		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
201		status = "disabled";
202	};
203
204	i2c2: i2c@ffc72000 {
205		#address-cells = <1>;
206		#size-cells = <0>;
207		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
208		reg = <0xffc72000 0x1000>;
209		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
210		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
211		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
212		status = "disabled";
213	};
214
215	i2c3: i2c@ffc73000 {
216		#address-cells = <1>;
217		#size-cells = <0>;
218		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
219		reg = <0xffc73000 0x1000>;
220		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
221		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
222		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
223		status = "disabled";
224	};
225
226	scif0: serial@ffe40000 {
227		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
228			     "renesas,scif";
229		reg = <0xffe40000 0x100>;
230		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
231		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
232			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
233		clock-names = "fck", "brg_int", "scif_clk";
234		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
235		status = "disabled";
236	};
237
238	scif1: serial@ffe41000 {
239		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
240			     "renesas,scif";
241		reg = <0xffe41000 0x100>;
242		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
243		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
244			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
245		clock-names = "fck", "brg_int", "scif_clk";
246		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
247		status = "disabled";
248	};
249
250	scif2: serial@ffe42000 {
251		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
252			     "renesas,scif";
253		reg = <0xffe42000 0x100>;
254		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
255		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
256			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
257		clock-names = "fck", "brg_int", "scif_clk";
258		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
259		status = "disabled";
260	};
261
262	scif3: serial@ffe43000 {
263		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
264			     "renesas,scif";
265		reg = <0xffe43000 0x100>;
266		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
267		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
268			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
269		clock-names = "fck", "brg_int", "scif_clk";
270		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
271		status = "disabled";
272	};
273
274	scif4: serial@ffe44000 {
275		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
276			     "renesas,scif";
277		reg = <0xffe44000 0x100>;
278		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
279		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
280			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
281		clock-names = "fck", "brg_int", "scif_clk";
282		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
283		status = "disabled";
284	};
285
286	scif5: serial@ffe45000 {
287		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
288			     "renesas,scif";
289		reg = <0xffe45000 0x100>;
290		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
291		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
292			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
293		clock-names = "fck", "brg_int", "scif_clk";
294		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
295		status = "disabled";
296	};
297
298	hscif0: serial@ffe48000 {
299		compatible = "renesas,hscif-r8a7779",
300			     "renesas,rcar-gen1-hscif", "renesas,hscif";
301		reg = <0xffe48000 96>;
302		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
303		clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
304			 <&cpg_clocks R8A7779_CLK_S>,
305			 <&scif_clk>;
306		clock-names = "fck", "brg_int", "scif_clk";
307		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
308		status = "disabled";
309	};
310
311	hscif1: serial@ffe49000 {
312		compatible = "renesas,hscif-r8a7779",
313			     "renesas,rcar-gen1-hscif", "renesas,hscif";
314		reg = <0xffe49000 96>;
315		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
316		clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
317			 <&cpg_clocks R8A7779_CLK_S>,
318			 <&scif_clk>;
319		clock-names = "fck", "brg_int", "scif_clk";
320		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
321		status = "disabled";
322	};
323
324	pfc: pin-controller@fffc0000 {
325		compatible = "renesas,pfc-r8a7779";
326		reg = <0xfffc0000 0x23c>;
327	};
328
329	thermal@ffc48000 {
330		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
331		reg = <0xffc48000 0x38>;
332	};
333
334	tmu0: timer@ffd80000 {
335		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
336		reg = <0xffd80000 0x30>;
337		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
338			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
339			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
340		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
341		clock-names = "fck";
342		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
343
344		#renesas,channels = <3>;
345
346		status = "disabled";
347	};
348
349	tmu1: timer@ffd81000 {
350		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
351		reg = <0xffd81000 0x30>;
352		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
353			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
354			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
355		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
356		clock-names = "fck";
357		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
358
359		#renesas,channels = <3>;
360
361		status = "disabled";
362	};
363
364	tmu2: timer@ffd82000 {
365		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
366		reg = <0xffd82000 0x30>;
367		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
368			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
369			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
370		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
371		clock-names = "fck";
372		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
373
374		#renesas,channels = <3>;
375
376		status = "disabled";
377	};
378
379	sata: sata@fc600000 {
380		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
381		reg = <0xfc600000 0x200000>;
382		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
383		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
384		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
385		status = "disabled";
386	};
387
388	sdhi0: sd@ffe4c000 {
389		compatible = "renesas,sdhi-r8a7779",
390			     "renesas,rcar-gen1-sdhi";
391		reg = <0xffe4c000 0x100>;
392		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
393		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
394		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
395		status = "disabled";
396	};
397
398	sdhi1: sd@ffe4d000 {
399		compatible = "renesas,sdhi-r8a7779",
400			     "renesas,rcar-gen1-sdhi";
401		reg = <0xffe4d000 0x100>;
402		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
403		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
404		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
405		status = "disabled";
406	};
407
408	sdhi2: sd@ffe4e000 {
409		compatible = "renesas,sdhi-r8a7779",
410			     "renesas,rcar-gen1-sdhi";
411		reg = <0xffe4e000 0x100>;
412		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
413		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
414		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
415		status = "disabled";
416	};
417
418	sdhi3: sd@ffe4f000 {
419		compatible = "renesas,sdhi-r8a7779",
420			     "renesas,rcar-gen1-sdhi";
421		reg = <0xffe4f000 0x100>;
422		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
423		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
424		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
425		status = "disabled";
426	};
427
428	hspi0: spi@fffc7000 {
429		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
430		reg = <0xfffc7000 0x18>;
431		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
432		#address-cells = <1>;
433		#size-cells = <0>;
434		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
435		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
436		status = "disabled";
437	};
438
439	hspi1: spi@fffc8000 {
440		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
441		reg = <0xfffc8000 0x18>;
442		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
443		#address-cells = <1>;
444		#size-cells = <0>;
445		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
446		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
447		status = "disabled";
448	};
449
450	hspi2: spi@fffc6000 {
451		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
452		reg = <0xfffc6000 0x18>;
453		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
454		#address-cells = <1>;
455		#size-cells = <0>;
456		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
457		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
458		status = "disabled";
459	};
460
461	du: display@fff80000 {
462		compatible = "renesas,du-r8a7779";
463		reg = <0xfff80000 0x40000>;
464		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
465		clocks = <&mstp1_clks R8A7779_CLK_DU>;
466		clock-names = "du.0";
467		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
468		status = "disabled";
469
470		ports {
471			#address-cells = <1>;
472			#size-cells = <0>;
473
474			port@0 {
475				reg = <0>;
476				du_out_rgb0: endpoint {
477				};
478			};
479			port@1 {
480				reg = <1>;
481				du_out_rgb1: endpoint {
482				};
483			};
484		};
485	};
486
487	clocks {
488		#address-cells = <1>;
489		#size-cells = <1>;
490		ranges;
491
492		/* External root clock */
493		extal_clk: extal {
494			compatible = "fixed-clock";
495			#clock-cells = <0>;
496			/* This value must be overriden by the board. */
497			clock-frequency = <0>;
498		};
499
500		/* External SCIF clock */
501		scif_clk: scif {
502			compatible = "fixed-clock";
503			#clock-cells = <0>;
504			/* This value must be overridden by the board. */
505			clock-frequency = <0>;
506		};
507
508		/* Special CPG clocks */
509		cpg_clocks: clocks@ffc80000 {
510			compatible = "renesas,r8a7779-cpg-clocks";
511			reg = <0xffc80000 0x30>;
512			clocks = <&extal_clk>;
513			#clock-cells = <1>;
514			clock-output-names = "plla", "z", "zs", "s",
515					     "s1", "p", "b", "out";
516			#power-domain-cells = <0>;
517		};
518
519		/* Fixed factor clocks */
520		i_clk: i {
521			compatible = "fixed-factor-clock";
522			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
523			#clock-cells = <0>;
524			clock-div = <2>;
525			clock-mult = <1>;
526		};
527		s3_clk: s3 {
528			compatible = "fixed-factor-clock";
529			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
530			#clock-cells = <0>;
531			clock-div = <8>;
532			clock-mult = <1>;
533		};
534		s4_clk: s4 {
535			compatible = "fixed-factor-clock";
536			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
537			#clock-cells = <0>;
538			clock-div = <16>;
539			clock-mult = <1>;
540		};
541		g_clk: g {
542			compatible = "fixed-factor-clock";
543			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
544			#clock-cells = <0>;
545			clock-div = <24>;
546			clock-mult = <1>;
547		};
548
549		/* Gate clocks */
550		mstp0_clks: clocks@ffc80030 {
551			compatible = "renesas,r8a7779-mstp-clocks",
552				     "renesas,cpg-mstp-clocks";
553			reg = <0xffc80030 4>;
554			clocks = <&cpg_clocks R8A7779_CLK_S>,
555				 <&cpg_clocks R8A7779_CLK_P>,
556				 <&cpg_clocks R8A7779_CLK_P>,
557				 <&cpg_clocks R8A7779_CLK_P>,
558				 <&cpg_clocks R8A7779_CLK_S>,
559				 <&cpg_clocks R8A7779_CLK_S>,
560				 <&cpg_clocks R8A7779_CLK_P>,
561				 <&cpg_clocks R8A7779_CLK_P>,
562				 <&cpg_clocks R8A7779_CLK_P>,
563				 <&cpg_clocks R8A7779_CLK_P>,
564				 <&cpg_clocks R8A7779_CLK_P>,
565				 <&cpg_clocks R8A7779_CLK_P>,
566				 <&cpg_clocks R8A7779_CLK_P>,
567				 <&cpg_clocks R8A7779_CLK_P>,
568				 <&cpg_clocks R8A7779_CLK_P>,
569				 <&cpg_clocks R8A7779_CLK_P>;
570			#clock-cells = <1>;
571			clock-indices = <
572				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
573				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
574				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
575				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
576				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
577				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
578				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
579				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
580			>;
581			clock-output-names =
582				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
583				"hscif0", "scif5", "scif4", "scif3", "scif2",
584				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
585				"i2c0";
586		};
587		mstp1_clks: clocks@ffc80034 {
588			compatible = "renesas,r8a7779-mstp-clocks",
589				     "renesas,cpg-mstp-clocks";
590			reg = <0xffc80034 4>, <0xffc80044 4>;
591			clocks = <&cpg_clocks R8A7779_CLK_P>,
592				 <&cpg_clocks R8A7779_CLK_P>,
593				 <&cpg_clocks R8A7779_CLK_S>,
594				 <&cpg_clocks R8A7779_CLK_S>,
595				 <&cpg_clocks R8A7779_CLK_S>,
596				 <&cpg_clocks R8A7779_CLK_S>,
597				 <&cpg_clocks R8A7779_CLK_P>,
598				 <&cpg_clocks R8A7779_CLK_P>,
599				 <&cpg_clocks R8A7779_CLK_P>,
600				 <&cpg_clocks R8A7779_CLK_S>;
601			#clock-cells = <1>;
602			clock-indices = <
603				R8A7779_CLK_USB01 R8A7779_CLK_USB2
604				R8A7779_CLK_DU R8A7779_CLK_VIN2
605				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
606				R8A7779_CLK_ETHER R8A7779_CLK_SATA
607				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
608			>;
609			clock-output-names =
610				"usb01", "usb2",
611				"du", "vin2",
612				"vin1", "vin0",
613				"ether", "sata",
614				"pcie", "vin3";
615		};
616		mstp3_clks: clocks@ffc8003c {
617			compatible = "renesas,r8a7779-mstp-clocks",
618				     "renesas,cpg-mstp-clocks";
619			reg = <0xffc8003c 4>;
620			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
621				 <&s4_clk>, <&s4_clk>;
622			#clock-cells = <1>;
623			clock-indices = <
624				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
625				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
626				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
627			>;
628			clock-output-names =
629				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
630				"mmc1", "mmc0";
631		};
632	};
633
634	prr: chipid@ff000044 {
635		compatible = "renesas,prr";
636		reg = <0xff000044 4>;
637	};
638
639	rst: reset-controller@ffcc0000 {
640		compatible = "renesas,r8a7779-reset-wdt";
641		reg = <0xffcc0000 0x48>;
642	};
643
644	sysc: system-controller@ffd85000 {
645		compatible = "renesas,r8a7779-sysc";
646		reg = <0xffd85000 0x0200>;
647		#power-domain-cells = <1>;
648	};
649};
650