1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; 25 reg = <0x0>; 26 operating-points = < 27 /* kHz uV */ 28 1416000 1300000 29 1200000 1175000 30 1008000 1125000 31 816000 1125000 32 600000 1100000 33 504000 1100000 34 312000 1075000 35 >; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 }; 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 next-level-cache = <&L2>; 43 reg = <0x1>; 44 }; 45 }; 46 47 display-subsystem { 48 compatible = "rockchip,display-subsystem"; 49 ports = <&vop0_out>, <&vop1_out>; 50 }; 51 52 sram: sram@10080000 { 53 compatible = "mmio-sram"; 54 reg = <0x10080000 0x10000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0 0x10080000 0x10000>; 58 59 smp-sram@0 { 60 compatible = "rockchip,rk3066-smp-sram"; 61 reg = <0x0 0x50>; 62 }; 63 }; 64 65 vop0: vop@1010c000 { 66 compatible = "rockchip,rk3066-vop"; 67 reg = <0x1010c000 0x19c>; 68 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&cru ACLK_LCDC0>, 70 <&cru DCLK_LCDC0>, 71 <&cru HCLK_LCDC0>; 72 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 73 power-domains = <&power RK3066_PD_VIO>; 74 resets = <&cru SRST_LCDC0_AXI>, 75 <&cru SRST_LCDC0_AHB>, 76 <&cru SRST_LCDC0_DCLK>; 77 reset-names = "axi", "ahb", "dclk"; 78 status = "disabled"; 79 80 vop0_out: port { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 vop0_out_hdmi: endpoint@0 { 85 reg = <0>; 86 remote-endpoint = <&hdmi_in_vop0>; 87 }; 88 }; 89 }; 90 91 vop1: vop@1010e000 { 92 compatible = "rockchip,rk3066-vop"; 93 reg = <0x1010e000 0x19c>; 94 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&cru ACLK_LCDC1>, 96 <&cru DCLK_LCDC1>, 97 <&cru HCLK_LCDC1>; 98 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 99 power-domains = <&power RK3066_PD_VIO>; 100 resets = <&cru SRST_LCDC1_AXI>, 101 <&cru SRST_LCDC1_AHB>, 102 <&cru SRST_LCDC1_DCLK>; 103 reset-names = "axi", "ahb", "dclk"; 104 status = "disabled"; 105 106 vop1_out: port { 107 #address-cells = <1>; 108 #size-cells = <0>; 109 110 vop1_out_hdmi: endpoint@0 { 111 reg = <0>; 112 remote-endpoint = <&hdmi_in_vop1>; 113 }; 114 }; 115 }; 116 117 hdmi: hdmi@10116000 { 118 compatible = "rockchip,rk3066-hdmi"; 119 reg = <0x10116000 0x2000>; 120 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&cru HCLK_HDMI>; 122 clock-names = "hclk"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 125 power-domains = <&power RK3066_PD_VIO>; 126 rockchip,grf = <&grf>; 127 status = "disabled"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 hdmi_in: port@0 { 134 reg = <0>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 hdmi_in_vop0: endpoint@0 { 139 reg = <0>; 140 remote-endpoint = <&vop0_out_hdmi>; 141 }; 142 143 hdmi_in_vop1: endpoint@1 { 144 reg = <1>; 145 remote-endpoint = <&vop1_out_hdmi>; 146 }; 147 }; 148 149 hdmi_out: port@1 { 150 reg = <1>; 151 }; 152 }; 153 }; 154 155 i2s0: i2s@10118000 { 156 compatible = "rockchip,rk3066-i2s"; 157 reg = <0x10118000 0x2000>; 158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&i2s0_bus>; 163 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 164 dma-names = "tx", "rx"; 165 clock-names = "i2s_hclk", "i2s_clk"; 166 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 167 rockchip,playback-channels = <8>; 168 rockchip,capture-channels = <2>; 169 #sound-dai-cells = <0>; 170 status = "disabled"; 171 }; 172 173 i2s1: i2s@1011a000 { 174 compatible = "rockchip,rk3066-i2s"; 175 reg = <0x1011a000 0x2000>; 176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&i2s1_bus>; 181 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 182 dma-names = "tx", "rx"; 183 clock-names = "i2s_hclk", "i2s_clk"; 184 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; 185 rockchip,playback-channels = <2>; 186 rockchip,capture-channels = <2>; 187 #sound-dai-cells = <0>; 188 status = "disabled"; 189 }; 190 191 i2s2: i2s@1011c000 { 192 compatible = "rockchip,rk3066-i2s"; 193 reg = <0x1011c000 0x2000>; 194 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&i2s2_bus>; 199 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 200 dma-names = "tx", "rx"; 201 clock-names = "i2s_hclk", "i2s_clk"; 202 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; 203 rockchip,playback-channels = <2>; 204 rockchip,capture-channels = <2>; 205 #sound-dai-cells = <0>; 206 status = "disabled"; 207 }; 208 209 cru: clock-controller@20000000 { 210 compatible = "rockchip,rk3066a-cru"; 211 reg = <0x20000000 0x1000>; 212 rockchip,grf = <&grf>; 213 214 #clock-cells = <1>; 215 #reset-cells = <1>; 216 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 217 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 218 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 219 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 220 assigned-clock-rates = <400000000>, <594000000>, 221 <300000000>, <150000000>, 222 <75000000>, <300000000>, 223 <150000000>, <75000000>; 224 }; 225 226 timer@2000e000 { 227 compatible = "snps,dw-apb-timer-osc"; 228 reg = <0x2000e000 0x100>; 229 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 231 clock-names = "timer", "pclk"; 232 }; 233 234 efuse: efuse@20010000 { 235 compatible = "rockchip,rk3066a-efuse"; 236 reg = <0x20010000 0x4000>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 clocks = <&cru PCLK_EFUSE>; 240 clock-names = "pclk_efuse"; 241 242 cpu_leakage: cpu_leakage@17 { 243 reg = <0x17 0x1>; 244 }; 245 }; 246 247 timer@20038000 { 248 compatible = "snps,dw-apb-timer-osc"; 249 reg = <0x20038000 0x100>; 250 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 252 clock-names = "timer", "pclk"; 253 }; 254 255 timer@2003a000 { 256 compatible = "snps,dw-apb-timer-osc"; 257 reg = <0x2003a000 0x100>; 258 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 260 clock-names = "timer", "pclk"; 261 }; 262 263 tsadc: tsadc@20060000 { 264 compatible = "rockchip,rk3066-tsadc"; 265 reg = <0x20060000 0x100>; 266 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 267 clock-names = "saradc", "apb_pclk"; 268 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 269 #io-channel-cells = <1>; 270 resets = <&cru SRST_TSADC>; 271 reset-names = "saradc-apb"; 272 status = "disabled"; 273 }; 274 275 usbphy: phy { 276 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; 277 rockchip,grf = <&grf>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 282 usbphy0: usb-phy@17c { 283 #phy-cells = <0>; 284 reg = <0x17c>; 285 clocks = <&cru SCLK_OTGPHY0>; 286 clock-names = "phyclk"; 287 #clock-cells = <0>; 288 }; 289 290 usbphy1: usb-phy@188 { 291 #phy-cells = <0>; 292 reg = <0x188>; 293 clocks = <&cru SCLK_OTGPHY1>; 294 clock-names = "phyclk"; 295 #clock-cells = <0>; 296 }; 297 }; 298 299 pinctrl: pinctrl { 300 compatible = "rockchip,rk3066a-pinctrl"; 301 rockchip,grf = <&grf>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges; 305 306 gpio0: gpio0@20034000 { 307 compatible = "rockchip,gpio-bank"; 308 reg = <0x20034000 0x100>; 309 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cru PCLK_GPIO0>; 311 312 gpio-controller; 313 #gpio-cells = <2>; 314 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 319 gpio1: gpio1@2003c000 { 320 compatible = "rockchip,gpio-bank"; 321 reg = <0x2003c000 0x100>; 322 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&cru PCLK_GPIO1>; 324 325 gpio-controller; 326 #gpio-cells = <2>; 327 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 }; 331 332 gpio2: gpio2@2003e000 { 333 compatible = "rockchip,gpio-bank"; 334 reg = <0x2003e000 0x100>; 335 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cru PCLK_GPIO2>; 337 338 gpio-controller; 339 #gpio-cells = <2>; 340 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 }; 344 345 gpio3: gpio3@20080000 { 346 compatible = "rockchip,gpio-bank"; 347 reg = <0x20080000 0x100>; 348 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cru PCLK_GPIO3>; 350 351 gpio-controller; 352 #gpio-cells = <2>; 353 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 }; 357 358 gpio4: gpio4@20084000 { 359 compatible = "rockchip,gpio-bank"; 360 reg = <0x20084000 0x100>; 361 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cru PCLK_GPIO4>; 363 364 gpio-controller; 365 #gpio-cells = <2>; 366 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 }; 370 371 gpio6: gpio6@2000a000 { 372 compatible = "rockchip,gpio-bank"; 373 reg = <0x2000a000 0x100>; 374 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cru PCLK_GPIO6>; 376 377 gpio-controller; 378 #gpio-cells = <2>; 379 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 }; 383 384 pcfg_pull_default: pcfg_pull_default { 385 bias-pull-pin-default; 386 }; 387 388 pcfg_pull_none: pcfg_pull_none { 389 bias-disable; 390 }; 391 392 emac { 393 emac_xfer: emac-xfer { 394 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 395 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 396 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 397 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 398 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 399 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 400 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 401 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 402 }; 403 404 emac_mdio: emac-mdio { 405 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 406 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 407 }; 408 }; 409 410 emmc { 411 emmc_clk: emmc-clk { 412 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 413 }; 414 415 emmc_cmd: emmc-cmd { 416 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 417 }; 418 419 emmc_rst: emmc-rst { 420 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 421 }; 422 423 /* 424 * The data pins are shared between nandc and emmc and 425 * not accessible through pinctrl. Also they should've 426 * been already set correctly by firmware, as 427 * flash/emmc is the boot-device. 428 */ 429 }; 430 431 hdmi { 432 hdmi_hpd: hdmi-hpd { 433 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 434 }; 435 436 hdmii2c_xfer: hdmii2c-xfer { 437 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 438 <0 RK_PA2 1 &pcfg_pull_none>; 439 }; 440 }; 441 442 i2c0 { 443 i2c0_xfer: i2c0-xfer { 444 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 445 <2 RK_PD5 1 &pcfg_pull_none>; 446 }; 447 }; 448 449 i2c1 { 450 i2c1_xfer: i2c1-xfer { 451 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 452 <2 RK_PD7 1 &pcfg_pull_none>; 453 }; 454 }; 455 456 i2c2 { 457 i2c2_xfer: i2c2-xfer { 458 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 459 <3 RK_PA1 1 &pcfg_pull_none>; 460 }; 461 }; 462 463 i2c3 { 464 i2c3_xfer: i2c3-xfer { 465 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 466 <3 RK_PA3 2 &pcfg_pull_none>; 467 }; 468 }; 469 470 i2c4 { 471 i2c4_xfer: i2c4-xfer { 472 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 473 <3 RK_PA5 1 &pcfg_pull_none>; 474 }; 475 }; 476 477 pwm0 { 478 pwm0_out: pwm0-out { 479 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 480 }; 481 }; 482 483 pwm1 { 484 pwm1_out: pwm1-out { 485 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 486 }; 487 }; 488 489 pwm2 { 490 pwm2_out: pwm2-out { 491 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 492 }; 493 }; 494 495 pwm3 { 496 pwm3_out: pwm3-out { 497 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 498 }; 499 }; 500 501 spi0 { 502 spi0_clk: spi0-clk { 503 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 504 }; 505 spi0_cs0: spi0-cs0 { 506 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 507 }; 508 spi0_tx: spi0-tx { 509 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 510 }; 511 spi0_rx: spi0-rx { 512 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 513 }; 514 spi0_cs1: spi0-cs1 { 515 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 516 }; 517 }; 518 519 spi1 { 520 spi1_clk: spi1-clk { 521 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 522 }; 523 spi1_cs0: spi1-cs0 { 524 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 525 }; 526 spi1_rx: spi1-rx { 527 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 528 }; 529 spi1_tx: spi1-tx { 530 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 531 }; 532 spi1_cs1: spi1-cs1 { 533 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 534 }; 535 }; 536 537 uart0 { 538 uart0_xfer: uart0-xfer { 539 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 540 <1 RK_PA1 1 &pcfg_pull_default>; 541 }; 542 543 uart0_cts: uart0-cts { 544 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 545 }; 546 547 uart0_rts: uart0-rts { 548 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 549 }; 550 }; 551 552 uart1 { 553 uart1_xfer: uart1-xfer { 554 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 555 <1 RK_PA5 1 &pcfg_pull_default>; 556 }; 557 558 uart1_cts: uart1-cts { 559 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 560 }; 561 562 uart1_rts: uart1-rts { 563 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 564 }; 565 }; 566 567 uart2 { 568 uart2_xfer: uart2-xfer { 569 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 570 <1 RK_PB1 1 &pcfg_pull_default>; 571 }; 572 /* no rts / cts for uart2 */ 573 }; 574 575 uart3 { 576 uart3_xfer: uart3-xfer { 577 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 578 <3 RK_PD4 1 &pcfg_pull_default>; 579 }; 580 581 uart3_cts: uart3-cts { 582 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 583 }; 584 585 uart3_rts: uart3-rts { 586 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 587 }; 588 }; 589 590 sd0 { 591 sd0_clk: sd0-clk { 592 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 593 }; 594 595 sd0_cmd: sd0-cmd { 596 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 597 }; 598 599 sd0_cd: sd0-cd { 600 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 601 }; 602 603 sd0_wp: sd0-wp { 604 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 605 }; 606 607 sd0_bus1: sd0-bus-width1 { 608 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 609 }; 610 611 sd0_bus4: sd0-bus-width4 { 612 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 613 <3 RK_PB3 1 &pcfg_pull_default>, 614 <3 RK_PB4 1 &pcfg_pull_default>, 615 <3 RK_PB5 1 &pcfg_pull_default>; 616 }; 617 }; 618 619 sd1 { 620 sd1_clk: sd1-clk { 621 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 622 }; 623 624 sd1_cmd: sd1-cmd { 625 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 626 }; 627 628 sd1_cd: sd1-cd { 629 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 630 }; 631 632 sd1_wp: sd1-wp { 633 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 634 }; 635 636 sd1_bus1: sd1-bus-width1 { 637 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 638 }; 639 640 sd1_bus4: sd1-bus-width4 { 641 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 642 <3 RK_PC2 1 &pcfg_pull_default>, 643 <3 RK_PC3 1 &pcfg_pull_default>, 644 <3 RK_PC4 1 &pcfg_pull_default>; 645 }; 646 }; 647 648 i2s0 { 649 i2s0_bus: i2s0-bus { 650 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 651 <0 RK_PB0 1 &pcfg_pull_default>, 652 <0 RK_PB1 1 &pcfg_pull_default>, 653 <0 RK_PB2 1 &pcfg_pull_default>, 654 <0 RK_PB3 1 &pcfg_pull_default>, 655 <0 RK_PB4 1 &pcfg_pull_default>, 656 <0 RK_PB5 1 &pcfg_pull_default>, 657 <0 RK_PB6 1 &pcfg_pull_default>, 658 <0 RK_PB7 1 &pcfg_pull_default>; 659 }; 660 }; 661 662 i2s1 { 663 i2s1_bus: i2s1-bus { 664 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 665 <0 RK_PC1 1 &pcfg_pull_default>, 666 <0 RK_PC2 1 &pcfg_pull_default>, 667 <0 RK_PC3 1 &pcfg_pull_default>, 668 <0 RK_PC4 1 &pcfg_pull_default>, 669 <0 RK_PC5 1 &pcfg_pull_default>; 670 }; 671 }; 672 673 i2s2 { 674 i2s2_bus: i2s2-bus { 675 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 676 <0 RK_PD1 1 &pcfg_pull_default>, 677 <0 RK_PD2 1 &pcfg_pull_default>, 678 <0 RK_PD3 1 &pcfg_pull_default>, 679 <0 RK_PD4 1 &pcfg_pull_default>, 680 <0 RK_PD5 1 &pcfg_pull_default>; 681 }; 682 }; 683 }; 684}; 685 686&gpu { 687 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 688 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-names = "gp", 699 "gpmmu", 700 "pp0", 701 "ppmmu0", 702 "pp1", 703 "ppmmu1", 704 "pp2", 705 "ppmmu2", 706 "pp3", 707 "ppmmu3"; 708 power-domains = <&power RK3066_PD_GPU>; 709}; 710 711&i2c0 { 712 pinctrl-names = "default"; 713 pinctrl-0 = <&i2c0_xfer>; 714}; 715 716&i2c1 { 717 pinctrl-names = "default"; 718 pinctrl-0 = <&i2c1_xfer>; 719}; 720 721&i2c2 { 722 pinctrl-names = "default"; 723 pinctrl-0 = <&i2c2_xfer>; 724}; 725 726&i2c3 { 727 pinctrl-names = "default"; 728 pinctrl-0 = <&i2c3_xfer>; 729}; 730 731&i2c4 { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&i2c4_xfer>; 734}; 735 736&mmc0 { 737 clock-frequency = <50000000>; 738 dmas = <&dmac2 1>; 739 dma-names = "rx-tx"; 740 max-frequency = <50000000>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 743}; 744 745&mmc1 { 746 dmas = <&dmac2 3>; 747 dma-names = "rx-tx"; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 750}; 751 752&emmc { 753 dmas = <&dmac2 4>; 754 dma-names = "rx-tx"; 755}; 756 757&pmu { 758 power: power-controller { 759 compatible = "rockchip,rk3066-power-controller"; 760 #power-domain-cells = <1>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 764 power-domain@RK3066_PD_VIO { 765 reg = <RK3066_PD_VIO>; 766 clocks = <&cru ACLK_LCDC0>, 767 <&cru ACLK_LCDC1>, 768 <&cru DCLK_LCDC0>, 769 <&cru DCLK_LCDC1>, 770 <&cru HCLK_LCDC0>, 771 <&cru HCLK_LCDC1>, 772 <&cru SCLK_CIF1>, 773 <&cru ACLK_CIF1>, 774 <&cru HCLK_CIF1>, 775 <&cru SCLK_CIF0>, 776 <&cru ACLK_CIF0>, 777 <&cru HCLK_CIF0>, 778 <&cru HCLK_HDMI>, 779 <&cru ACLK_IPP>, 780 <&cru HCLK_IPP>, 781 <&cru ACLK_RGA>, 782 <&cru HCLK_RGA>; 783 pm_qos = <&qos_lcdc0>, 784 <&qos_lcdc1>, 785 <&qos_cif0>, 786 <&qos_cif1>, 787 <&qos_ipp>, 788 <&qos_rga>; 789 }; 790 791 power-domain@RK3066_PD_VIDEO { 792 reg = <RK3066_PD_VIDEO>; 793 clocks = <&cru ACLK_VDPU>, 794 <&cru ACLK_VEPU>, 795 <&cru HCLK_VDPU>, 796 <&cru HCLK_VEPU>; 797 pm_qos = <&qos_vpu>; 798 }; 799 800 power-domain@RK3066_PD_GPU { 801 reg = <RK3066_PD_GPU>; 802 clocks = <&cru ACLK_GPU>; 803 pm_qos = <&qos_gpu>; 804 }; 805 }; 806}; 807 808&pwm0 { 809 pinctrl-names = "default"; 810 pinctrl-0 = <&pwm0_out>; 811}; 812 813&pwm1 { 814 pinctrl-names = "default"; 815 pinctrl-0 = <&pwm1_out>; 816}; 817 818&pwm2 { 819 pinctrl-names = "default"; 820 pinctrl-0 = <&pwm2_out>; 821}; 822 823&pwm3 { 824 pinctrl-names = "default"; 825 pinctrl-0 = <&pwm3_out>; 826}; 827 828&spi0 { 829 pinctrl-names = "default"; 830 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 831}; 832 833&spi1 { 834 pinctrl-names = "default"; 835 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 836}; 837 838&uart0 { 839 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 840 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 841 dma-names = "tx", "rx"; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&uart0_xfer>; 844}; 845 846&uart1 { 847 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 848 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 849 dma-names = "tx", "rx"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&uart1_xfer>; 852}; 853 854&uart2 { 855 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 856 dmas = <&dmac2 6>, <&dmac2 7>; 857 dma-names = "tx", "rx"; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&uart2_xfer>; 860}; 861 862&uart3 { 863 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 864 dmas = <&dmac2 8>, <&dmac2 9>; 865 dma-names = "tx", "rx"; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&uart3_xfer>; 868}; 869 870&wdt { 871 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 872}; 873 874&emac { 875 compatible = "rockchip,rk3066-emac"; 876}; 877