1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2012 Linaro Ltd 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/mfd/dbx500-prcmu.h> 9#include <dt-bindings/arm/ux500_pm_domains.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 chosen { 18 }; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 enable-method = "ste,dbx500-smp"; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&CPU0>; 29 }; 30 core1 { 31 cpu = <&CPU1>; 32 }; 33 }; 34 }; 35 CPU0: cpu@300 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a9"; 38 reg = <0x300>; 39 /* cpufreq controls */ 40 operating-points = <998400 0 41 800000 0 42 400000 0 43 200000 0>; 44 clocks = <&prcmu_clk PRCMU_ARMSS>; 45 clock-names = "cpu"; 46 clock-latency = <20000>; 47 #cooling-cells = <2>; 48 }; 49 CPU1: cpu@301 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a9"; 52 reg = <0x301>; 53 }; 54 }; 55 56 thermal-zones { 57 /* 58 * Thermal zone for the SoC, using the thermal sensor in the 59 * PRCMU for temperature and the cpufreq driver for passive 60 * cooling. 61 */ 62 cpu_thermal: cpu-thermal { 63 polling-delay-passive = <250>; 64 /* 65 * This sensor fires interrupts to update the thermal 66 * zone, so no polling is needed. 67 */ 68 polling-delay = <0>; 69 70 thermal-sensors = <&thermal>; 71 72 trips { 73 cpu_alert: cpu-alert { 74 temperature = <70000>; 75 hysteresis = <2000>; 76 type = "passive"; 77 }; 78 cpu-crit { 79 temperature = <85000>; 80 hysteresis = <0>; 81 type = "critical"; 82 }; 83 }; 84 85 cooling-maps { 86 trip = <&cpu_alert>; 87 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 88 contribution = <100>; 89 }; 90 }; 91 }; 92 93 soc { 94 #address-cells = <1>; 95 #size-cells = <1>; 96 compatible = "stericsson,db8500"; 97 interrupt-parent = <&intc>; 98 ranges; 99 100 ptm@801ae000 { 101 compatible = "arm,coresight-etm3x", "arm,primecell"; 102 reg = <0x801ae000 0x1000>; 103 104 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 105 clock-names = "apb_pclk", "atclk"; 106 cpu = <&CPU0>; 107 out-ports { 108 port { 109 ptm0_out_port: endpoint { 110 remote-endpoint = <&funnel_in_port0>; 111 }; 112 }; 113 }; 114 }; 115 116 ptm@801af000 { 117 compatible = "arm,coresight-etm3x", "arm,primecell"; 118 reg = <0x801af000 0x1000>; 119 120 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 121 clock-names = "apb_pclk", "atclk"; 122 cpu = <&CPU1>; 123 out-ports { 124 port { 125 ptm1_out_port: endpoint { 126 remote-endpoint = <&funnel_in_port1>; 127 }; 128 }; 129 }; 130 }; 131 132 funnel@801a6000 { 133 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 134 reg = <0x801a6000 0x1000>; 135 136 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 137 clock-names = "apb_pclk", "atclk"; 138 out-ports { 139 port { 140 funnel_out_port: endpoint { 141 remote-endpoint = 142 <&replicator_in_port0>; 143 }; 144 }; 145 }; 146 147 in-ports { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 port@0 { 152 reg = <0>; 153 funnel_in_port0: endpoint { 154 remote-endpoint = <&ptm0_out_port>; 155 }; 156 }; 157 158 port@1 { 159 reg = <1>; 160 funnel_in_port1: endpoint { 161 remote-endpoint = <&ptm1_out_port>; 162 }; 163 }; 164 }; 165 }; 166 167 replicator { 168 compatible = "arm,coresight-static-replicator"; 169 clocks = <&prcmu_clk PRCMU_APEATCLK>; 170 clock-names = "atclk"; 171 172 out-ports { 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 port@0 { 177 reg = <0>; 178 replicator_out_port0: endpoint { 179 remote-endpoint = <&tpiu_in_port>; 180 }; 181 }; 182 port@1 { 183 reg = <1>; 184 replicator_out_port1: endpoint { 185 remote-endpoint = <&etb_in_port>; 186 }; 187 }; 188 }; 189 190 in-ports { 191 port { 192 replicator_in_port0: endpoint { 193 remote-endpoint = <&funnel_out_port>; 194 }; 195 }; 196 }; 197 }; 198 199 tpiu@80190000 { 200 compatible = "arm,coresight-tpiu", "arm,primecell"; 201 reg = <0x80190000 0x1000>; 202 203 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 204 clock-names = "apb_pclk", "atclk"; 205 in-ports { 206 port { 207 tpiu_in_port: endpoint { 208 remote-endpoint = <&replicator_out_port0>; 209 }; 210 }; 211 }; 212 }; 213 214 etb@801a4000 { 215 compatible = "arm,coresight-etb10", "arm,primecell"; 216 reg = <0x801a4000 0x1000>; 217 218 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 219 clock-names = "apb_pclk", "atclk"; 220 in-ports { 221 port { 222 etb_in_port: endpoint { 223 remote-endpoint = <&replicator_out_port1>; 224 }; 225 }; 226 }; 227 }; 228 229 intc: interrupt-controller@a0411000 { 230 compatible = "arm,cortex-a9-gic"; 231 #interrupt-cells = <3>; 232 #address-cells = <1>; 233 interrupt-controller; 234 reg = <0xa0411000 0x1000>, 235 <0xa0410100 0x100>; 236 }; 237 238 scu@a0410000 { 239 compatible = "arm,cortex-a9-scu"; 240 reg = <0xa0410000 0x100>; 241 }; 242 243 /* 244 * The backup RAM is used for retention during sleep 245 * and various things like spin tables 246 */ 247 backupram@80150000 { 248 compatible = "ste,dbx500-backupram"; 249 reg = <0x80150000 0x2000>; 250 }; 251 252 L2: l2-cache { 253 compatible = "arm,pl310-cache"; 254 reg = <0xa0412000 0x1000>; 255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 256 cache-unified; 257 cache-level = <2>; 258 }; 259 260 pmu { 261 compatible = "arm,cortex-a9-pmu"; 262 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 263 }; 264 265 pm_domains: pm_domains0 { 266 compatible = "stericsson,ux500-pm-domains"; 267 #power-domain-cells = <1>; 268 }; 269 270 clocks { 271 compatible = "stericsson,u8500-clks"; 272 /* 273 * Registers for the CLKRST block on peripheral 274 * groups 1, 2, 3, 5, 6, 275 */ 276 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, 277 <0x8000f000 0x1000>, <0xa03ff000 0x1000>, 278 <0xa03cf000 0x1000>; 279 280 prcmu_clk: prcmu-clock { 281 #clock-cells = <1>; 282 }; 283 284 prcc_pclk: prcc-periph-clock { 285 #clock-cells = <2>; 286 }; 287 288 prcc_kclk: prcc-kernel-clock { 289 #clock-cells = <2>; 290 }; 291 292 rtc_clk: rtc32k-clock { 293 #clock-cells = <0>; 294 }; 295 296 smp_twd_clk: smp-twd-clock { 297 #clock-cells = <0>; 298 }; 299 }; 300 301 mtu@a03c6000 { 302 /* Nomadik System Timer */ 303 compatible = "st,nomadik-mtu"; 304 reg = <0xa03c6000 0x1000>; 305 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 306 307 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; 308 clock-names = "timclk", "apb_pclk"; 309 }; 310 311 timer@a0410600 { 312 compatible = "arm,cortex-a9-twd-timer"; 313 reg = <0xa0410600 0x20>; 314 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 315 316 clocks = <&smp_twd_clk>; 317 }; 318 319 watchdog@a0410620 { 320 compatible = "arm,cortex-a9-twd-wdt"; 321 reg = <0xa0410620 0x20>; 322 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 323 clocks = <&smp_twd_clk>; 324 }; 325 326 rtc@80154000 { 327 compatible = "arm,rtc-pl031", "arm,primecell"; 328 reg = <0x80154000 0x1000>; 329 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 330 331 clocks = <&rtc_clk>; 332 clock-names = "apb_pclk"; 333 }; 334 335 gpio0: gpio@8012e000 { 336 compatible = "stericsson,db8500-gpio", 337 "st,nomadik-gpio"; 338 reg = <0x8012e000 0x80>; 339 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 st,supports-sleepmode; 343 gpio-controller; 344 #gpio-cells = <2>; 345 gpio-bank = <0>; 346 gpio-ranges = <&pinctrl 0 0 32>; 347 clocks = <&prcc_pclk 1 9>; 348 }; 349 350 gpio1: gpio@8012e080 { 351 compatible = "stericsson,db8500-gpio", 352 "st,nomadik-gpio"; 353 reg = <0x8012e080 0x80>; 354 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-controller; 356 #interrupt-cells = <2>; 357 st,supports-sleepmode; 358 gpio-controller; 359 #gpio-cells = <2>; 360 gpio-bank = <1>; 361 gpio-ranges = <&pinctrl 0 32 5>; 362 clocks = <&prcc_pclk 1 9>; 363 }; 364 365 gpio2: gpio@8000e000 { 366 compatible = "stericsson,db8500-gpio", 367 "st,nomadik-gpio"; 368 reg = <0x8000e000 0x80>; 369 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 st,supports-sleepmode; 373 gpio-controller; 374 #gpio-cells = <2>; 375 gpio-bank = <2>; 376 gpio-ranges = <&pinctrl 0 64 32>; 377 clocks = <&prcc_pclk 3 8>; 378 }; 379 380 gpio3: gpio@8000e080 { 381 compatible = "stericsson,db8500-gpio", 382 "st,nomadik-gpio"; 383 reg = <0x8000e080 0x80>; 384 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 st,supports-sleepmode; 388 gpio-controller; 389 #gpio-cells = <2>; 390 gpio-bank = <3>; 391 gpio-ranges = <&pinctrl 0 96 2>; 392 clocks = <&prcc_pclk 3 8>; 393 }; 394 395 gpio4: gpio@8000e100 { 396 compatible = "stericsson,db8500-gpio", 397 "st,nomadik-gpio"; 398 reg = <0x8000e100 0x80>; 399 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 400 interrupt-controller; 401 #interrupt-cells = <2>; 402 st,supports-sleepmode; 403 gpio-controller; 404 #gpio-cells = <2>; 405 gpio-bank = <4>; 406 gpio-ranges = <&pinctrl 0 128 32>; 407 clocks = <&prcc_pclk 3 8>; 408 }; 409 410 gpio5: gpio@8000e180 { 411 compatible = "stericsson,db8500-gpio", 412 "st,nomadik-gpio"; 413 reg = <0x8000e180 0x80>; 414 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 st,supports-sleepmode; 418 gpio-controller; 419 #gpio-cells = <2>; 420 gpio-bank = <5>; 421 gpio-ranges = <&pinctrl 0 160 12>; 422 clocks = <&prcc_pclk 3 8>; 423 }; 424 425 gpio6: gpio@8011e000 { 426 compatible = "stericsson,db8500-gpio", 427 "st,nomadik-gpio"; 428 reg = <0x8011e000 0x80>; 429 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 st,supports-sleepmode; 433 gpio-controller; 434 #gpio-cells = <2>; 435 gpio-bank = <6>; 436 gpio-ranges = <&pinctrl 0 192 32>; 437 clocks = <&prcc_pclk 2 11>; 438 }; 439 440 gpio7: gpio@8011e080 { 441 compatible = "stericsson,db8500-gpio", 442 "st,nomadik-gpio"; 443 reg = <0x8011e080 0x80>; 444 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 st,supports-sleepmode; 448 gpio-controller; 449 #gpio-cells = <2>; 450 gpio-bank = <7>; 451 gpio-ranges = <&pinctrl 0 224 7>; 452 clocks = <&prcc_pclk 2 11>; 453 }; 454 455 gpio8: gpio@a03fe000 { 456 compatible = "stericsson,db8500-gpio", 457 "st,nomadik-gpio"; 458 reg = <0xa03fe000 0x80>; 459 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 st,supports-sleepmode; 463 gpio-controller; 464 #gpio-cells = <2>; 465 gpio-bank = <8>; 466 gpio-ranges = <&pinctrl 0 256 12>; 467 clocks = <&prcc_pclk 5 1>; 468 }; 469 470 pinctrl: pinctrl { 471 compatible = "stericsson,db8500-pinctrl"; 472 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, 473 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, 474 <&gpio8>; 475 prcm = <&prcmu>; 476 }; 477 478 usb_per5@a03e0000 { 479 compatible = "stericsson,db8500-musb"; 480 reg = <0xa03e0000 0x10000>; 481 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "mc"; 483 484 dr_mode = "otg"; 485 486 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ 487 <&dma 38 0 0x0>, /* Logical - MemToDev */ 488 <&dma 37 0 0x2>, /* Logical - DevToMem */ 489 <&dma 37 0 0x0>, /* Logical - MemToDev */ 490 <&dma 36 0 0x2>, /* Logical - DevToMem */ 491 <&dma 36 0 0x0>, /* Logical - MemToDev */ 492 <&dma 19 0 0x2>, /* Logical - DevToMem */ 493 <&dma 19 0 0x0>, /* Logical - MemToDev */ 494 <&dma 18 0 0x2>, /* Logical - DevToMem */ 495 <&dma 18 0 0x0>, /* Logical - MemToDev */ 496 <&dma 17 0 0x2>, /* Logical - DevToMem */ 497 <&dma 17 0 0x0>, /* Logical - MemToDev */ 498 <&dma 16 0 0x2>, /* Logical - DevToMem */ 499 <&dma 16 0 0x0>, /* Logical - MemToDev */ 500 <&dma 39 0 0x2>, /* Logical - DevToMem */ 501 <&dma 39 0 0x0>; /* Logical - MemToDev */ 502 503 dma-names = "iep_1_9", "oep_1_9", 504 "iep_2_10", "oep_2_10", 505 "iep_3_11", "oep_3_11", 506 "iep_4_12", "oep_4_12", 507 "iep_5_13", "oep_5_13", 508 "iep_6_14", "oep_6_14", 509 "iep_7_15", "oep_7_15", 510 "iep_8", "oep_8"; 511 512 clocks = <&prcc_pclk 5 0>; 513 }; 514 515 dma: dma-controller@801C0000 { 516 compatible = "stericsson,db8500-dma40", "stericsson,dma40"; 517 reg = <0x801C0000 0x1000 0x40010000 0x800>; 518 reg-names = "base", "lcpa"; 519 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 520 521 #dma-cells = <3>; 522 memcpy-channels = <56 57 58 59 60>; 523 524 clocks = <&prcmu_clk PRCMU_DMACLK>; 525 }; 526 527 prcmu: prcmu@80157000 { 528 compatible = "stericsson,db8500-prcmu", "syscon"; 529 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; 530 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; 531 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 532 #address-cells = <1>; 533 #size-cells = <1>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 ranges; 537 538 prcmu-timer-4@80157450 { 539 compatible = "stericsson,db8500-prcmu-timer-4"; 540 reg = <0x80157450 0xC>; 541 }; 542 543 thermal: thermal@801573c0 { 544 compatible = "stericsson,db8500-thermal"; 545 reg = <0x801573c0 0x40>; 546 interrupt-parent = <&prcmu>; 547 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, 548 <22 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; 550 #thermal-sensor-cells = <0>; 551 }; 552 553 db8500-prcmu-regulators { 554 compatible = "stericsson,db8500-prcmu-regulator"; 555 556 // DB8500_REGULATOR_VAPE 557 db8500_vape_reg: db8500_vape { 558 regulator-always-on; 559 }; 560 561 // DB8500_REGULATOR_VARM 562 db8500_varm_reg: db8500_varm { 563 }; 564 565 // DB8500_REGULATOR_VMODEM 566 db8500_vmodem_reg: db8500_vmodem { 567 }; 568 569 // DB8500_REGULATOR_VPLL 570 db8500_vpll_reg: db8500_vpll { 571 }; 572 573 // DB8500_REGULATOR_VSMPS1 574 db8500_vsmps1_reg: db8500_vsmps1 { 575 }; 576 577 // DB8500_REGULATOR_VSMPS2 578 db8500_vsmps2_reg: db8500_vsmps2 { 579 }; 580 581 // DB8500_REGULATOR_VSMPS3 582 db8500_vsmps3_reg: db8500_vsmps3 { 583 }; 584 585 // DB8500_REGULATOR_VRF1 586 db8500_vrf1_reg: db8500_vrf1 { 587 }; 588 589 // DB8500_REGULATOR_SWITCH_SVAMMDSP 590 db8500_sva_mmdsp_reg: db8500_sva_mmdsp { 591 }; 592 593 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET 594 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { 595 }; 596 597 // DB8500_REGULATOR_SWITCH_SVAPIPE 598 db8500_sva_pipe_reg: db8500_sva_pipe { 599 }; 600 601 // DB8500_REGULATOR_SWITCH_SIAMMDSP 602 db8500_sia_mmdsp_reg: db8500_sia_mmdsp { 603 }; 604 605 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET 606 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { 607 }; 608 609 // DB8500_REGULATOR_SWITCH_SIAPIPE 610 db8500_sia_pipe_reg: db8500_sia_pipe { 611 }; 612 613 // DB8500_REGULATOR_SWITCH_SGA 614 db8500_sga_reg: db8500_sga { 615 vin-supply = <&db8500_vape_reg>; 616 }; 617 618 // DB8500_REGULATOR_SWITCH_B2R2_MCDE 619 db8500_b2r2_mcde_reg: db8500_b2r2_mcde { 620 vin-supply = <&db8500_vape_reg>; 621 }; 622 623 // DB8500_REGULATOR_SWITCH_ESRAM12 624 db8500_esram12_reg: db8500_esram12 { 625 }; 626 627 // DB8500_REGULATOR_SWITCH_ESRAM12RET 628 db8500_esram12_ret_reg: db8500_esram12_ret { 629 }; 630 631 // DB8500_REGULATOR_SWITCH_ESRAM34 632 db8500_esram34_reg: db8500_esram34 { 633 }; 634 635 // DB8500_REGULATOR_SWITCH_ESRAM34RET 636 db8500_esram34_ret_reg: db8500_esram34_ret { 637 }; 638 }; 639 }; 640 641 i2c@80004000 { 642 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 643 reg = <0x80004000 0x1000>; 644 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 645 646 #address-cells = <1>; 647 #size-cells = <0>; 648 v-i2c-supply = <&db8500_vape_reg>; 649 650 clock-frequency = <400000>; 651 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; 652 clock-names = "i2cclk", "apb_pclk"; 653 power-domains = <&pm_domains DOMAIN_VAPE>; 654 }; 655 656 i2c@80122000 { 657 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 658 reg = <0x80122000 0x1000>; 659 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 660 661 #address-cells = <1>; 662 #size-cells = <0>; 663 v-i2c-supply = <&db8500_vape_reg>; 664 665 clock-frequency = <400000>; 666 667 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; 668 clock-names = "i2cclk", "apb_pclk"; 669 power-domains = <&pm_domains DOMAIN_VAPE>; 670 }; 671 672 i2c@80128000 { 673 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 674 reg = <0x80128000 0x1000>; 675 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 676 677 #address-cells = <1>; 678 #size-cells = <0>; 679 v-i2c-supply = <&db8500_vape_reg>; 680 681 clock-frequency = <400000>; 682 683 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; 684 clock-names = "i2cclk", "apb_pclk"; 685 power-domains = <&pm_domains DOMAIN_VAPE>; 686 }; 687 688 i2c@80110000 { 689 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 690 reg = <0x80110000 0x1000>; 691 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 692 693 #address-cells = <1>; 694 #size-cells = <0>; 695 v-i2c-supply = <&db8500_vape_reg>; 696 697 clock-frequency = <400000>; 698 699 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; 700 clock-names = "i2cclk", "apb_pclk"; 701 power-domains = <&pm_domains DOMAIN_VAPE>; 702 }; 703 704 i2c@8012a000 { 705 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 706 reg = <0x8012a000 0x1000>; 707 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 708 709 #address-cells = <1>; 710 #size-cells = <0>; 711 v-i2c-supply = <&db8500_vape_reg>; 712 713 clock-frequency = <400000>; 714 715 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; 716 clock-names = "i2cclk", "apb_pclk"; 717 power-domains = <&pm_domains DOMAIN_VAPE>; 718 }; 719 720 spi@80002000 { 721 compatible = "arm,pl022", "arm,primecell"; 722 reg = <0x80002000 0x1000>; 723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; 727 clock-names = "SSPCLK", "apb_pclk"; 728 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ 729 <&dma 8 0 0x0>; /* Logical - MemToDev */ 730 dma-names = "rx", "tx"; 731 power-domains = <&pm_domains DOMAIN_VAPE>; 732 }; 733 734 spi@80003000 { 735 compatible = "arm,pl022", "arm,primecell"; 736 reg = <0x80003000 0x1000>; 737 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; 741 clock-names = "SSPCLK", "apb_pclk"; 742 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ 743 <&dma 9 0 0x0>; /* Logical - MemToDev */ 744 dma-names = "rx", "tx"; 745 power-domains = <&pm_domains DOMAIN_VAPE>; 746 }; 747 748 spi@8011a000 { 749 compatible = "arm,pl022", "arm,primecell"; 750 reg = <0x8011a000 0x1000>; 751 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 /* Same clock wired to kernel and pclk */ 755 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; 756 clock-names = "SSPCLK", "apb_pclk"; 757 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ 758 <&dma 0 0 0x0>; /* Logical - MemToDev */ 759 dma-names = "rx", "tx"; 760 power-domains = <&pm_domains DOMAIN_VAPE>; 761 }; 762 763 spi@80112000 { 764 compatible = "arm,pl022", "arm,primecell"; 765 reg = <0x80112000 0x1000>; 766 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 /* Same clock wired to kernel and pclk */ 770 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; 771 clock-names = "SSPCLK", "apb_pclk"; 772 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ 773 <&dma 35 0 0x0>; /* Logical - MemToDev */ 774 dma-names = "rx", "tx"; 775 power-domains = <&pm_domains DOMAIN_VAPE>; 776 }; 777 778 spi@80111000 { 779 compatible = "arm,pl022", "arm,primecell"; 780 reg = <0x80111000 0x1000>; 781 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 /* Same clock wired to kernel and pclk */ 785 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; 786 clock-names = "SSPCLK", "apb_pclk"; 787 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ 788 <&dma 33 0 0x0>; /* Logical - MemToDev */ 789 dma-names = "rx", "tx"; 790 power-domains = <&pm_domains DOMAIN_VAPE>; 791 }; 792 793 spi@80129000 { 794 compatible = "arm,pl022", "arm,primecell"; 795 reg = <0x80129000 0x1000>; 796 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 /* Same clock wired to kernel and pclk */ 800 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; 801 clock-names = "SSPCLK", "apb_pclk"; 802 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ 803 <&dma 40 0 0x0>; /* Logical - MemToDev */ 804 dma-names = "rx", "tx"; 805 power-domains = <&pm_domains DOMAIN_VAPE>; 806 }; 807 808 ux500_serial0: uart@80120000 { 809 compatible = "arm,pl011", "arm,primecell"; 810 reg = <0x80120000 0x1000>; 811 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 812 813 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ 814 <&dma 13 0 0x0>; /* Logical - MemToDev */ 815 dma-names = "rx", "tx"; 816 817 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; 818 clock-names = "uart", "apb_pclk"; 819 820 status = "disabled"; 821 }; 822 823 ux500_serial1: uart@80121000 { 824 compatible = "arm,pl011", "arm,primecell"; 825 reg = <0x80121000 0x1000>; 826 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 827 828 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ 829 <&dma 12 0 0x0>; /* Logical - MemToDev */ 830 dma-names = "rx", "tx"; 831 832 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; 833 clock-names = "uart", "apb_pclk"; 834 835 status = "disabled"; 836 }; 837 838 ux500_serial2: uart@80007000 { 839 compatible = "arm,pl011", "arm,primecell"; 840 reg = <0x80007000 0x1000>; 841 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 842 843 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ 844 <&dma 11 0 0x0>; /* Logical - MemToDev */ 845 dma-names = "rx", "tx"; 846 847 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; 848 clock-names = "uart", "apb_pclk"; 849 850 status = "disabled"; 851 }; 852 853 sdi0_per1@80126000 { 854 compatible = "arm,pl18x", "arm,primecell"; 855 reg = <0x80126000 0x1000>; 856 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 857 858 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ 859 <&dma 29 0 0x0>; /* Logical - MemToDev */ 860 dma-names = "rx", "tx"; 861 862 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; 863 clock-names = "sdi", "apb_pclk"; 864 power-domains = <&pm_domains DOMAIN_VAPE>; 865 866 status = "disabled"; 867 }; 868 869 sdi1_per2@80118000 { 870 compatible = "arm,pl18x", "arm,primecell"; 871 reg = <0x80118000 0x1000>; 872 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 873 874 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ 875 <&dma 32 0 0x0>; /* Logical - MemToDev */ 876 dma-names = "rx", "tx"; 877 878 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; 879 clock-names = "sdi", "apb_pclk"; 880 power-domains = <&pm_domains DOMAIN_VAPE>; 881 882 status = "disabled"; 883 }; 884 885 sdi2_per3@80005000 { 886 compatible = "arm,pl18x", "arm,primecell"; 887 reg = <0x80005000 0x1000>; 888 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 889 890 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ 891 <&dma 28 0 0x0>; /* Logical - MemToDev */ 892 dma-names = "rx", "tx"; 893 894 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; 895 clock-names = "sdi", "apb_pclk"; 896 power-domains = <&pm_domains DOMAIN_VAPE>; 897 898 status = "disabled"; 899 }; 900 901 sdi3_per2@80119000 { 902 compatible = "arm,pl18x", "arm,primecell"; 903 reg = <0x80119000 0x1000>; 904 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 905 906 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ 907 <&dma 41 0 0x0>; /* Logical - MemToDev */ 908 dma-names = "rx", "tx"; 909 910 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; 911 clock-names = "sdi", "apb_pclk"; 912 power-domains = <&pm_domains DOMAIN_VAPE>; 913 914 status = "disabled"; 915 }; 916 917 sdi4_per2@80114000 { 918 compatible = "arm,pl18x", "arm,primecell"; 919 reg = <0x80114000 0x1000>; 920 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 921 922 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ 923 <&dma 42 0 0x0>; /* Logical - MemToDev */ 924 dma-names = "rx", "tx"; 925 926 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; 927 clock-names = "sdi", "apb_pclk"; 928 power-domains = <&pm_domains DOMAIN_VAPE>; 929 930 status = "disabled"; 931 }; 932 933 sdi5_per3@80008000 { 934 compatible = "arm,pl18x", "arm,primecell"; 935 reg = <0x80008000 0x1000>; 936 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 937 938 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ 939 <&dma 43 0 0x0>; /* Logical - MemToDev */ 940 dma-names = "rx", "tx"; 941 942 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; 943 clock-names = "sdi", "apb_pclk"; 944 power-domains = <&pm_domains DOMAIN_VAPE>; 945 946 status = "disabled"; 947 }; 948 949 sound { 950 compatible = "stericsson,snd-soc-mop500"; 951 stericsson,cpu-dai = <&msp1 &msp3>; 952 }; 953 954 msp0: msp@80123000 { 955 compatible = "stericsson,ux500-msp-i2s"; 956 reg = <0x80123000 0x1000>; 957 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 958 v-ape-supply = <&db8500_vape_reg>; 959 960 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ 961 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ 962 dma-names = "rx", "tx"; 963 964 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; 965 clock-names = "msp", "apb_pclk"; 966 967 status = "disabled"; 968 }; 969 970 msp1: msp@80124000 { 971 compatible = "stericsson,ux500-msp-i2s"; 972 reg = <0x80124000 0x1000>; 973 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 974 v-ape-supply = <&db8500_vape_reg>; 975 976 /* This DMA channel only exist on DB8500 v1 */ 977 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ 978 dma-names = "tx"; 979 980 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; 981 clock-names = "msp", "apb_pclk"; 982 983 status = "disabled"; 984 }; 985 986 // HDMI sound 987 msp2: msp@80117000 { 988 compatible = "stericsson,ux500-msp-i2s"; 989 reg = <0x80117000 0x1000>; 990 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 991 v-ape-supply = <&db8500_vape_reg>; 992 993 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ 994 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev 995 HighPrio - Fixed */ 996 dma-names = "rx", "tx"; 997 998 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; 999 clock-names = "msp", "apb_pclk"; 1000 1001 status = "disabled"; 1002 }; 1003 1004 msp3: msp@80125000 { 1005 compatible = "stericsson,ux500-msp-i2s"; 1006 reg = <0x80125000 0x1000>; 1007 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1008 v-ape-supply = <&db8500_vape_reg>; 1009 1010 /* This DMA channel only exist on DB8500 v2 */ 1011 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ 1012 dma-names = "rx"; 1013 1014 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; 1015 clock-names = "msp", "apb_pclk"; 1016 1017 status = "disabled"; 1018 }; 1019 1020 external-bus@50000000 { 1021 compatible = "simple-bus"; 1022 reg = <0x50000000 0x4000000>; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 ranges = <0 0x50000000 0x4000000>; 1026 status = "disabled"; 1027 }; 1028 1029 gpu@a0300000 { 1030 /* 1031 * This block is referred to as "Smart Graphics Adapter SGA500" 1032 * in documentation but is in practice a pretty straight-forward 1033 * MALI-400 GPU block. 1034 */ 1035 compatible = "stericsson,db8500-mali", "arm,mali-400"; 1036 reg = <0xa0300000 0x10000>; 1037 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1042 interrupt-names = "gp", 1043 "gpmmu", 1044 "pp0", 1045 "ppmmu0", 1046 "combined"; 1047 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; 1048 clock-names = "bus", "core"; 1049 mali-supply = <&db8500_sga_reg>; 1050 power-domains = <&pm_domains DOMAIN_VAPE>; 1051 }; 1052 1053 mcde@a0350000 { 1054 compatible = "ste,mcde"; 1055 reg = <0xa0350000 0x1000>; 1056 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1057 epod-supply = <&db8500_b2r2_mcde_reg>; 1058 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ 1059 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ 1060 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ 1061 clock-names = "mcde", "lcd", "hdmi"; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges; 1065 status = "disabled"; 1066 1067 dsi0: dsi@a0351000 { 1068 compatible = "ste,mcde-dsi"; 1069 reg = <0xa0351000 0x1000>; 1070 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; 1071 clock-names = "hs", "lp"; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 }; 1075 dsi1: dsi@a0352000 { 1076 compatible = "ste,mcde-dsi"; 1077 reg = <0xa0352000 0x1000>; 1078 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; 1079 clock-names = "hs", "lp"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 }; 1083 dsi2: dsi@a0353000 { 1084 compatible = "ste,mcde-dsi"; 1085 reg = <0xa0353000 0x1000>; 1086 /* This DSI port only has the Low Power / Energy Save clock */ 1087 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; 1088 clock-names = "lp"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 }; 1092 }; 1093 1094 cryp@a03cb000 { 1095 compatible = "stericsson,ux500-cryp"; 1096 reg = <0xa03cb000 0x1000>; 1097 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1098 1099 v-ape-supply = <&db8500_vape_reg>; 1100 clocks = <&prcc_pclk 6 1>; 1101 }; 1102 1103 hash@a03c2000 { 1104 compatible = "stericsson,ux500-hash"; 1105 reg = <0xa03c2000 0x1000>; 1106 1107 v-ape-supply = <&db8500_vape_reg>; 1108 clocks = <&prcc_pclk 6 2>; 1109 }; 1110 }; 1111}; 1112