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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Linaro Ltd.
4 */
5
6#include "ste-nomadik-pinctrl.dtsi"
7
8/ {
9	soc {
10		pinctrl {
11			/* Settings for all UART default and sleep states */
12			uart0 {
13				uart0_default_mode: uart0_default {
14					default_mux {
15						function = "u0";
16						groups = "u0_a_1";
17					};
18					default_cfg1 {
19						pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
20						ste,config = <&in_pu>;
21					};
22
23					default_cfg2 {
24						pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
25						ste,config = <&out_hi>;
26					};
27				};
28
29				uart0_sleep_mode: uart0_sleep {
30					sleep_cfg1 {
31						pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
32						ste,config = <&slpm_in_wkup_pdis>;
33					};
34
35					sleep_cfg2 {
36						pins = "GPIO1_AJ3"; /* RTS */
37						ste,config = <&slpm_out_hi_wkup_pdis>;
38					};
39
40					sleep_cfg3 {
41						pins = "GPIO3_AH3"; /* TXD */
42						ste,config = <&slpm_out_wkup_pdis>;
43					};
44				};
45			};
46
47			uart1 {
48				uart1_default_mode: uart1_default {
49					default_mux {
50						function = "u1";
51						groups = "u1rxtx_a_1";
52					};
53					default_cfg1 {
54						pins = "GPIO4_AH6"; /* RXD */
55						ste,config = <&in_pu>;
56					};
57
58					default_cfg2 {
59						pins = "GPIO5_AG6"; /* TXD */
60						ste,config = <&out_hi>;
61					};
62				};
63
64				uart1_sleep_mode: uart1_sleep {
65					sleep_cfg1 {
66						pins = "GPIO4_AH6"; /* RXD */
67						ste,config = <&slpm_in_wkup_pdis>;
68					};
69
70					sleep_cfg2 {
71						pins = "GPIO5_AG6"; /* TXD */
72						ste,config = <&slpm_out_wkup_pdis>;
73					};
74				};
75			};
76
77			uart2 {
78				uart2_default_mode: uart2_default {
79					default_mux {
80						function = "u2";
81						groups = "u2rxtx_c_1";
82					};
83					default_cfg1 {
84						pins = "GPIO29_W2"; /* RXD */
85						ste,config = <&in_pu>;
86					};
87
88					default_cfg2 {
89						pins = "GPIO30_W3"; /* TXD */
90						ste,config = <&out_hi>;
91					};
92				};
93
94				uart2_sleep_mode: uart2_sleep {
95					sleep_cfg1 {
96						pins = "GPIO29_W2"; /* RXD */
97						ste,config = <&in_wkup_pdis>;
98					};
99
100					sleep_cfg2 {
101						pins = "GPIO30_W3"; /* TXD */
102						ste,config = <&out_wkup_pdis>;
103					};
104				};
105			};
106
107			/* Settings for all I2C default and sleep states */
108			i2c0 {
109				i2c0_default_mode: i2c_default {
110					default_mux {
111						function = "i2c0";
112						groups = "i2c0_a_1";
113					};
114					default_cfg1 {
115						pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
116						ste,config = <&in_pu>;
117					};
118				};
119
120				i2c0_sleep_mode: i2c_sleep {
121					sleep_cfg1 {
122						pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
123						ste,config = <&slpm_in_wkup_pdis>;
124					};
125				};
126			};
127
128			i2c1 {
129				i2c1_default_mode: i2c_default {
130					default_mux {
131						function = "i2c1";
132						groups = "i2c1_b_2";
133					};
134					default_cfg1 {
135						pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
136						ste,config = <&in_pu>;
137					};
138				};
139
140				i2c1_sleep_mode: i2c_sleep {
141					sleep_cfg1 {
142						pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
143						ste,config = <&slpm_in_wkup_pdis>;
144					};
145				};
146			};
147
148			i2c2 {
149				i2c2_default_mode: i2c_default {
150					default_mux {
151						function = "i2c2";
152						groups = "i2c2_b_2";
153					};
154					default_cfg1 {
155						pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
156						ste,config = <&in_pu>;
157					};
158				};
159
160				i2c2_sleep_mode: i2c_sleep {
161					sleep_cfg1 {
162						pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
163						ste,config = <&slpm_in_wkup_pdis>;
164					};
165				};
166			};
167
168			i2c3 {
169				i2c3_default_mode: i2c_default {
170					default_mux {
171						function = "i2c3";
172						groups = "i2c3_c_2";
173					};
174					default_cfg1 {
175						pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
176						ste,config = <&in_pu>;
177					};
178				};
179
180				i2c3_sleep_mode: i2c_sleep {
181					sleep_cfg1 {
182						pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
183						ste,config = <&slpm_in_wkup_pdis>;
184					};
185				};
186			};
187
188			/*
189			 * Activating I2C4 will conflict with UART1 about the same pins so do not
190			 * enable I2C4 and UART1 at the same time.
191			 */
192			i2c4 {
193				i2c4_default_mode: i2c_default {
194					default_mux {
195						function = "i2c4";
196						groups = "i2c4_b_1";
197					};
198					default_cfg1 {
199						pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
200						ste,config = <&in_pu>;
201					};
202				};
203
204				i2c4_sleep_mode: i2c_sleep {
205					sleep_cfg1 {
206						pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
207						ste,config = <&slpm_in_wkup_pdis>;
208					};
209				};
210			};
211
212			/* Settings for all SPI default and sleep states */
213			spi2 {
214				spi2_default_mode: spi_default {
215					default_mux {
216						function = "spi2";
217						groups = "spi2_oc1_2";
218					};
219					default_cfg1 {
220						pins = "GPIO216_AG12"; /* FRM */
221						ste,config = <&gpio_out_hi>;
222					};
223					default_cfg2 {
224						pins = "GPIO218_AH11"; /* RXD */
225						ste,config = <&in_pd>;
226					};
227					default_cfg3 {
228						pins =
229						"GPIO215_AH13", /* TXD */
230						"GPIO217_AH12"; /* CLK */
231						ste,config = <&out_lo>;
232					};
233				};
234
235				spi2_idle_mode: spi_idle {
236					/*
237					 * The idle mode is basically sleep mode sans wakeups. Also
238					 * note that we have muxes the pins off the function here
239					 * as we do not state any muxing.
240					 */
241					idle_cfg1 {
242						pins = "GPIO218_AH11"; /* RXD */
243						ste,config = <&slpm_in_pdis>;
244					};
245					idle_cfg2 {
246						pins = "GPIO215_AH13"; /* TXD */
247						ste,config = <&slpm_out_lo_pdis>;
248					};
249					idle_cfg3 {
250						pins = "GPIO217_AH12"; /* CLK */
251						ste,config = <&slpm_pdis>;
252					};
253				};
254
255				spi2_sleep_mode: spi_sleep {
256					sleep_cfg1 {
257						pins =
258						"GPIO216_AG12", /* FRM */
259						"GPIO218_AH11"; /* RXD */
260						ste,config = <&slpm_in_wkup_pdis>;
261					};
262					sleep_cfg2 {
263						pins = "GPIO215_AH13"; /* TXD */
264						ste,config = <&slpm_out_lo_wkup_pdis>;
265					};
266					sleep_cfg3 {
267						pins = "GPIO217_AH12"; /* CLK */
268						ste,config = <&slpm_wkup_pdis>;
269					};
270				};
271			};
272
273			/* Settings for all MMC/SD/SDIO default and sleep states */
274			sdi0 {
275				/* This is the external SD card slot, 4 bits wide */
276				sdi0_default_mode: sdi0_default {
277					default_mux {
278						function = "mc0";
279						groups = "mc0_a_1";
280					};
281					default_cfg1 {
282						pins =
283						"GPIO18_AC2", /* CMDDIR */
284						"GPIO19_AC1", /* DAT0DIR */
285						"GPIO20_AB4"; /* DAT2DIR */
286						ste,config = <&out_hi>;
287					};
288					default_cfg2 {
289						pins = "GPIO22_AA3"; /* FBCLK */
290						ste,config = <&in_nopull>;
291					};
292					default_cfg3 {
293						pins = "GPIO23_AA4"; /* CLK */
294						ste,config = <&out_lo>;
295					};
296					default_cfg4 {
297						pins =
298						"GPIO24_AB2", /* CMD */
299						"GPIO25_Y4", /* DAT0 */
300						"GPIO26_Y2", /* DAT1 */
301						"GPIO27_AA2", /* DAT2 */
302						"GPIO28_AA1"; /* DAT3 */
303						ste,config = <&in_pu>;
304					};
305				};
306
307				sdi0_sleep_mode: sdi0_sleep {
308					sleep_cfg1 {
309						pins =
310						"GPIO18_AC2", /* CMDDIR */
311						"GPIO19_AC1", /* DAT0DIR */
312						"GPIO20_AB4"; /* DAT2DIR */
313						ste,config = <&slpm_out_hi_wkup_pdis>;
314					};
315					sleep_cfg2 {
316						pins =
317						"GPIO22_AA3", /* FBCLK */
318						"GPIO24_AB2", /* CMD */
319						"GPIO25_Y4", /* DAT0 */
320						"GPIO26_Y2", /* DAT1 */
321						"GPIO27_AA2", /* DAT2 */
322						"GPIO28_AA1"; /* DAT3 */
323						ste,config = <&slpm_in_wkup_pdis>;
324					};
325					sleep_cfg3 {
326						pins = "GPIO23_AA4"; /* CLK */
327						ste,config = <&slpm_out_lo_wkup_pdis>;
328					};
329				};
330			};
331
332			sdi1 {
333				/* This is the WLAN SDIO 4 bits wide */
334				sdi1_default_mode: sdi1_default {
335					default_mux {
336						function = "mc1";
337						groups = "mc1_a_1";
338					};
339					default_cfg1 {
340						pins = "GPIO208_AH16"; /* CLK */
341						ste,config = <&out_lo>;
342					};
343					default_cfg2 {
344						pins = "GPIO209_AG15"; /* FBCLK */
345						ste,config = <&in_nopull>;
346					};
347					default_cfg3 {
348						pins =
349						"GPIO210_AJ15", /* CMD */
350						"GPIO211_AG14", /* DAT0 */
351						"GPIO212_AF13", /* DAT1 */
352						"GPIO213_AG13", /* DAT2 */
353						"GPIO214_AH15"; /* DAT3 */
354						ste,config = <&in_pu>;
355					};
356				};
357
358				sdi1_sleep_mode: sdi1_sleep {
359					sleep_cfg1 {
360						pins = "GPIO208_AH16"; /* CLK */
361						ste,config = <&slpm_out_lo_wkup_pdis>;
362					};
363					sleep_cfg2 {
364						pins =
365						"GPIO209_AG15", /* FBCLK */
366						"GPIO210_AJ15", /* CMD */
367						"GPIO211_AG14", /* DAT0 */
368						"GPIO212_AF13", /* DAT1 */
369						"GPIO213_AG13", /* DAT2 */
370						"GPIO214_AH15"; /* DAT3 */
371						ste,config = <&slpm_in_wkup_pdis>;
372					};
373				};
374			};
375
376			sdi2 {
377				/* This is the eMMC 8 bits wide, usually PoP eMMC */
378				sdi2_default_mode: sdi2_default {
379					default_mux {
380						function = "mc2";
381						groups = "mc2_a_1";
382					};
383					default_cfg1 {
384						pins = "GPIO128_A5"; /* CLK */
385						ste,config = <&out_lo>;
386					};
387					default_cfg2 {
388						pins = "GPIO130_C8"; /* FBCLK */
389						ste,config = <&in_nopull>;
390					};
391					default_cfg3 {
392						pins =
393						"GPIO129_B4", /* CMD */
394						"GPIO131_A12", /* DAT0 */
395						"GPIO132_C10", /* DAT1 */
396						"GPIO133_B10", /* DAT2 */
397						"GPIO134_B9", /* DAT3 */
398						"GPIO135_A9", /* DAT4 */
399						"GPIO136_C7", /* DAT5 */
400						"GPIO137_A7", /* DAT6 */
401						"GPIO138_C5"; /* DAT7 */
402						ste,config = <&in_pu>;
403					};
404				};
405
406				sdi2_sleep_mode: sdi2_sleep {
407					sleep_cfg1 {
408						pins = "GPIO128_A5"; /* CLK */
409						ste,config = <&out_lo_wkup_pdis>;
410					};
411					sleep_cfg2 {
412						pins =
413						"GPIO130_C8", /* FBCLK */
414						"GPIO129_B4"; /* CMD */
415						ste,config = <&in_wkup_pdis_en>;
416					};
417					sleep_cfg3 {
418						pins =
419						"GPIO131_A12", /* DAT0 */
420						"GPIO132_C10", /* DAT1 */
421						"GPIO133_B10", /* DAT2 */
422						"GPIO134_B9", /* DAT3 */
423						"GPIO135_A9", /* DAT4 */
424						"GPIO136_C7", /* DAT5 */
425						"GPIO137_A7", /* DAT6 */
426						"GPIO138_C5"; /* DAT7 */
427						ste,config = <&in_wkup_pdis>;
428					};
429				};
430			};
431
432			sdi4 {
433				/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
434				sdi4_default_mode: sdi4_default {
435					default_mux {
436						function = "mc4";
437						groups = "mc4_a_1";
438					};
439					default_cfg1 {
440						pins = "GPIO203_AE23"; /* CLK */
441						ste,config = <&out_lo>;
442					};
443					default_cfg2 {
444						pins = "GPIO202_AF25"; /* FBCLK */
445						ste,config = <&in_nopull>;
446					};
447					default_cfg3 {
448						pins =
449						"GPIO201_AF24", /* CMD */
450						"GPIO200_AH26", /* DAT0 */
451						"GPIO199_AH23", /* DAT1 */
452						"GPIO198_AG25", /* DAT2 */
453						"GPIO197_AH24", /* DAT3 */
454						"GPIO207_AJ23", /* DAT4 */
455						"GPIO206_AG24", /* DAT5 */
456						"GPIO205_AG23", /* DAT6 */
457						"GPIO204_AF23"; /* DAT7 */
458						ste,config = <&in_pu>;
459					};
460				};
461
462				sdi4_sleep_mode: sdi4_sleep {
463					sleep_cfg1 {
464						pins = "GPIO203_AE23"; /* CLK */
465						ste,config = <&out_lo_wkup_pdis>;
466					};
467					sleep_cfg2 {
468						pins =
469						"GPIO202_AF25", /* FBCLK */
470						"GPIO201_AF24", /* CMD */
471						"GPIO200_AH26", /* DAT0 */
472						"GPIO199_AH23", /* DAT1 */
473						"GPIO198_AG25", /* DAT2 */
474						"GPIO197_AH24", /* DAT3 */
475						"GPIO207_AJ23", /* DAT4 */
476						"GPIO206_AG24", /* DAT5 */
477						"GPIO205_AG23", /* DAT6 */
478						"GPIO204_AF23"; /* DAT7 */
479						ste,config = <&slpm_in_wkup_pdis>;
480					};
481				};
482			};
483
484			/*
485			 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
486			 * cannot be muxed onto any pins.
487			 */
488			msp0 {
489				msp0_default_mode: msp0_default {
490					default_msp0_mux {
491						function = "msp0";
492						groups = "msp0txrx_a_1", "msp0tfstck_a_1";
493					};
494					default_msp0_cfg {
495						pins =
496						"GPIO12_AC4", /* TXD */
497						"GPIO15_AC3", /* RXD */
498						"GPIO13_AF3", /* TFS */
499						"GPIO14_AE3"; /* TCK */
500						ste,config = <&in_nopull>;
501					};
502				};
503			};
504
505			msp1 {
506				msp1_default_mode: msp1_default {
507					default_mux {
508						function = "msp1";
509						groups = "msp1txrx_a_1", "msp1_a_1";
510					};
511					default_cfg1 {
512						pins = "GPIO33_AF2";
513						ste,config = <&out_lo>;
514					};
515					default_cfg2 {
516						pins =
517						"GPIO34_AE1",
518						"GPIO35_AE2",
519						"GPIO36_AG2";
520						ste,config = <&in_nopull>;
521					};
522
523				};
524			};
525
526			msp2 {
527				msp2_default_mode: msp2_default {
528					/* MSP2 usually used for HDMI audio */
529					default_mux {
530						function = "msp2";
531						groups = "msp2_a_1";
532					};
533					default_cfg1 {
534						pins =
535						"GPIO193_AH27", /* TXD */
536						"GPIO194_AF27", /* TCK */
537						"GPIO195_AG28"; /* TFS */
538						ste,config = <&in_pd>;
539					};
540					default_cfg2 {
541						pins = "GPIO196_AG26"; /* RXD */
542						ste,config = <&out_lo>;
543					};
544				};
545			};
546
547
548			musb {
549				musb_default_mode: musb_default {
550					default_mux {
551						function = "usb";
552						groups = "usb_a_1";
553					};
554					default_cfg1 {
555						pins =
556						"GPIO256_AF28", /* NXT */
557						"GPIO258_AD29", /* XCLK */
558						"GPIO259_AC29", /* DIR */
559						"GPIO260_AD28", /* DAT7 */
560						"GPIO261_AD26", /* DAT6 */
561						"GPIO262_AE26", /* DAT5 */
562						"GPIO263_AG29", /* DAT4 */
563						"GPIO264_AE27", /* DAT3 */
564						"GPIO265_AD27", /* DAT2 */
565						"GPIO266_AC28", /* DAT1 */
566						"GPIO267_AC27"; /* DAT0 */
567						ste,config = <&in_nopull>;
568					};
569					default_cfg2 {
570						pins = "GPIO257_AE29"; /* STP */
571						ste,config = <&out_hi>;
572					};
573				};
574
575				musb_sleep_mode: musb_sleep {
576					sleep_cfg1 {
577						pins =
578						"GPIO256_AF28", /* NXT */
579						"GPIO258_AD29", /* XCLK */
580						"GPIO259_AC29"; /* DIR */
581						ste,config = <&slpm_wkup_pdis_en>;
582					};
583					sleep_cfg2 {
584						pins = "GPIO257_AE29"; /* STP */
585						ste,config = <&slpm_out_hi_wkup_pdis>;
586					};
587					sleep_cfg3 {
588						pins =
589						"GPIO260_AD28", /* DAT7 */
590						"GPIO261_AD26", /* DAT6 */
591						"GPIO262_AE26", /* DAT5 */
592						"GPIO263_AG29", /* DAT4 */
593						"GPIO264_AE27", /* DAT3 */
594						"GPIO265_AD27", /* DAT2 */
595						"GPIO266_AC28", /* DAT1 */
596						"GPIO267_AC27"; /* DAT0 */
597						ste,config = <&slpm_in_wkup_pdis_en>;
598					};
599				};
600			};
601
602			mcde {
603				lcd_default_mode: lcd_default {
604					default_mux1 {
605						/* Mux in VSI0 and all the data lines */
606						function = "lcd";
607						groups =
608						"lcdvsi0_a_1", /* VSI0 for LCD */
609						"lcd_d0_d7_a_1", /* Data lines */
610						"lcdvsi1_a_1"; /* VSI1 for HDMI */
611					};
612					default_mux2 {
613						function = "lcda";
614						groups =
615						"lcdaclk_b_1"; /* Clock line for TV-out */
616					};
617					default_cfg1 {
618						pins =
619						"GPIO68_E1", /* VSI0 */
620						"GPIO69_E2"; /* VSI1 */
621						ste,config = <&in_pu>;
622					};
623				};
624				lcd_sleep_mode: lcd_sleep {
625					sleep_cfg1 {
626						pins = "GPIO69_E2"; /* VSI1 */
627						ste,config = <&slpm_in_wkup_pdis>;
628					};
629				};
630			};
631
632			ske {
633				/* SKE keys on position 2 in an 8x8 matrix */
634				ske_kpa2_default_mode: ske_kpa2_default {
635					default_mux {
636						function = "kp";
637						groups = "kp_a_2";
638					};
639					default_cfg1 {
640						pins =
641						"GPIO153_B17", /* I7 */
642						"GPIO154_C16", /* I6 */
643						"GPIO155_C19", /* I5 */
644						"GPIO156_C17", /* I4 */
645						"GPIO161_D21", /* I3 */
646						"GPIO162_D20", /* I2 */
647						"GPIO163_C20", /* I1 */
648						"GPIO164_B21"; /* I0 */
649						ste,config = <&in_pd>;
650					};
651					default_cfg2 {
652						pins =
653						"GPIO157_A18", /* O7 */
654						"GPIO158_C18", /* O6 */
655						"GPIO159_B19", /* O5 */
656						"GPIO160_B20", /* O4 */
657						"GPIO165_C21", /* O3 */
658						"GPIO166_A22", /* O2 */
659						"GPIO167_B24", /* O1 */
660						"GPIO168_C22"; /* O0 */
661						ste,config = <&out_lo>;
662					};
663				};
664				ske_kpa2_sleep_mode: ske_kpa2_sleep {
665					sleep_cfg1 {
666						pins =
667						"GPIO153_B17", /* I7 */
668						"GPIO154_C16", /* I6 */
669						"GPIO155_C19", /* I5 */
670						"GPIO156_C17", /* I4 */
671						"GPIO161_D21", /* I3 */
672						"GPIO162_D20", /* I2 */
673						"GPIO163_C20", /* I1 */
674						"GPIO164_B21"; /* I0 */
675						ste,config = <&slpm_in_pu_wkup_pdis_en>;
676					};
677					sleep_cfg2 {
678						pins =
679						"GPIO157_A18", /* O7 */
680						"GPIO158_C18", /* O6 */
681						"GPIO159_B19", /* O5 */
682						"GPIO160_B20", /* O4 */
683						"GPIO165_C21", /* O3 */
684						"GPIO166_A22", /* O2 */
685						"GPIO167_B24", /* O1 */
686						"GPIO168_C22"; /* O0 */
687						ste,config = <&slpm_out_lo_pdis>;
688					};
689				};
690				/*
691				 * SKE keys on position 1 and "other C1" combi giving
692				 * six rows of six keys.
693				 */
694				ske_kpaoc1_default_mode: ske_kpaoc1_default {
695					default_mux {
696						function = "kp";
697						groups = "kp_a_1", "kp_oc1_1";
698					};
699					default_cfg1 {
700						pins =
701						"GPIO91_B6", /* KP_O0 */
702						"GPIO90_A3", /* KP_O1 */
703						"GPIO87_B3", /* KP_O2 */
704						"GPIO86_C6", /* KP_O3 */
705						"GPIO96_D8", /* KP_O6 */
706						"GPIO94_D7"; /* KP_O7 */
707						ste,config = <&out_lo>;
708					};
709					default_cfg2 {
710						pins =
711						"GPIO93_B7", /* KP_I0 */
712						"GPIO92_D6", /* KP_I1 */
713						"GPIO89_E6", /* KP_I2 */
714						"GPIO88_C4", /* KP_I3 */
715						"GPIO97_D9", /* KP_I6 */
716						"GPIO95_E8"; /* KP_I7 */
717						ste,config = <&in_pu>;
718					};
719				};
720			};
721
722			wlan {
723				wlan_default_mode: wlan_default {
724					/*
725					 * Activate this mode with the WLAN chip.
726					 * These are plain GPIO pins used by WLAN
727					 */
728					default_cfg1 {
729						pins =
730						"GPIO226_AF8", /* WLAN_PMU_EN */
731						"GPIO85_D5"; /* WLAN_ENA */
732						ste,config = <&gpio_out_lo>;
733					};
734					default_cfg2 {
735						pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
736						ste,config = <&gpio_in_pu>;
737					};
738				};
739			};
740		};
741	};
742};
743