1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 */
5
6 #include <linux/types.h>
7 #include <linux/init.h>
8
9 #include <linux/platform_device.h>
10 #include <linux/mtd/physmap.h>
11 #include <linux/mtd/plat-ram.h>
12 #include <linux/memory.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/machine.h>
15 #include <linux/smc911x.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/property.h>
20 #include <linux/usb/otg.h>
21 #include <linux/usb/ulpi.h>
22
23 #include <asm/mach-types.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach/time.h>
26 #include <asm/mach/map.h>
27
28 #include "common.h"
29 #include "devices-imx35.h"
30 #include "ehci.h"
31 #include "hardware.h"
32 #include "iomux-mx35.h"
33 #include "ulpi.h"
34
35 static const struct fb_videomode fb_modedb[] = {
36 {
37 /* 240x320 @ 60 Hz */
38 .name = "Sharp-LQ035Q7",
39 .refresh = 60,
40 .xres = 240,
41 .yres = 320,
42 .pixclock = 185925,
43 .left_margin = 9,
44 .right_margin = 16,
45 .upper_margin = 7,
46 .lower_margin = 9,
47 .hsync_len = 1,
48 .vsync_len = 1,
49 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
50 .vmode = FB_VMODE_NONINTERLACED,
51 .flag = 0,
52 }, {
53 /* 240x320 @ 60 Hz */
54 .name = "TX090",
55 .refresh = 60,
56 .xres = 240,
57 .yres = 320,
58 .pixclock = 38255,
59 .left_margin = 144,
60 .right_margin = 0,
61 .upper_margin = 7,
62 .lower_margin = 40,
63 .hsync_len = 96,
64 .vsync_len = 1,
65 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
66 .vmode = FB_VMODE_NONINTERLACED,
67 .flag = 0,
68 },
69 };
70
71 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
72 .name = "Sharp-LQ035Q7",
73 .mode = fb_modedb,
74 .num_modes = ARRAY_SIZE(fb_modedb),
75 };
76
77 static struct physmap_flash_data pcm043_flash_data = {
78 .width = 2,
79 };
80
81 static struct resource pcm043_flash_resource = {
82 .start = 0xa0000000,
83 .end = 0xa1ffffff,
84 .flags = IORESOURCE_MEM,
85 };
86
87 static struct platform_device pcm043_flash = {
88 .name = "physmap-flash",
89 .id = 0,
90 .dev = {
91 .platform_data = &pcm043_flash_data,
92 },
93 .resource = &pcm043_flash_resource,
94 .num_resources = 1,
95 };
96
97 static const struct imxuart_platform_data uart_pdata __initconst = {
98 .flags = IMXUART_HAVE_RTSCTS,
99 };
100
101 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
102 .bitrate = 50000,
103 };
104
105 static const struct property_entry board_eeprom_properties[] = {
106 PROPERTY_ENTRY_U32("pagesize", 32),
107 { }
108 };
109
110 static struct i2c_board_info pcm043_i2c_devices[] = {
111 {
112 I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
113 .properties = board_eeprom_properties,
114 }, {
115 I2C_BOARD_INFO("pcf8563", 0x51),
116 },
117 };
118
119 static struct platform_device *devices[] __initdata = {
120 &pcm043_flash,
121 };
122
123 static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
124 /* UART1 */
125 MX35_PAD_CTS1__UART1_CTS,
126 MX35_PAD_RTS1__UART1_RTS,
127 MX35_PAD_TXD1__UART1_TXD_MUX,
128 MX35_PAD_RXD1__UART1_RXD_MUX,
129 /* UART2 */
130 MX35_PAD_CTS2__UART2_CTS,
131 MX35_PAD_RTS2__UART2_RTS,
132 MX35_PAD_TXD2__UART2_TXD_MUX,
133 MX35_PAD_RXD2__UART2_RXD_MUX,
134 /* FEC */
135 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
136 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
137 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
138 MX35_PAD_FEC_COL__FEC_COL,
139 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
140 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
141 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
142 MX35_PAD_FEC_MDC__FEC_MDC,
143 MX35_PAD_FEC_MDIO__FEC_MDIO,
144 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
145 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
146 MX35_PAD_FEC_CRS__FEC_CRS,
147 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
148 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
149 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
150 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
151 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
152 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
153 /* I2C1 */
154 MX35_PAD_I2C1_CLK__I2C1_SCL,
155 MX35_PAD_I2C1_DAT__I2C1_SDA,
156 /* Display */
157 MX35_PAD_LD0__IPU_DISPB_DAT_0,
158 MX35_PAD_LD1__IPU_DISPB_DAT_1,
159 MX35_PAD_LD2__IPU_DISPB_DAT_2,
160 MX35_PAD_LD3__IPU_DISPB_DAT_3,
161 MX35_PAD_LD4__IPU_DISPB_DAT_4,
162 MX35_PAD_LD5__IPU_DISPB_DAT_5,
163 MX35_PAD_LD6__IPU_DISPB_DAT_6,
164 MX35_PAD_LD7__IPU_DISPB_DAT_7,
165 MX35_PAD_LD8__IPU_DISPB_DAT_8,
166 MX35_PAD_LD9__IPU_DISPB_DAT_9,
167 MX35_PAD_LD10__IPU_DISPB_DAT_10,
168 MX35_PAD_LD11__IPU_DISPB_DAT_11,
169 MX35_PAD_LD12__IPU_DISPB_DAT_12,
170 MX35_PAD_LD13__IPU_DISPB_DAT_13,
171 MX35_PAD_LD14__IPU_DISPB_DAT_14,
172 MX35_PAD_LD15__IPU_DISPB_DAT_15,
173 MX35_PAD_LD16__IPU_DISPB_DAT_16,
174 MX35_PAD_LD17__IPU_DISPB_DAT_17,
175 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
176 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
177 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
178 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
179 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
180 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
181 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
182 /* gpio */
183 MX35_PAD_ATA_CS0__GPIO2_6,
184 /* USB host */
185 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
186 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
187 /* SSI */
188 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
189 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
190 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
191 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
192 /* CAN2 */
193 MX35_PAD_TX5_RX0__CAN2_TXCAN,
194 MX35_PAD_TX4_RX1__CAN2_RXCAN,
195 /* esdhc */
196 MX35_PAD_SD1_CMD__ESDHC1_CMD,
197 MX35_PAD_SD1_CLK__ESDHC1_CLK,
198 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
199 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
200 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
201 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
202 MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
203 MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
204 };
205
206 #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
207 #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
208 #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
209
pcm043_ac97_warm_reset(struct snd_ac97 * ac97)210 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
211 {
212 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
213 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
214 int ret;
215
216 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
217 if (ret) {
218 printk("failed to get GPIO_TXFS: %d\n", ret);
219 return;
220 }
221
222 mxc_iomux_v3_setup_pad(txfs_gpio);
223
224 /* warm reset */
225 gpio_direction_output(AC97_GPIO_TXFS, 1);
226 udelay(2);
227 gpio_set_value(AC97_GPIO_TXFS, 0);
228
229 gpio_free(AC97_GPIO_TXFS);
230 mxc_iomux_v3_setup_pad(txfs);
231 }
232
pcm043_ac97_cold_reset(struct snd_ac97 * ac97)233 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
234 {
235 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
236 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
237 iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
238 iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
239 iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
240 int ret;
241
242 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
243 if (ret)
244 goto err1;
245
246 ret = gpio_request(AC97_GPIO_TXD, "SSI");
247 if (ret)
248 goto err2;
249
250 ret = gpio_request(AC97_GPIO_RESET, "SSI");
251 if (ret)
252 goto err3;
253
254 mxc_iomux_v3_setup_pad(txfs_gpio);
255 mxc_iomux_v3_setup_pad(txd_gpio);
256 mxc_iomux_v3_setup_pad(reset_gpio);
257
258 gpio_direction_output(AC97_GPIO_TXFS, 0);
259 gpio_direction_output(AC97_GPIO_TXD, 0);
260
261 /* cold reset */
262 gpio_direction_output(AC97_GPIO_RESET, 0);
263 udelay(10);
264 gpio_direction_output(AC97_GPIO_RESET, 1);
265
266 mxc_iomux_v3_setup_pad(txd);
267 mxc_iomux_v3_setup_pad(txfs);
268
269 gpio_free(AC97_GPIO_RESET);
270 err3:
271 gpio_free(AC97_GPIO_TXD);
272 err2:
273 gpio_free(AC97_GPIO_TXFS);
274 err1:
275 if (ret)
276 printk("%s failed with %d\n", __func__, ret);
277 mdelay(1);
278 }
279
280 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
281 .ac97_reset = pcm043_ac97_cold_reset,
282 .ac97_warm_reset = pcm043_ac97_warm_reset,
283 .flags = IMX_SSI_USE_AC97,
284 };
285
286 static const struct mxc_nand_platform_data
287 pcm037_nand_board_info __initconst = {
288 .width = 1,
289 .hw_ecc = 1,
290 };
291
pcm043_otg_init(struct platform_device * pdev)292 static int pcm043_otg_init(struct platform_device *pdev)
293 {
294 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
295 }
296
297 static struct mxc_usbh_platform_data otg_pdata __initdata = {
298 .init = pcm043_otg_init,
299 .portsc = MXC_EHCI_MODE_UTMI,
300 };
301
pcm043_usbh1_init(struct platform_device * pdev)302 static int pcm043_usbh1_init(struct platform_device *pdev)
303 {
304 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
305 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
306 }
307
308 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
309 .init = pcm043_usbh1_init,
310 .portsc = MXC_EHCI_MODE_SERIAL,
311 };
312
313 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
314 .operating_mode = FSL_USB2_DR_DEVICE,
315 .phy_mode = FSL_USB2_PHY_UTMI,
316 };
317
318 static bool otg_mode_host __initdata;
319
pcm043_otg_mode(char * options)320 static int __init pcm043_otg_mode(char *options)
321 {
322 if (!strcmp(options, "host"))
323 otg_mode_host = true;
324 else if (!strcmp(options, "device"))
325 otg_mode_host = false;
326 else
327 pr_info("otg_mode neither \"host\" nor \"device\". "
328 "Defaulting to device\n");
329 return 1;
330 }
331 __setup("otg_mode=", pcm043_otg_mode);
332
333 static struct esdhc_platform_data sd1_pdata = {
334 .wp_type = ESDHC_WP_GPIO,
335 .cd_type = ESDHC_CD_GPIO,
336 };
337
338 static struct gpiod_lookup_table sd1_gpio_table = {
339 .dev_id = "sdhci-esdhc-imx35.0",
340 .table = {
341 /* Card detect: bank 2 offset 24 */
342 GPIO_LOOKUP("imx35-gpio.2", 24, "cd", GPIO_ACTIVE_LOW),
343 /* Write protect: bank 2 offset 23 */
344 GPIO_LOOKUP("imx35-gpio.2", 23, "wp", GPIO_ACTIVE_LOW),
345 { },
346 },
347 };
348
349 /*
350 * Board specific initialization.
351 */
pcm043_init(void)352 static void __init pcm043_init(void)
353 {
354 imx35_soc_init();
355
356 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
357
358 imx35_add_fec(NULL);
359 platform_add_devices(devices, ARRAY_SIZE(devices));
360 imx35_add_imx2_wdt();
361
362 imx35_add_imx_uart0(&uart_pdata);
363 imx35_add_mxc_nand(&pcm037_nand_board_info);
364
365 imx35_add_imx_uart1(&uart_pdata);
366
367 i2c_register_board_info(0, pcm043_i2c_devices,
368 ARRAY_SIZE(pcm043_i2c_devices));
369
370 imx35_add_imx_i2c0(&pcm043_i2c0_data);
371
372 imx35_add_ipu_core();
373 imx35_add_mx3_sdc_fb(&mx3fb_pdata);
374
375 if (otg_mode_host) {
376 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
377 ULPI_OTG_DRVVBUS_EXT);
378 if (otg_pdata.otg)
379 imx35_add_mxc_ehci_otg(&otg_pdata);
380 }
381 imx35_add_mxc_ehci_hs(&usbh1_pdata);
382
383 if (!otg_mode_host)
384 imx35_add_fsl_usb2_udc(&otg_device_pdata);
385
386 imx35_add_flexcan1();
387 }
388
pcm043_late_init(void)389 static void __init pcm043_late_init(void)
390 {
391 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
392
393 gpiod_add_lookup_table(&sd1_gpio_table);
394 imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
395 }
396
pcm043_timer_init(void)397 static void __init pcm043_timer_init(void)
398 {
399 mx35_clocks_init();
400 }
401
402 MACHINE_START(PCM043, "Phytec Phycore pcm043")
403 /* Maintainer: Pengutronix */
404 .atag_offset = 0x100,
405 .map_io = mx35_map_io,
406 .init_early = imx35_init_early,
407 .init_irq = mx35_init_irq,
408 .init_time = pcm043_timer_init,
409 .init_machine = pcm043_init,
410 .init_late = pcm043_late_init,
411 .restart = mxc_restart,
412 MACHINE_END
413