1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * opp2430_data.c - old-style "OPP" table for OMAP2430 4 * 5 * Copyright (C) 2005-2009 Texas Instruments, Inc. 6 * Copyright (C) 2004-2009 Nokia Corporation 7 * 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * 10 * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 11 * These configurations are characterized by voltage and speed for clocks. 12 * The device is only validated for certain combinations. One way to express 13 * these combinations is via the 'ratios' which the clocks operate with 14 * respect to each other. These ratio sets are for a given voltage/DPLL 15 * setting. All configurations can be described by a DPLL setting and a ratio. 16 * 17 * 2430 differs from 2420 in that there are no more phase synchronizers used. 18 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs 19 * 2430 (iva2.1, NOdsp, mdm) 20 * 21 * XXX Missing voltage data. 22 * XXX Missing 19.2MHz sys_clk rate sets. 23 * 24 * THe format described in this file is deprecated. Once a reasonable 25 * OPP API exists, the data in this file should be converted to use it. 26 * 27 * This is technically part of the OMAP2xxx clock code. 28 */ 29 30 #include <linux/kernel.h> 31 32 #include "opp2xxx.h" 33 #include "sdrc.h" 34 #include "clock.h" 35 36 /* 37 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated. 38 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, 39 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, 40 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM 41 * 42 * Filling in table based on 2430-SDPs variants available. There are 43 * quite a few more rate combinations which could be defined. 44 * 45 * When multiple values are defined the start up will try and choose 46 * the fastest one. If a 'fast' value is defined, then automatically, 47 * the /2 one should be included as it can be used. Generally having 48 * more than one fast set does not make sense, as static timings need 49 * to be changed to change the set. The exception is the bypass 50 * setting which is available for low power bypass. 51 * 52 * Note: This table needs to be sorted, fastest to slowest. 53 */ 54 const struct prcm_config omap2430_rate_table[] = { 55 /* PRCM #4 - ratio2 (ES2.1) - FAST */ 56 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ 57 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 58 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 59 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, 60 SDRC_RFR_CTRL_133MHz, 61 RATE_IN_243X}, 62 63 /* PRCM #2 - ratio1 (ES2) - FAST */ 64 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 65 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 66 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 67 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 68 SDRC_RFR_CTRL_165MHz, 69 RATE_IN_243X}, 70 71 /* PRCM #5a - ratio1 - FAST */ 72 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 73 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 74 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 75 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 76 SDRC_RFR_CTRL_133MHz, 77 RATE_IN_243X}, 78 79 /* PRCM #5b - ratio1 - FAST */ 80 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 81 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 82 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 83 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 84 SDRC_RFR_CTRL_100MHz, 85 RATE_IN_243X}, 86 87 /* PRCM #4 - ratio1 (ES2.1) - SLOW */ 88 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 89 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 90 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 91 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, 92 SDRC_RFR_CTRL_133MHz, 93 RATE_IN_243X}, 94 95 /* PRCM #2 - ratio1 (ES2) - SLOW */ 96 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ 97 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 98 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 99 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 100 SDRC_RFR_CTRL_165MHz, 101 RATE_IN_243X}, 102 103 /* PRCM #5a - ratio1 - SLOW */ 104 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 105 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 106 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 107 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 108 SDRC_RFR_CTRL_133MHz, 109 RATE_IN_243X}, 110 111 /* PRCM #5b - ratio1 - SLOW*/ 112 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ 113 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 114 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 115 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 116 SDRC_RFR_CTRL_100MHz, 117 RATE_IN_243X}, 118 119 /* PRCM-boot/bypass */ 120 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */ 121 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 122 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, 123 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 124 SDRC_RFR_CTRL_BYPASS, 125 RATE_IN_243X}, 126 127 /* PRCM-boot/bypass */ 128 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */ 129 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 130 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, 131 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 132 SDRC_RFR_CTRL_BYPASS, 133 RATE_IN_243X}, 134 135 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 136 }; 137