1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2/* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h6-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun8i-de2.h> 10#include <dt-bindings/clock/sun8i-tcon-top.h> 11#include <dt-bindings/reset/sun50i-h6-ccu.h> 12#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 13#include <dt-bindings/reset/sun8i-de2.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@1 { 32 compatible = "arm,cortex-a53"; 33 device_type = "cpu"; 34 reg = <1>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <2>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <3>; 49 enable-method = "psci"; 50 }; 51 }; 52 53 de: display-engine { 54 compatible = "allwinner,sun50i-h6-display-engine"; 55 allwinner,pipelines = <&mixer0>; 56 status = "disabled"; 57 }; 58 59 osc24M: osc24M_clk { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <24000000>; 63 clock-output-names = "osc24M"; 64 }; 65 66 ext_osc32k: ext_osc32k_clk { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32768>; 70 clock-output-names = "ext_osc32k"; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 80 }; 81 82 psci { 83 compatible = "arm,psci-0.2"; 84 method = "smc"; 85 }; 86 87 timer { 88 compatible = "arm,armv8-timer"; 89 interrupts = <GIC_PPI 13 90 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 91 <GIC_PPI 14 92 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 93 <GIC_PPI 11 94 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 10 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges; 104 105 bus@1000000 { 106 compatible = "allwinner,sun50i-h6-de3", 107 "allwinner,sun50i-a64-de2"; 108 reg = <0x1000000 0x400000>; 109 allwinner,sram = <&de2_sram 1>; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0 0x1000000 0x400000>; 113 114 display_clocks: clock@0 { 115 compatible = "allwinner,sun50i-h6-de3-clk"; 116 reg = <0x0 0x10000>; 117 clocks = <&ccu CLK_DE>, 118 <&ccu CLK_BUS_DE>; 119 clock-names = "mod", 120 "bus"; 121 resets = <&ccu RST_BUS_DE>; 122 #clock-cells = <1>; 123 #reset-cells = <1>; 124 }; 125 126 mixer0: mixer@100000 { 127 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 128 reg = <0x100000 0x100000>; 129 clocks = <&display_clocks CLK_BUS_MIXER0>, 130 <&display_clocks CLK_MIXER0>; 131 clock-names = "bus", 132 "mod"; 133 resets = <&display_clocks RST_MIXER0>; 134 135 ports { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 mixer0_out: port@1 { 140 reg = <1>; 141 142 mixer0_out_tcon_top_mixer0: endpoint { 143 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 144 }; 145 }; 146 }; 147 }; 148 }; 149 150 video-codec@1c0e000 { 151 compatible = "allwinner,sun50i-h6-video-engine"; 152 reg = <0x01c0e000 0x2000>; 153 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 154 <&ccu CLK_MBUS_VE>; 155 clock-names = "ahb", "mod", "ram"; 156 resets = <&ccu RST_BUS_VE>; 157 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 158 allwinner,sram = <&ve_sram 1>; 159 }; 160 161 syscon: syscon@3000000 { 162 compatible = "allwinner,sun50i-h6-system-control", 163 "allwinner,sun50i-a64-system-control"; 164 reg = <0x03000000 0x1000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges; 168 169 sram_c: sram@28000 { 170 compatible = "mmio-sram"; 171 reg = <0x00028000 0x1e000>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges = <0 0x00028000 0x1e000>; 175 176 de2_sram: sram-section@0 { 177 compatible = "allwinner,sun50i-h6-sram-c", 178 "allwinner,sun50i-a64-sram-c"; 179 reg = <0x0000 0x1e000>; 180 }; 181 }; 182 183 sram_c1: sram@1a00000 { 184 compatible = "mmio-sram"; 185 reg = <0x01a00000 0x200000>; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 ranges = <0 0x01a00000 0x200000>; 189 190 ve_sram: sram-section@0 { 191 compatible = "allwinner,sun50i-h6-sram-c1", 192 "allwinner,sun4i-a10-sram-c1"; 193 reg = <0x000000 0x200000>; 194 }; 195 }; 196 }; 197 198 ccu: clock@3001000 { 199 compatible = "allwinner,sun50i-h6-ccu"; 200 reg = <0x03001000 0x1000>; 201 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 202 clock-names = "hosc", "losc", "iosc"; 203 #clock-cells = <1>; 204 #reset-cells = <1>; 205 }; 206 207 dma: dma-controller@3002000 { 208 compatible = "allwinner,sun50i-h6-dma"; 209 reg = <0x03002000 0x1000>; 210 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 212 clock-names = "bus", "mbus"; 213 dma-channels = <16>; 214 dma-requests = <46>; 215 resets = <&ccu RST_BUS_DMA>; 216 #dma-cells = <1>; 217 }; 218 219 sid: efuse@3006000 { 220 compatible = "allwinner,sun50i-h6-sid"; 221 reg = <0x03006000 0x400>; 222 }; 223 224 watchdog: watchdog@30090a0 { 225 compatible = "allwinner,sun50i-h6-wdt", 226 "allwinner,sun6i-a31-wdt"; 227 reg = <0x030090a0 0x20>; 228 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&osc24M>; 230 /* Broken on some H6 boards */ 231 status = "disabled"; 232 }; 233 234 pio: pinctrl@300b000 { 235 compatible = "allwinner,sun50i-h6-pinctrl"; 236 reg = <0x0300b000 0x400>; 237 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 242 clock-names = "apb", "hosc", "losc"; 243 gpio-controller; 244 #gpio-cells = <3>; 245 interrupt-controller; 246 #interrupt-cells = <3>; 247 248 ext_rgmii_pins: rgmii-pins { 249 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 250 "PD5", "PD7", "PD8", "PD9", "PD10", 251 "PD11", "PD12", "PD13", "PD19", "PD20"; 252 function = "emac"; 253 drive-strength = <40>; 254 }; 255 256 hdmi_pins: hdmi-pins { 257 pins = "PH8", "PH9", "PH10"; 258 function = "hdmi"; 259 }; 260 261 i2c0_pins: i2c0-pins { 262 pins = "PD25", "PD26"; 263 function = "i2c0"; 264 }; 265 266 i2c1_pins: i2c1-pins { 267 pins = "PH5", "PH6"; 268 function = "i2c1"; 269 }; 270 271 i2c2_pins: i2c2-pins { 272 pins = "PD23", "PD24"; 273 function = "i2c2"; 274 }; 275 276 mmc0_pins: mmc0-pins { 277 pins = "PF0", "PF1", "PF2", "PF3", 278 "PF4", "PF5"; 279 function = "mmc0"; 280 drive-strength = <30>; 281 bias-pull-up; 282 }; 283 284 /omit-if-no-ref/ 285 mmc1_pins: mmc1-pins { 286 pins = "PG0", "PG1", "PG2", "PG3", 287 "PG4", "PG5"; 288 function = "mmc1"; 289 drive-strength = <30>; 290 bias-pull-up; 291 }; 292 293 mmc2_pins: mmc2-pins { 294 pins = "PC1", "PC4", "PC5", "PC6", 295 "PC7", "PC8", "PC9", "PC10", 296 "PC11", "PC12", "PC13", "PC14"; 297 function = "mmc2"; 298 drive-strength = <30>; 299 bias-pull-up; 300 }; 301 302 spdif_tx_pin: spdif-tx-pin { 303 pins = "PH7"; 304 function = "spdif"; 305 }; 306 307 uart0_ph_pins: uart0-ph-pins { 308 pins = "PH0", "PH1"; 309 function = "uart0"; 310 }; 311 }; 312 313 gic: interrupt-controller@3021000 { 314 compatible = "arm,gic-400"; 315 reg = <0x03021000 0x1000>, 316 <0x03022000 0x2000>, 317 <0x03024000 0x2000>, 318 <0x03026000 0x2000>; 319 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 320 interrupt-controller; 321 #interrupt-cells = <3>; 322 }; 323 324 mmc0: mmc@4020000 { 325 compatible = "allwinner,sun50i-h6-mmc", 326 "allwinner,sun50i-a64-mmc"; 327 reg = <0x04020000 0x1000>; 328 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 329 clock-names = "ahb", "mmc"; 330 resets = <&ccu RST_BUS_MMC0>; 331 reset-names = "ahb"; 332 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&mmc0_pins>; 335 max-frequency = <150000000>; 336 status = "disabled"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 }; 340 341 mmc1: mmc@4021000 { 342 compatible = "allwinner,sun50i-h6-mmc", 343 "allwinner,sun50i-a64-mmc"; 344 reg = <0x04021000 0x1000>; 345 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 346 clock-names = "ahb", "mmc"; 347 resets = <&ccu RST_BUS_MMC1>; 348 reset-names = "ahb"; 349 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&mmc1_pins>; 352 max-frequency = <150000000>; 353 status = "disabled"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 }; 357 358 mmc2: mmc@4022000 { 359 compatible = "allwinner,sun50i-h6-emmc", 360 "allwinner,sun50i-a64-emmc"; 361 reg = <0x04022000 0x1000>; 362 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 363 clock-names = "ahb", "mmc"; 364 resets = <&ccu RST_BUS_MMC2>; 365 reset-names = "ahb"; 366 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&mmc2_pins>; 369 max-frequency = <150000000>; 370 status = "disabled"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 }; 374 375 uart0: serial@5000000 { 376 compatible = "snps,dw-apb-uart"; 377 reg = <0x05000000 0x400>; 378 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 379 reg-shift = <2>; 380 reg-io-width = <4>; 381 clocks = <&ccu CLK_BUS_UART0>; 382 resets = <&ccu RST_BUS_UART0>; 383 status = "disabled"; 384 }; 385 386 uart1: serial@5000400 { 387 compatible = "snps,dw-apb-uart"; 388 reg = <0x05000400 0x400>; 389 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 390 reg-shift = <2>; 391 reg-io-width = <4>; 392 clocks = <&ccu CLK_BUS_UART1>; 393 resets = <&ccu RST_BUS_UART1>; 394 status = "disabled"; 395 }; 396 397 uart2: serial@5000800 { 398 compatible = "snps,dw-apb-uart"; 399 reg = <0x05000800 0x400>; 400 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 401 reg-shift = <2>; 402 reg-io-width = <4>; 403 clocks = <&ccu CLK_BUS_UART2>; 404 resets = <&ccu RST_BUS_UART2>; 405 status = "disabled"; 406 }; 407 408 uart3: serial@5000c00 { 409 compatible = "snps,dw-apb-uart"; 410 reg = <0x05000c00 0x400>; 411 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 412 reg-shift = <2>; 413 reg-io-width = <4>; 414 clocks = <&ccu CLK_BUS_UART3>; 415 resets = <&ccu RST_BUS_UART3>; 416 status = "disabled"; 417 }; 418 419 i2c0: i2c@5002000 { 420 compatible = "allwinner,sun50i-h6-i2c", 421 "allwinner,sun6i-a31-i2c"; 422 reg = <0x05002000 0x400>; 423 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&ccu CLK_BUS_I2C0>; 425 resets = <&ccu RST_BUS_I2C0>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&i2c0_pins>; 428 status = "disabled"; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 }; 432 433 i2c1: i2c@5002400 { 434 compatible = "allwinner,sun50i-h6-i2c", 435 "allwinner,sun6i-a31-i2c"; 436 reg = <0x05002400 0x400>; 437 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&ccu CLK_BUS_I2C1>; 439 resets = <&ccu RST_BUS_I2C1>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2c1_pins>; 442 status = "disabled"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 }; 446 447 i2c2: i2c@5002800 { 448 compatible = "allwinner,sun50i-h6-i2c", 449 "allwinner,sun6i-a31-i2c"; 450 reg = <0x05002800 0x400>; 451 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&ccu CLK_BUS_I2C2>; 453 resets = <&ccu RST_BUS_I2C2>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&i2c2_pins>; 456 status = "disabled"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 }; 460 461 emac: ethernet@5020000 { 462 compatible = "allwinner,sun50i-h6-emac", 463 "allwinner,sun50i-a64-emac"; 464 syscon = <&syscon>; 465 reg = <0x05020000 0x10000>; 466 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "macirq"; 468 resets = <&ccu RST_BUS_EMAC>; 469 reset-names = "stmmaceth"; 470 clocks = <&ccu CLK_BUS_EMAC>; 471 clock-names = "stmmaceth"; 472 status = "disabled"; 473 474 mdio: mdio { 475 compatible = "snps,dwmac-mdio"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 }; 479 }; 480 481 spdif: spdif@5093000 { 482 #sound-dai-cells = <0>; 483 compatible = "allwinner,sun50i-h6-spdif"; 484 reg = <0x05093000 0x400>; 485 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 487 clock-names = "apb", "spdif"; 488 resets = <&ccu RST_BUS_SPDIF>; 489 dmas = <&dma 2>; 490 dma-names = "tx"; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&spdif_tx_pin>; 493 status = "disabled"; 494 }; 495 496 usb2otg: usb@5100000 { 497 compatible = "allwinner,sun50i-h6-musb", 498 "allwinner,sun8i-a33-musb"; 499 reg = <0x05100000 0x0400>; 500 clocks = <&ccu CLK_BUS_OTG>; 501 resets = <&ccu RST_BUS_OTG>; 502 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "mc"; 504 phys = <&usb2phy 0>; 505 phy-names = "usb"; 506 extcon = <&usb2phy 0>; 507 status = "disabled"; 508 }; 509 510 usb2phy: phy@5100400 { 511 compatible = "allwinner,sun50i-h6-usb-phy"; 512 reg = <0x05100400 0x24>, 513 <0x05101800 0x4>, 514 <0x05311800 0x4>; 515 reg-names = "phy_ctrl", 516 "pmu0", 517 "pmu3"; 518 clocks = <&ccu CLK_USB_PHY0>, 519 <&ccu CLK_USB_PHY3>; 520 clock-names = "usb0_phy", 521 "usb3_phy"; 522 resets = <&ccu RST_USB_PHY0>, 523 <&ccu RST_USB_PHY3>; 524 reset-names = "usb0_reset", 525 "usb3_reset"; 526 status = "disabled"; 527 #phy-cells = <1>; 528 }; 529 530 ehci0: usb@5101000 { 531 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 532 reg = <0x05101000 0x100>; 533 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&ccu CLK_BUS_OHCI0>, 535 <&ccu CLK_BUS_EHCI0>, 536 <&ccu CLK_USB_OHCI0>; 537 resets = <&ccu RST_BUS_OHCI0>, 538 <&ccu RST_BUS_EHCI0>; 539 phys = <&usb2phy 0>; 540 phy-names = "usb"; 541 status = "disabled"; 542 }; 543 544 ohci0: usb@5101400 { 545 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 546 reg = <0x05101400 0x100>; 547 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&ccu CLK_BUS_OHCI0>, 549 <&ccu CLK_USB_OHCI0>; 550 resets = <&ccu RST_BUS_OHCI0>; 551 phys = <&usb2phy 0>; 552 phy-names = "usb"; 553 status = "disabled"; 554 }; 555 556 ehci3: usb@5311000 { 557 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 558 reg = <0x05311000 0x100>; 559 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&ccu CLK_BUS_OHCI3>, 561 <&ccu CLK_BUS_EHCI3>, 562 <&ccu CLK_USB_OHCI3>; 563 resets = <&ccu RST_BUS_OHCI3>, 564 <&ccu RST_BUS_EHCI3>; 565 phys = <&usb2phy 3>; 566 phy-names = "usb"; 567 status = "disabled"; 568 }; 569 570 ohci3: usb@5311400 { 571 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 572 reg = <0x05311400 0x100>; 573 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&ccu CLK_BUS_OHCI3>, 575 <&ccu CLK_USB_OHCI3>; 576 resets = <&ccu RST_BUS_OHCI3>; 577 phys = <&usb2phy 3>; 578 phy-names = "usb"; 579 status = "disabled"; 580 }; 581 582 hdmi: hdmi@6000000 { 583 compatible = "allwinner,sun50i-h6-dw-hdmi"; 584 reg = <0x06000000 0x10000>; 585 reg-io-width = <1>; 586 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 588 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 589 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 590 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 591 "hdcp-bus"; 592 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 593 reset-names = "ctrl", "hdcp"; 594 phys = <&hdmi_phy>; 595 phy-names = "phy"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&hdmi_pins>; 598 status = "disabled"; 599 600 ports { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 604 hdmi_in: port@0 { 605 reg = <0>; 606 607 hdmi_in_tcon_top: endpoint { 608 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 609 }; 610 }; 611 612 hdmi_out: port@1 { 613 reg = <1>; 614 }; 615 }; 616 }; 617 618 hdmi_phy: hdmi-phy@6010000 { 619 compatible = "allwinner,sun50i-h6-hdmi-phy"; 620 reg = <0x06010000 0x10000>; 621 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 622 clock-names = "bus", "mod"; 623 resets = <&ccu RST_BUS_HDMI>; 624 reset-names = "phy"; 625 #phy-cells = <0>; 626 }; 627 628 tcon_top: tcon-top@6510000 { 629 compatible = "allwinner,sun50i-h6-tcon-top"; 630 reg = <0x06510000 0x1000>; 631 clocks = <&ccu CLK_BUS_TCON_TOP>, 632 <&ccu CLK_TCON_TV0>; 633 clock-names = "bus", 634 "tcon-tv0"; 635 clock-output-names = "tcon-top-tv0"; 636 resets = <&ccu RST_BUS_TCON_TOP>; 637 reset-names = "rst"; 638 #clock-cells = <1>; 639 640 ports { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 tcon_top_mixer0_in: port@0 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 reg = <0>; 648 649 tcon_top_mixer0_in_mixer0: endpoint@0 { 650 reg = <0>; 651 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 652 }; 653 }; 654 655 tcon_top_mixer0_out: port@1 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 reg = <1>; 659 660 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 661 reg = <2>; 662 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 663 }; 664 }; 665 666 tcon_top_hdmi_in: port@4 { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 reg = <4>; 670 671 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 672 reg = <0>; 673 remote-endpoint = <&tcon_tv_out_tcon_top>; 674 }; 675 }; 676 677 tcon_top_hdmi_out: port@5 { 678 reg = <5>; 679 680 tcon_top_hdmi_out_hdmi: endpoint { 681 remote-endpoint = <&hdmi_in_tcon_top>; 682 }; 683 }; 684 }; 685 }; 686 687 tcon_tv: lcd-controller@6515000 { 688 compatible = "allwinner,sun50i-h6-tcon-tv", 689 "allwinner,sun8i-r40-tcon-tv"; 690 reg = <0x06515000 0x1000>; 691 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&ccu CLK_BUS_TCON_TV0>, 693 <&tcon_top CLK_TCON_TOP_TV0>; 694 clock-names = "ahb", 695 "tcon-ch1"; 696 resets = <&ccu RST_BUS_TCON_TV0>; 697 reset-names = "lcd"; 698 699 ports { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 703 tcon_tv_in: port@0 { 704 reg = <0>; 705 706 tcon_tv_in_tcon_top_mixer0: endpoint { 707 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 708 }; 709 }; 710 711 tcon_tv_out: port@1 { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 reg = <1>; 715 716 tcon_tv_out_tcon_top: endpoint@1 { 717 reg = <1>; 718 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 719 }; 720 }; 721 }; 722 }; 723 724 rtc: rtc@7000000 { 725 compatible = "allwinner,sun50i-h6-rtc"; 726 reg = <0x07000000 0x400>; 727 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 729 clock-output-names = "osc32k", "osc32k-out", "iosc"; 730 clocks = <&ext_osc32k>; 731 #clock-cells = <1>; 732 }; 733 734 r_ccu: clock@7010000 { 735 compatible = "allwinner,sun50i-h6-r-ccu"; 736 reg = <0x07010000 0x400>; 737 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 738 <&ccu CLK_PLL_PERIPH0>; 739 clock-names = "hosc", "losc", "iosc", "pll-periph"; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 }; 743 744 r_watchdog: watchdog@7020400 { 745 compatible = "allwinner,sun50i-h6-wdt", 746 "allwinner,sun6i-a31-wdt"; 747 reg = <0x07020400 0x20>; 748 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&osc24M>; 750 }; 751 752 r_intc: interrupt-controller@7021000 { 753 compatible = "allwinner,sun50i-h6-r-intc", 754 "allwinner,sun6i-a31-r-intc"; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 reg = <0x07021000 0x400>; 758 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 759 }; 760 761 r_pio: pinctrl@7022000 { 762 compatible = "allwinner,sun50i-h6-r-pinctrl"; 763 reg = <0x07022000 0x400>; 764 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 767 clock-names = "apb", "hosc", "losc"; 768 gpio-controller; 769 #gpio-cells = <3>; 770 interrupt-controller; 771 #interrupt-cells = <3>; 772 773 r_i2c_pins: r-i2c-pins { 774 pins = "PL0", "PL1"; 775 function = "s_i2c"; 776 }; 777 778 r_ir_rx_pin: r-ir-rx-pin { 779 pins = "PL9"; 780 function = "s_cir_rx"; 781 }; 782 }; 783 784 r_ir: ir@7040000 { 785 compatible = "allwinner,sun50i-h6-ir", 786 "allwinner,sun6i-a31-ir"; 787 reg = <0x07040000 0x400>; 788 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&r_ccu CLK_R_APB1_IR>, 790 <&r_ccu CLK_IR>; 791 clock-names = "apb", "ir"; 792 resets = <&r_ccu RST_R_APB1_IR>; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&r_ir_rx_pin>; 795 status = "disabled"; 796 }; 797 798 r_i2c: i2c@7081400 { 799 compatible = "allwinner,sun50i-h6-i2c", 800 "allwinner,sun6i-a31-i2c"; 801 reg = <0x07081400 0x400>; 802 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&r_ccu CLK_R_APB2_I2C>; 804 resets = <&r_ccu RST_R_APB2_I2C>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&r_i2c_pins>; 807 status = "disabled"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 }; 811 }; 812}; 813