1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> 15#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 tdmif_a: audio-controller-0 { 23 compatible = "amlogic,axg-tdm-iface"; 24 #sound-dai-cells = <0>; 25 sound-name-prefix = "TDM_A"; 26 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 27 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 29 clock-names = "mclk", "sclk", "lrclk"; 30 status = "disabled"; 31 }; 32 33 tdmif_b: audio-controller-1 { 34 compatible = "amlogic,axg-tdm-iface"; 35 #sound-dai-cells = <0>; 36 sound-name-prefix = "TDM_B"; 37 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 38 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 40 clock-names = "mclk", "sclk", "lrclk"; 41 status = "disabled"; 42 }; 43 44 tdmif_c: audio-controller-2 { 45 compatible = "amlogic,axg-tdm-iface"; 46 #sound-dai-cells = <0>; 47 sound-name-prefix = "TDM_C"; 48 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 49 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 51 clock-names = "mclk", "sclk", "lrclk"; 52 status = "disabled"; 53 }; 54 55 efuse: efuse { 56 compatible = "amlogic,meson-gxbb-efuse"; 57 clocks = <&clkc CLKID_EFUSE>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 read-only; 61 }; 62 63 psci { 64 compatible = "arm,psci-1.0"; 65 method = "smc"; 66 }; 67 68 reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 74 secmon_reserved: secmon@5000000 { 75 reg = <0x0 0x05000000 0x0 0x300000>; 76 no-map; 77 }; 78 79 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 80 secmon_reserved_bl32: secmon@5300000 { 81 reg = <0x0 0x05300000 0x0 0x2000000>; 82 no-map; 83 }; 84 85 linux,cma { 86 compatible = "shared-dma-pool"; 87 reusable; 88 size = <0x0 0x10000000>; 89 alignment = <0x0 0x400000>; 90 linux,cma-default; 91 }; 92 }; 93 94 sm: secure-monitor { 95 compatible = "amlogic,meson-gxbb-sm"; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges; 103 104 ethmac: ethernet@ff3f0000 { 105 compatible = "amlogic,meson-axg-dwmac", 106 "snps,dwmac-3.70a", 107 "snps,dwmac"; 108 reg = <0x0 0xff3f0000 0x0 0x10000>, 109 <0x0 0xff634540 0x0 0x8>; 110 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 111 interrupt-names = "macirq"; 112 clocks = <&clkc CLKID_ETH>, 113 <&clkc CLKID_FCLK_DIV2>, 114 <&clkc CLKID_MPLL2>; 115 clock-names = "stmmaceth", "clkin0", "clkin1"; 116 rx-fifo-depth = <4096>; 117 tx-fifo-depth = <2048>; 118 status = "disabled"; 119 120 mdio0: mdio { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 compatible = "snps,dwmac-mdio"; 124 }; 125 }; 126 127 apb: bus@ff600000 { 128 compatible = "simple-bus"; 129 reg = <0x0 0xff600000 0x0 0x200000>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 133 134 hdmi_tx: hdmi-tx@0 { 135 compatible = "amlogic,meson-g12a-dw-hdmi"; 136 reg = <0x0 0x0 0x0 0x10000>; 137 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 138 resets = <&reset RESET_HDMITX_CAPB3>, 139 <&reset RESET_HDMITX_PHY>, 140 <&reset RESET_HDMITX>; 141 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 142 clocks = <&clkc CLKID_HDMI>, 143 <&clkc CLKID_HTX_PCLK>, 144 <&clkc CLKID_VPU_INTR>; 145 clock-names = "isfr", "iahb", "venci"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 #sound-dai-cells = <0>; 149 status = "disabled"; 150 151 /* VPU VENC Input */ 152 hdmi_tx_venc_port: port@0 { 153 reg = <0>; 154 155 hdmi_tx_in: endpoint { 156 remote-endpoint = <&hdmi_tx_out>; 157 }; 158 }; 159 160 /* TMDS Output */ 161 hdmi_tx_tmds_port: port@1 { 162 reg = <1>; 163 }; 164 }; 165 166 apb_efuse: bus@30000 { 167 compatible = "simple-bus"; 168 reg = <0x0 0x30000 0x0 0x2000>; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 172 173 hwrng: rng@218 { 174 compatible = "amlogic,meson-rng"; 175 reg = <0x0 0x218 0x0 0x4>; 176 clocks = <&clkc CLKID_RNG0>; 177 clock-names = "core"; 178 }; 179 }; 180 181 periphs: bus@34400 { 182 compatible = "simple-bus"; 183 reg = <0x0 0x34400 0x0 0x400>; 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 187 188 periphs_pinctrl: pinctrl@40 { 189 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 gpio: bank@40 { 195 reg = <0x0 0x40 0x0 0x4c>, 196 <0x0 0xe8 0x0 0x18>, 197 <0x0 0x120 0x0 0x18>, 198 <0x0 0x2c0 0x0 0x40>, 199 <0x0 0x340 0x0 0x1c>; 200 reg-names = "gpio", 201 "pull", 202 "pull-enable", 203 "mux", 204 "ds"; 205 gpio-controller; 206 #gpio-cells = <2>; 207 gpio-ranges = <&periphs_pinctrl 0 0 86>; 208 }; 209 210 cec_ao_a_h_pins: cec_ao_a_h { 211 mux { 212 groups = "cec_ao_a_h"; 213 function = "cec_ao_a_h"; 214 bias-disable; 215 }; 216 }; 217 218 cec_ao_b_h_pins: cec_ao_b_h { 219 mux { 220 groups = "cec_ao_b_h"; 221 function = "cec_ao_b_h"; 222 bias-disable; 223 }; 224 }; 225 226 emmc_pins: emmc { 227 mux-0 { 228 groups = "emmc_nand_d0", 229 "emmc_nand_d1", 230 "emmc_nand_d2", 231 "emmc_nand_d3", 232 "emmc_nand_d4", 233 "emmc_nand_d5", 234 "emmc_nand_d6", 235 "emmc_nand_d7", 236 "emmc_cmd"; 237 function = "emmc"; 238 bias-pull-up; 239 drive-strength-microamp = <4000>; 240 }; 241 242 mux-1 { 243 groups = "emmc_clk"; 244 function = "emmc"; 245 bias-disable; 246 drive-strength-microamp = <4000>; 247 }; 248 }; 249 250 emmc_ds_pins: emmc-ds { 251 mux { 252 groups = "emmc_nand_ds"; 253 function = "emmc"; 254 bias-pull-down; 255 drive-strength-microamp = <4000>; 256 }; 257 }; 258 259 emmc_clk_gate_pins: emmc_clk_gate { 260 mux { 261 groups = "BOOT_8"; 262 function = "gpio_periphs"; 263 bias-pull-down; 264 drive-strength-microamp = <4000>; 265 }; 266 }; 267 268 hdmitx_ddc_pins: hdmitx_ddc { 269 mux { 270 groups = "hdmitx_sda", 271 "hdmitx_sck"; 272 function = "hdmitx"; 273 bias-disable; 274 drive-strength-microamp = <4000>; 275 }; 276 }; 277 278 hdmitx_hpd_pins: hdmitx_hpd { 279 mux { 280 groups = "hdmitx_hpd_in"; 281 function = "hdmitx"; 282 bias-disable; 283 }; 284 }; 285 286 287 i2c0_sda_c_pins: i2c0-sda-c { 288 mux { 289 groups = "i2c0_sda_c"; 290 function = "i2c0"; 291 bias-disable; 292 drive-strength-microamp = <3000>; 293 294 }; 295 }; 296 297 i2c0_sck_c_pins: i2c0-sck-c { 298 mux { 299 groups = "i2c0_sck_c"; 300 function = "i2c0"; 301 bias-disable; 302 drive-strength-microamp = <3000>; 303 }; 304 }; 305 306 i2c0_sda_z0_pins: i2c0-sda-z0 { 307 mux { 308 groups = "i2c0_sda_z0"; 309 function = "i2c0"; 310 bias-disable; 311 drive-strength-microamp = <3000>; 312 }; 313 }; 314 315 i2c0_sck_z1_pins: i2c0-sck-z1 { 316 mux { 317 groups = "i2c0_sck_z1"; 318 function = "i2c0"; 319 bias-disable; 320 drive-strength-microamp = <3000>; 321 }; 322 }; 323 324 i2c0_sda_z7_pins: i2c0-sda-z7 { 325 mux { 326 groups = "i2c0_sda_z7"; 327 function = "i2c0"; 328 bias-disable; 329 drive-strength-microamp = <3000>; 330 }; 331 }; 332 333 i2c0_sda_z8_pins: i2c0-sda-z8 { 334 mux { 335 groups = "i2c0_sda_z8"; 336 function = "i2c0"; 337 bias-disable; 338 drive-strength-microamp = <3000>; 339 }; 340 }; 341 342 i2c1_sda_x_pins: i2c1-sda-x { 343 mux { 344 groups = "i2c1_sda_x"; 345 function = "i2c1"; 346 bias-disable; 347 drive-strength-microamp = <3000>; 348 }; 349 }; 350 351 i2c1_sck_x_pins: i2c1-sck-x { 352 mux { 353 groups = "i2c1_sck_x"; 354 function = "i2c1"; 355 bias-disable; 356 drive-strength-microamp = <3000>; 357 }; 358 }; 359 360 i2c1_sda_h2_pins: i2c1-sda-h2 { 361 mux { 362 groups = "i2c1_sda_h2"; 363 function = "i2c1"; 364 bias-disable; 365 drive-strength-microamp = <3000>; 366 }; 367 }; 368 369 i2c1_sck_h3_pins: i2c1-sck-h3 { 370 mux { 371 groups = "i2c1_sck_h3"; 372 function = "i2c1"; 373 bias-disable; 374 drive-strength-microamp = <3000>; 375 }; 376 }; 377 378 i2c1_sda_h6_pins: i2c1-sda-h6 { 379 mux { 380 groups = "i2c1_sda_h6"; 381 function = "i2c1"; 382 bias-disable; 383 drive-strength-microamp = <3000>; 384 }; 385 }; 386 387 i2c1_sck_h7_pins: i2c1-sck-h7 { 388 mux { 389 groups = "i2c1_sck_h7"; 390 function = "i2c1"; 391 bias-disable; 392 drive-strength-microamp = <3000>; 393 }; 394 }; 395 396 i2c2_sda_x_pins: i2c2-sda-x { 397 mux { 398 groups = "i2c2_sda_x"; 399 function = "i2c2"; 400 bias-disable; 401 drive-strength-microamp = <3000>; 402 }; 403 }; 404 405 i2c2_sck_x_pins: i2c2-sck-x { 406 mux { 407 groups = "i2c2_sck_x"; 408 function = "i2c2"; 409 bias-disable; 410 drive-strength-microamp = <3000>; 411 }; 412 }; 413 414 i2c2_sda_z_pins: i2c2-sda-z { 415 mux { 416 groups = "i2c2_sda_z"; 417 function = "i2c2"; 418 bias-disable; 419 drive-strength-microamp = <3000>; 420 }; 421 }; 422 423 i2c2_sck_z_pins: i2c2-sck-z { 424 mux { 425 groups = "i2c2_sck_z"; 426 function = "i2c2"; 427 bias-disable; 428 drive-strength-microamp = <3000>; 429 }; 430 }; 431 432 i2c3_sda_h_pins: i2c3-sda-h { 433 mux { 434 groups = "i2c3_sda_h"; 435 function = "i2c3"; 436 bias-disable; 437 drive-strength-microamp = <3000>; 438 }; 439 }; 440 441 i2c3_sck_h_pins: i2c3-sck-h { 442 mux { 443 groups = "i2c3_sck_h"; 444 function = "i2c3"; 445 bias-disable; 446 drive-strength-microamp = <3000>; 447 }; 448 }; 449 450 i2c3_sda_a_pins: i2c3-sda-a { 451 mux { 452 groups = "i2c3_sda_a"; 453 function = "i2c3"; 454 bias-disable; 455 drive-strength-microamp = <3000>; 456 }; 457 }; 458 459 i2c3_sck_a_pins: i2c3-sck-a { 460 mux { 461 groups = "i2c3_sck_a"; 462 function = "i2c3"; 463 bias-disable; 464 drive-strength-microamp = <3000>; 465 }; 466 }; 467 468 mclk0_a_pins: mclk0-a { 469 mux { 470 groups = "mclk0_a"; 471 function = "mclk0"; 472 bias-disable; 473 drive-strength-microamp = <3000>; 474 }; 475 }; 476 477 mclk1_a_pins: mclk1-a { 478 mux { 479 groups = "mclk1_a"; 480 function = "mclk1"; 481 bias-disable; 482 drive-strength-microamp = <3000>; 483 }; 484 }; 485 486 mclk1_x_pins: mclk1-x { 487 mux { 488 groups = "mclk1_x"; 489 function = "mclk1"; 490 bias-disable; 491 drive-strength-microamp = <3000>; 492 }; 493 }; 494 495 mclk1_z_pins: mclk1-z { 496 mux { 497 groups = "mclk1_z"; 498 function = "mclk1"; 499 bias-disable; 500 drive-strength-microamp = <3000>; 501 }; 502 }; 503 504 pdm_din0_a_pins: pdm-din0-a { 505 mux { 506 groups = "pdm_din0_a"; 507 function = "pdm"; 508 bias-disable; 509 }; 510 }; 511 512 pdm_din0_c_pins: pdm-din0-c { 513 mux { 514 groups = "pdm_din0_c"; 515 function = "pdm"; 516 bias-disable; 517 }; 518 }; 519 520 pdm_din0_x_pins: pdm-din0-x { 521 mux { 522 groups = "pdm_din0_x"; 523 function = "pdm"; 524 bias-disable; 525 }; 526 }; 527 528 pdm_din0_z_pins: pdm-din0-z { 529 mux { 530 groups = "pdm_din0_z"; 531 function = "pdm"; 532 bias-disable; 533 }; 534 }; 535 536 pdm_din1_a_pins: pdm-din1-a { 537 mux { 538 groups = "pdm_din1_a"; 539 function = "pdm"; 540 bias-disable; 541 }; 542 }; 543 544 pdm_din1_c_pins: pdm-din1-c { 545 mux { 546 groups = "pdm_din1_c"; 547 function = "pdm"; 548 bias-disable; 549 }; 550 }; 551 552 pdm_din1_x_pins: pdm-din1-x { 553 mux { 554 groups = "pdm_din1_x"; 555 function = "pdm"; 556 bias-disable; 557 }; 558 }; 559 560 pdm_din1_z_pins: pdm-din1-z { 561 mux { 562 groups = "pdm_din1_z"; 563 function = "pdm"; 564 bias-disable; 565 }; 566 }; 567 568 pdm_din2_a_pins: pdm-din2-a { 569 mux { 570 groups = "pdm_din2_a"; 571 function = "pdm"; 572 bias-disable; 573 }; 574 }; 575 576 pdm_din2_c_pins: pdm-din2-c { 577 mux { 578 groups = "pdm_din2_c"; 579 function = "pdm"; 580 bias-disable; 581 }; 582 }; 583 584 pdm_din2_x_pins: pdm-din2-x { 585 mux { 586 groups = "pdm_din2_x"; 587 function = "pdm"; 588 bias-disable; 589 }; 590 }; 591 592 pdm_din2_z_pins: pdm-din2-z { 593 mux { 594 groups = "pdm_din2_z"; 595 function = "pdm"; 596 bias-disable; 597 }; 598 }; 599 600 pdm_din3_a_pins: pdm-din3-a { 601 mux { 602 groups = "pdm_din3_a"; 603 function = "pdm"; 604 bias-disable; 605 }; 606 }; 607 608 pdm_din3_c_pins: pdm-din3-c { 609 mux { 610 groups = "pdm_din3_c"; 611 function = "pdm"; 612 bias-disable; 613 }; 614 }; 615 616 pdm_din3_x_pins: pdm-din3-x { 617 mux { 618 groups = "pdm_din3_x"; 619 function = "pdm"; 620 bias-disable; 621 }; 622 }; 623 624 pdm_din3_z_pins: pdm-din3-z { 625 mux { 626 groups = "pdm_din3_z"; 627 function = "pdm"; 628 bias-disable; 629 }; 630 }; 631 632 pdm_dclk_a_pins: pdm-dclk-a { 633 mux { 634 groups = "pdm_dclk_a"; 635 function = "pdm"; 636 bias-disable; 637 drive-strength-microamp = <500>; 638 }; 639 }; 640 641 pdm_dclk_c_pins: pdm-dclk-c { 642 mux { 643 groups = "pdm_dclk_c"; 644 function = "pdm"; 645 bias-disable; 646 drive-strength-microamp = <500>; 647 }; 648 }; 649 650 pdm_dclk_x_pins: pdm-dclk-x { 651 mux { 652 groups = "pdm_dclk_x"; 653 function = "pdm"; 654 bias-disable; 655 drive-strength-microamp = <500>; 656 }; 657 }; 658 659 pdm_dclk_z_pins: pdm-dclk-z { 660 mux { 661 groups = "pdm_dclk_z"; 662 function = "pdm"; 663 bias-disable; 664 drive-strength-microamp = <500>; 665 }; 666 }; 667 668 pwm_a_pins: pwm-a { 669 mux { 670 groups = "pwm_a"; 671 function = "pwm_a"; 672 bias-disable; 673 }; 674 }; 675 676 pwm_b_x7_pins: pwm-b-x7 { 677 mux { 678 groups = "pwm_b_x7"; 679 function = "pwm_b"; 680 bias-disable; 681 }; 682 }; 683 684 pwm_b_x19_pins: pwm-b-x19 { 685 mux { 686 groups = "pwm_b_x19"; 687 function = "pwm_b"; 688 bias-disable; 689 }; 690 }; 691 692 pwm_c_c_pins: pwm-c-c { 693 mux { 694 groups = "pwm_c_c"; 695 function = "pwm_c"; 696 bias-disable; 697 }; 698 }; 699 700 pwm_c_x5_pins: pwm-c-x5 { 701 mux { 702 groups = "pwm_c_x5"; 703 function = "pwm_c"; 704 bias-disable; 705 }; 706 }; 707 708 pwm_c_x8_pins: pwm-c-x8 { 709 mux { 710 groups = "pwm_c_x8"; 711 function = "pwm_c"; 712 bias-disable; 713 }; 714 }; 715 716 pwm_d_x3_pins: pwm-d-x3 { 717 mux { 718 groups = "pwm_d_x3"; 719 function = "pwm_d"; 720 bias-disable; 721 }; 722 }; 723 724 pwm_d_x6_pins: pwm-d-x6 { 725 mux { 726 groups = "pwm_d_x6"; 727 function = "pwm_d"; 728 bias-disable; 729 }; 730 }; 731 732 pwm_e_pins: pwm-e { 733 mux { 734 groups = "pwm_e"; 735 function = "pwm_e"; 736 bias-disable; 737 }; 738 }; 739 740 pwm_f_x_pins: pwm-f-x { 741 mux { 742 groups = "pwm_f_x"; 743 function = "pwm_f"; 744 bias-disable; 745 }; 746 }; 747 748 pwm_f_h_pins: pwm-f-h { 749 mux { 750 groups = "pwm_f_h"; 751 function = "pwm_f"; 752 bias-disable; 753 }; 754 }; 755 756 sdcard_c_pins: sdcard_c { 757 mux-0 { 758 groups = "sdcard_d0_c", 759 "sdcard_d1_c", 760 "sdcard_d2_c", 761 "sdcard_d3_c", 762 "sdcard_cmd_c"; 763 function = "sdcard"; 764 bias-pull-up; 765 drive-strength-microamp = <4000>; 766 }; 767 768 mux-1 { 769 groups = "sdcard_clk_c"; 770 function = "sdcard"; 771 bias-disable; 772 drive-strength-microamp = <4000>; 773 }; 774 }; 775 776 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 777 mux { 778 groups = "GPIOC_4"; 779 function = "gpio_periphs"; 780 bias-pull-down; 781 drive-strength-microamp = <4000>; 782 }; 783 }; 784 785 sdcard_z_pins: sdcard_z { 786 mux-0 { 787 groups = "sdcard_d0_z", 788 "sdcard_d1_z", 789 "sdcard_d2_z", 790 "sdcard_d3_z", 791 "sdcard_cmd_z"; 792 function = "sdcard"; 793 bias-pull-up; 794 drive-strength-microamp = <4000>; 795 }; 796 797 mux-1 { 798 groups = "sdcard_clk_z"; 799 function = "sdcard"; 800 bias-disable; 801 drive-strength-microamp = <4000>; 802 }; 803 }; 804 805 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 806 mux { 807 groups = "GPIOZ_6"; 808 function = "gpio_periphs"; 809 bias-pull-down; 810 drive-strength-microamp = <4000>; 811 }; 812 }; 813 814 sdio_pins: sdio { 815 mux { 816 groups = "sdio_d0", 817 "sdio_d1", 818 "sdio_d2", 819 "sdio_d3", 820 "sdio_clk", 821 "sdio_cmd"; 822 function = "sdio"; 823 bias-disable; 824 drive-strength-microamp = <4000>; 825 }; 826 }; 827 828 sdio_clk_gate_pins: sdio_clk_gate { 829 mux { 830 groups = "GPIOX_4"; 831 function = "gpio_periphs"; 832 bias-pull-down; 833 drive-strength-microamp = <4000>; 834 }; 835 }; 836 837 spdif_in_a10_pins: spdif-in-a10 { 838 mux { 839 groups = "spdif_in_a10"; 840 function = "spdif_in"; 841 bias-disable; 842 }; 843 }; 844 845 spdif_in_a12_pins: spdif-in-a12 { 846 mux { 847 groups = "spdif_in_a12"; 848 function = "spdif_in"; 849 bias-disable; 850 }; 851 }; 852 853 spdif_in_h_pins: spdif-in-h { 854 mux { 855 groups = "spdif_in_h"; 856 function = "spdif_in"; 857 bias-disable; 858 }; 859 }; 860 861 spdif_out_h_pins: spdif-out-h { 862 mux { 863 groups = "spdif_out_h"; 864 function = "spdif_out"; 865 drive-strength-microamp = <500>; 866 bias-disable; 867 }; 868 }; 869 870 spdif_out_a11_pins: spdif-out-a11 { 871 mux { 872 groups = "spdif_out_a11"; 873 function = "spdif_out"; 874 drive-strength-microamp = <500>; 875 bias-disable; 876 }; 877 }; 878 879 spdif_out_a13_pins: spdif-out-a13 { 880 mux { 881 groups = "spdif_out_a13"; 882 function = "spdif_out"; 883 drive-strength-microamp = <500>; 884 bias-disable; 885 }; 886 }; 887 888 tdm_a_din0_pins: tdm-a-din0 { 889 mux { 890 groups = "tdm_a_din0"; 891 function = "tdm_a"; 892 bias-disable; 893 }; 894 }; 895 896 897 tdm_a_din1_pins: tdm-a-din1 { 898 mux { 899 groups = "tdm_a_din1"; 900 function = "tdm_a"; 901 bias-disable; 902 }; 903 }; 904 905 tdm_a_dout0_pins: tdm-a-dout0 { 906 mux { 907 groups = "tdm_a_dout0"; 908 function = "tdm_a"; 909 bias-disable; 910 drive-strength-microamp = <3000>; 911 }; 912 }; 913 914 tdm_a_dout1_pins: tdm-a-dout1 { 915 mux { 916 groups = "tdm_a_dout1"; 917 function = "tdm_a"; 918 bias-disable; 919 drive-strength-microamp = <3000>; 920 }; 921 }; 922 923 tdm_a_fs_pins: tdm-a-fs { 924 mux { 925 groups = "tdm_a_fs"; 926 function = "tdm_a"; 927 bias-disable; 928 drive-strength-microamp = <3000>; 929 }; 930 }; 931 932 tdm_a_sclk_pins: tdm-a-sclk { 933 mux { 934 groups = "tdm_a_sclk"; 935 function = "tdm_a"; 936 bias-disable; 937 drive-strength-microamp = <3000>; 938 }; 939 }; 940 941 tdm_a_slv_fs_pins: tdm-a-slv-fs { 942 mux { 943 groups = "tdm_a_slv_fs"; 944 function = "tdm_a"; 945 bias-disable; 946 }; 947 }; 948 949 950 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 951 mux { 952 groups = "tdm_a_slv_sclk"; 953 function = "tdm_a"; 954 bias-disable; 955 }; 956 }; 957 958 tdm_b_din0_pins: tdm-b-din0 { 959 mux { 960 groups = "tdm_b_din0"; 961 function = "tdm_b"; 962 bias-disable; 963 }; 964 }; 965 966 tdm_b_din1_pins: tdm-b-din1 { 967 mux { 968 groups = "tdm_b_din1"; 969 function = "tdm_b"; 970 bias-disable; 971 }; 972 }; 973 974 tdm_b_din2_pins: tdm-b-din2 { 975 mux { 976 groups = "tdm_b_din2"; 977 function = "tdm_b"; 978 bias-disable; 979 }; 980 }; 981 982 tdm_b_din3_a_pins: tdm-b-din3-a { 983 mux { 984 groups = "tdm_b_din3_a"; 985 function = "tdm_b"; 986 bias-disable; 987 }; 988 }; 989 990 tdm_b_din3_h_pins: tdm-b-din3-h { 991 mux { 992 groups = "tdm_b_din3_h"; 993 function = "tdm_b"; 994 bias-disable; 995 }; 996 }; 997 998 tdm_b_dout0_pins: tdm-b-dout0 { 999 mux { 1000 groups = "tdm_b_dout0"; 1001 function = "tdm_b"; 1002 bias-disable; 1003 drive-strength-microamp = <3000>; 1004 }; 1005 }; 1006 1007 tdm_b_dout1_pins: tdm-b-dout1 { 1008 mux { 1009 groups = "tdm_b_dout1"; 1010 function = "tdm_b"; 1011 bias-disable; 1012 drive-strength-microamp = <3000>; 1013 }; 1014 }; 1015 1016 tdm_b_dout2_pins: tdm-b-dout2 { 1017 mux { 1018 groups = "tdm_b_dout2"; 1019 function = "tdm_b"; 1020 bias-disable; 1021 drive-strength-microamp = <3000>; 1022 }; 1023 }; 1024 1025 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1026 mux { 1027 groups = "tdm_b_dout3_a"; 1028 function = "tdm_b"; 1029 bias-disable; 1030 drive-strength-microamp = <3000>; 1031 }; 1032 }; 1033 1034 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1035 mux { 1036 groups = "tdm_b_dout3_h"; 1037 function = "tdm_b"; 1038 bias-disable; 1039 drive-strength-microamp = <3000>; 1040 }; 1041 }; 1042 1043 tdm_b_fs_pins: tdm-b-fs { 1044 mux { 1045 groups = "tdm_b_fs"; 1046 function = "tdm_b"; 1047 bias-disable; 1048 drive-strength-microamp = <3000>; 1049 }; 1050 }; 1051 1052 tdm_b_sclk_pins: tdm-b-sclk { 1053 mux { 1054 groups = "tdm_b_sclk"; 1055 function = "tdm_b"; 1056 bias-disable; 1057 drive-strength-microamp = <3000>; 1058 }; 1059 }; 1060 1061 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1062 mux { 1063 groups = "tdm_b_slv_fs"; 1064 function = "tdm_b"; 1065 bias-disable; 1066 }; 1067 }; 1068 1069 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1070 mux { 1071 groups = "tdm_b_slv_sclk"; 1072 function = "tdm_b"; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 tdm_c_din0_a_pins: tdm-c-din0-a { 1078 mux { 1079 groups = "tdm_c_din0_a"; 1080 function = "tdm_c"; 1081 bias-disable; 1082 }; 1083 }; 1084 1085 tdm_c_din0_z_pins: tdm-c-din0-z { 1086 mux { 1087 groups = "tdm_c_din0_z"; 1088 function = "tdm_c"; 1089 bias-disable; 1090 }; 1091 }; 1092 1093 tdm_c_din1_a_pins: tdm-c-din1-a { 1094 mux { 1095 groups = "tdm_c_din1_a"; 1096 function = "tdm_c"; 1097 bias-disable; 1098 }; 1099 }; 1100 1101 tdm_c_din1_z_pins: tdm-c-din1-z { 1102 mux { 1103 groups = "tdm_c_din1_z"; 1104 function = "tdm_c"; 1105 bias-disable; 1106 }; 1107 }; 1108 1109 tdm_c_din2_a_pins: tdm-c-din2-a { 1110 mux { 1111 groups = "tdm_c_din2_a"; 1112 function = "tdm_c"; 1113 bias-disable; 1114 }; 1115 }; 1116 1117 eth_leds_pins: eth-leds { 1118 mux { 1119 groups = "eth_link_led", 1120 "eth_act_led"; 1121 function = "eth"; 1122 bias-disable; 1123 }; 1124 }; 1125 1126 eth_pins: eth { 1127 mux { 1128 groups = "eth_mdio", 1129 "eth_mdc", 1130 "eth_rgmii_rx_clk", 1131 "eth_rx_dv", 1132 "eth_rxd0", 1133 "eth_rxd1", 1134 "eth_txen", 1135 "eth_txd0", 1136 "eth_txd1"; 1137 function = "eth"; 1138 drive-strength-microamp = <4000>; 1139 bias-disable; 1140 }; 1141 }; 1142 1143 eth_rgmii_pins: eth-rgmii { 1144 mux { 1145 groups = "eth_rxd2_rgmii", 1146 "eth_rxd3_rgmii", 1147 "eth_rgmii_tx_clk", 1148 "eth_txd2_rgmii", 1149 "eth_txd3_rgmii"; 1150 function = "eth"; 1151 drive-strength-microamp = <4000>; 1152 bias-disable; 1153 }; 1154 }; 1155 1156 tdm_c_din2_z_pins: tdm-c-din2-z { 1157 mux { 1158 groups = "tdm_c_din2_z"; 1159 function = "tdm_c"; 1160 bias-disable; 1161 }; 1162 }; 1163 1164 tdm_c_din3_a_pins: tdm-c-din3-a { 1165 mux { 1166 groups = "tdm_c_din3_a"; 1167 function = "tdm_c"; 1168 bias-disable; 1169 }; 1170 }; 1171 1172 tdm_c_din3_z_pins: tdm-c-din3-z { 1173 mux { 1174 groups = "tdm_c_din3_z"; 1175 function = "tdm_c"; 1176 bias-disable; 1177 }; 1178 }; 1179 1180 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1181 mux { 1182 groups = "tdm_c_dout0_a"; 1183 function = "tdm_c"; 1184 bias-disable; 1185 drive-strength-microamp = <3000>; 1186 }; 1187 }; 1188 1189 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1190 mux { 1191 groups = "tdm_c_dout0_z"; 1192 function = "tdm_c"; 1193 bias-disable; 1194 drive-strength-microamp = <3000>; 1195 }; 1196 }; 1197 1198 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1199 mux { 1200 groups = "tdm_c_dout1_a"; 1201 function = "tdm_c"; 1202 bias-disable; 1203 drive-strength-microamp = <3000>; 1204 }; 1205 }; 1206 1207 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1208 mux { 1209 groups = "tdm_c_dout1_z"; 1210 function = "tdm_c"; 1211 bias-disable; 1212 drive-strength-microamp = <3000>; 1213 }; 1214 }; 1215 1216 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1217 mux { 1218 groups = "tdm_c_dout2_a"; 1219 function = "tdm_c"; 1220 bias-disable; 1221 drive-strength-microamp = <3000>; 1222 }; 1223 }; 1224 1225 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1226 mux { 1227 groups = "tdm_c_dout2_z"; 1228 function = "tdm_c"; 1229 bias-disable; 1230 drive-strength-microamp = <3000>; 1231 }; 1232 }; 1233 1234 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1235 mux { 1236 groups = "tdm_c_dout3_a"; 1237 function = "tdm_c"; 1238 bias-disable; 1239 drive-strength-microamp = <3000>; 1240 }; 1241 }; 1242 1243 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1244 mux { 1245 groups = "tdm_c_dout3_z"; 1246 function = "tdm_c"; 1247 bias-disable; 1248 drive-strength-microamp = <3000>; 1249 }; 1250 }; 1251 1252 tdm_c_fs_a_pins: tdm-c-fs-a { 1253 mux { 1254 groups = "tdm_c_fs_a"; 1255 function = "tdm_c"; 1256 bias-disable; 1257 drive-strength-microamp = <3000>; 1258 }; 1259 }; 1260 1261 tdm_c_fs_z_pins: tdm-c-fs-z { 1262 mux { 1263 groups = "tdm_c_fs_z"; 1264 function = "tdm_c"; 1265 bias-disable; 1266 drive-strength-microamp = <3000>; 1267 }; 1268 }; 1269 1270 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1271 mux { 1272 groups = "tdm_c_sclk_a"; 1273 function = "tdm_c"; 1274 bias-disable; 1275 drive-strength-microamp = <3000>; 1276 }; 1277 }; 1278 1279 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1280 mux { 1281 groups = "tdm_c_sclk_z"; 1282 function = "tdm_c"; 1283 bias-disable; 1284 drive-strength-microamp = <3000>; 1285 }; 1286 }; 1287 1288 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1289 mux { 1290 groups = "tdm_c_slv_fs_a"; 1291 function = "tdm_c"; 1292 bias-disable; 1293 }; 1294 }; 1295 1296 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1297 mux { 1298 groups = "tdm_c_slv_fs_z"; 1299 function = "tdm_c"; 1300 bias-disable; 1301 }; 1302 }; 1303 1304 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1305 mux { 1306 groups = "tdm_c_slv_sclk_a"; 1307 function = "tdm_c"; 1308 bias-disable; 1309 }; 1310 }; 1311 1312 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1313 mux { 1314 groups = "tdm_c_slv_sclk_z"; 1315 function = "tdm_c"; 1316 bias-disable; 1317 }; 1318 }; 1319 1320 uart_a_pins: uart-a { 1321 mux { 1322 groups = "uart_a_tx", 1323 "uart_a_rx"; 1324 function = "uart_a"; 1325 bias-disable; 1326 }; 1327 }; 1328 1329 uart_a_cts_rts_pins: uart-a-cts-rts { 1330 mux { 1331 groups = "uart_a_cts", 1332 "uart_a_rts"; 1333 function = "uart_a"; 1334 bias-disable; 1335 }; 1336 }; 1337 1338 uart_b_pins: uart-b { 1339 mux { 1340 groups = "uart_b_tx", 1341 "uart_b_rx"; 1342 function = "uart_b"; 1343 bias-disable; 1344 }; 1345 }; 1346 1347 uart_c_pins: uart-c { 1348 mux { 1349 groups = "uart_c_tx", 1350 "uart_c_rx"; 1351 function = "uart_c"; 1352 bias-disable; 1353 }; 1354 }; 1355 1356 uart_c_cts_rts_pins: uart-c-cts-rts { 1357 mux { 1358 groups = "uart_c_cts", 1359 "uart_c_rts"; 1360 function = "uart_c"; 1361 bias-disable; 1362 }; 1363 }; 1364 }; 1365 }; 1366 1367 usb2_phy0: phy@36000 { 1368 compatible = "amlogic,g12a-usb2-phy"; 1369 reg = <0x0 0x36000 0x0 0x2000>; 1370 clocks = <&xtal>; 1371 clock-names = "xtal"; 1372 resets = <&reset RESET_USB_PHY20>; 1373 reset-names = "phy"; 1374 #phy-cells = <0>; 1375 }; 1376 1377 dmc: bus@38000 { 1378 compatible = "simple-bus"; 1379 #address-cells = <2>; 1380 #size-cells = <2>; 1381 ranges = <0x0 0x0 0x0 0x38000 0x0 0x2000>; 1382 1383 canvas: video-lut@48 { 1384 compatible = "amlogic,canvas"; 1385 reg = <0x0 0x48 0x0 0x14>; 1386 }; 1387 }; 1388 1389 usb2_phy1: phy@3a000 { 1390 compatible = "amlogic,g12a-usb2-phy"; 1391 reg = <0x0 0x3a000 0x0 0x2000>; 1392 clocks = <&xtal>; 1393 clock-names = "xtal"; 1394 resets = <&reset RESET_USB_PHY21>; 1395 reset-names = "phy"; 1396 #phy-cells = <0>; 1397 }; 1398 1399 hiu: bus@3c000 { 1400 compatible = "simple-bus"; 1401 reg = <0x0 0x3c000 0x0 0x1400>; 1402 #address-cells = <2>; 1403 #size-cells = <2>; 1404 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1405 1406 hhi: system-controller@0 { 1407 compatible = "amlogic,meson-gx-hhi-sysctrl", 1408 "simple-mfd", "syscon"; 1409 reg = <0 0 0 0x400>; 1410 1411 clkc: clock-controller { 1412 compatible = "amlogic,g12a-clkc"; 1413 #clock-cells = <1>; 1414 clocks = <&xtal>; 1415 clock-names = "xtal"; 1416 }; 1417 1418 pwrc: power-controller { 1419 compatible = "amlogic,meson-g12a-pwrc"; 1420 #power-domain-cells = <1>; 1421 amlogic,ao-sysctrl = <&rti>; 1422 resets = <&reset RESET_VIU>, 1423 <&reset RESET_VENC>, 1424 <&reset RESET_VCBUS>, 1425 <&reset RESET_BT656>, 1426 <&reset RESET_RDMA>, 1427 <&reset RESET_VENCI>, 1428 <&reset RESET_VENCP>, 1429 <&reset RESET_VDAC>, 1430 <&reset RESET_VDI6>, 1431 <&reset RESET_VENCL>, 1432 <&reset RESET_VID_LOCK>; 1433 reset-names = "viu", "venc", "vcbus", "bt656", 1434 "rdma", "venci", "vencp", "vdac", 1435 "vdi6", "vencl", "vid_lock"; 1436 clocks = <&clkc CLKID_VPU>, 1437 <&clkc CLKID_VAPB>; 1438 clock-names = "vpu", "vapb"; 1439 /* 1440 * VPU clocking is provided by two identical clock paths 1441 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1442 * free mux to safely change frequency while running. 1443 * Same for VAPB but with a final gate after the glitch free mux. 1444 */ 1445 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1446 <&clkc CLKID_VPU_0>, 1447 <&clkc CLKID_VPU>, /* Glitch free mux */ 1448 <&clkc CLKID_VAPB_0_SEL>, 1449 <&clkc CLKID_VAPB_0>, 1450 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1451 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1452 <0>, /* Do Nothing */ 1453 <&clkc CLKID_VPU_0>, 1454 <&clkc CLKID_FCLK_DIV4>, 1455 <0>, /* Do Nothing */ 1456 <&clkc CLKID_VAPB_0>; 1457 assigned-clock-rates = <0>, /* Do Nothing */ 1458 <666666666>, 1459 <0>, /* Do Nothing */ 1460 <0>, /* Do Nothing */ 1461 <250000000>, 1462 <0>; /* Do Nothing */ 1463 }; 1464 }; 1465 }; 1466 1467 pdm: audio-controller@40000 { 1468 compatible = "amlogic,g12a-pdm", 1469 "amlogic,axg-pdm"; 1470 reg = <0x0 0x40000 0x0 0x34>; 1471 #sound-dai-cells = <0>; 1472 sound-name-prefix = "PDM"; 1473 clocks = <&clkc_audio AUD_CLKID_PDM>, 1474 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1475 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1476 clock-names = "pclk", "dclk", "sysclk"; 1477 status = "disabled"; 1478 }; 1479 1480 audio: bus@42000 { 1481 compatible = "simple-bus"; 1482 reg = <0x0 0x42000 0x0 0x2000>; 1483 #address-cells = <2>; 1484 #size-cells = <2>; 1485 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1486 1487 clkc_audio: clock-controller@0 { 1488 status = "disabled"; 1489 compatible = "amlogic,g12a-audio-clkc"; 1490 reg = <0x0 0x0 0x0 0xb4>; 1491 #clock-cells = <1>; 1492 #reset-cells = <1>; 1493 1494 clocks = <&clkc CLKID_AUDIO>, 1495 <&clkc CLKID_MPLL0>, 1496 <&clkc CLKID_MPLL1>, 1497 <&clkc CLKID_MPLL2>, 1498 <&clkc CLKID_MPLL3>, 1499 <&clkc CLKID_HIFI_PLL>, 1500 <&clkc CLKID_FCLK_DIV3>, 1501 <&clkc CLKID_FCLK_DIV4>, 1502 <&clkc CLKID_GP0_PLL>; 1503 clock-names = "pclk", 1504 "mst_in0", 1505 "mst_in1", 1506 "mst_in2", 1507 "mst_in3", 1508 "mst_in4", 1509 "mst_in5", 1510 "mst_in6", 1511 "mst_in7"; 1512 1513 resets = <&reset RESET_AUDIO>; 1514 }; 1515 1516 toddr_a: audio-controller@100 { 1517 compatible = "amlogic,g12a-toddr", 1518 "amlogic,axg-toddr"; 1519 reg = <0x0 0x100 0x0 0x2c>; 1520 #sound-dai-cells = <0>; 1521 sound-name-prefix = "TODDR_A"; 1522 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1523 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1524 resets = <&arb AXG_ARB_TODDR_A>; 1525 status = "disabled"; 1526 }; 1527 1528 toddr_b: audio-controller@140 { 1529 compatible = "amlogic,g12a-toddr", 1530 "amlogic,axg-toddr"; 1531 reg = <0x0 0x140 0x0 0x2c>; 1532 #sound-dai-cells = <0>; 1533 sound-name-prefix = "TODDR_B"; 1534 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1535 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1536 resets = <&arb AXG_ARB_TODDR_B>; 1537 status = "disabled"; 1538 }; 1539 1540 toddr_c: audio-controller@180 { 1541 compatible = "amlogic,g12a-toddr", 1542 "amlogic,axg-toddr"; 1543 reg = <0x0 0x180 0x0 0x2c>; 1544 #sound-dai-cells = <0>; 1545 sound-name-prefix = "TODDR_C"; 1546 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1547 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1548 resets = <&arb AXG_ARB_TODDR_C>; 1549 status = "disabled"; 1550 }; 1551 1552 frddr_a: audio-controller@1c0 { 1553 compatible = "amlogic,g12a-frddr", 1554 "amlogic,axg-frddr"; 1555 reg = <0x0 0x1c0 0x0 0x2c>; 1556 #sound-dai-cells = <0>; 1557 sound-name-prefix = "FRDDR_A"; 1558 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1559 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1560 resets = <&arb AXG_ARB_FRDDR_A>; 1561 status = "disabled"; 1562 }; 1563 1564 frddr_b: audio-controller@200 { 1565 compatible = "amlogic,g12a-frddr", 1566 "amlogic,axg-frddr"; 1567 reg = <0x0 0x200 0x0 0x2c>; 1568 #sound-dai-cells = <0>; 1569 sound-name-prefix = "FRDDR_B"; 1570 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1571 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1572 resets = <&arb AXG_ARB_FRDDR_B>; 1573 status = "disabled"; 1574 }; 1575 1576 frddr_c: audio-controller@240 { 1577 compatible = "amlogic,g12a-frddr", 1578 "amlogic,axg-frddr"; 1579 reg = <0x0 0x240 0x0 0x2c>; 1580 #sound-dai-cells = <0>; 1581 sound-name-prefix = "FRDDR_C"; 1582 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1583 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1584 resets = <&arb AXG_ARB_FRDDR_C>; 1585 status = "disabled"; 1586 }; 1587 1588 arb: reset-controller@280 { 1589 status = "disabled"; 1590 compatible = "amlogic,meson-axg-audio-arb"; 1591 reg = <0x0 0x280 0x0 0x4>; 1592 #reset-cells = <1>; 1593 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1594 }; 1595 1596 tdmin_a: audio-controller@300 { 1597 compatible = "amlogic,g12a-tdmin", 1598 "amlogic,axg-tdmin"; 1599 reg = <0x0 0x300 0x0 0x40>; 1600 sound-name-prefix = "TDMIN_A"; 1601 resets = <&clkc_audio AUD_RESET_TDMIN_A>; 1602 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1603 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1604 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1605 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1606 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1607 clock-names = "pclk", "sclk", "sclk_sel", 1608 "lrclk", "lrclk_sel"; 1609 status = "disabled"; 1610 }; 1611 1612 tdmin_b: audio-controller@340 { 1613 compatible = "amlogic,g12a-tdmin", 1614 "amlogic,axg-tdmin"; 1615 reg = <0x0 0x340 0x0 0x40>; 1616 sound-name-prefix = "TDMIN_B"; 1617 resets = <&clkc_audio AUD_RESET_TDMIN_B>; 1618 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1619 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1620 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1621 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1622 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1623 clock-names = "pclk", "sclk", "sclk_sel", 1624 "lrclk", "lrclk_sel"; 1625 status = "disabled"; 1626 }; 1627 1628 tdmin_c: audio-controller@380 { 1629 compatible = "amlogic,g12a-tdmin", 1630 "amlogic,axg-tdmin"; 1631 reg = <0x0 0x380 0x0 0x40>; 1632 sound-name-prefix = "TDMIN_C"; 1633 resets = <&clkc_audio AUD_RESET_TDMIN_C>; 1634 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1635 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1636 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1637 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1638 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1639 clock-names = "pclk", "sclk", "sclk_sel", 1640 "lrclk", "lrclk_sel"; 1641 status = "disabled"; 1642 }; 1643 1644 tdmin_lb: audio-controller@3c0 { 1645 compatible = "amlogic,g12a-tdmin", 1646 "amlogic,axg-tdmin"; 1647 reg = <0x0 0x3c0 0x0 0x40>; 1648 sound-name-prefix = "TDMIN_LB"; 1649 resets = <&clkc_audio AUD_RESET_TDMIN_LB>; 1650 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1651 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1652 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1653 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1654 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1655 clock-names = "pclk", "sclk", "sclk_sel", 1656 "lrclk", "lrclk_sel"; 1657 status = "disabled"; 1658 }; 1659 1660 spdifin: audio-controller@400 { 1661 compatible = "amlogic,g12a-spdifin", 1662 "amlogic,axg-spdifin"; 1663 reg = <0x0 0x400 0x0 0x30>; 1664 #sound-dai-cells = <0>; 1665 sound-name-prefix = "SPDIFIN"; 1666 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1667 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1668 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1669 clock-names = "pclk", "refclk"; 1670 status = "disabled"; 1671 }; 1672 1673 spdifout: audio-controller@480 { 1674 compatible = "amlogic,g12a-spdifout", 1675 "amlogic,axg-spdifout"; 1676 reg = <0x0 0x480 0x0 0x50>; 1677 #sound-dai-cells = <0>; 1678 sound-name-prefix = "SPDIFOUT"; 1679 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1680 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1681 clock-names = "pclk", "mclk"; 1682 status = "disabled"; 1683 }; 1684 1685 tdmout_a: audio-controller@500 { 1686 compatible = "amlogic,g12a-tdmout"; 1687 reg = <0x0 0x500 0x0 0x40>; 1688 sound-name-prefix = "TDMOUT_A"; 1689 resets = <&clkc_audio AUD_RESET_TDMOUT_A>; 1690 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1691 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1692 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1693 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1694 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1695 clock-names = "pclk", "sclk", "sclk_sel", 1696 "lrclk", "lrclk_sel"; 1697 status = "disabled"; 1698 }; 1699 1700 tdmout_b: audio-controller@540 { 1701 compatible = "amlogic,g12a-tdmout"; 1702 reg = <0x0 0x540 0x0 0x40>; 1703 sound-name-prefix = "TDMOUT_B"; 1704 resets = <&clkc_audio AUD_RESET_TDMOUT_B>; 1705 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1706 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1707 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1708 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1709 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1710 clock-names = "pclk", "sclk", "sclk_sel", 1711 "lrclk", "lrclk_sel"; 1712 status = "disabled"; 1713 }; 1714 1715 tdmout_c: audio-controller@580 { 1716 compatible = "amlogic,g12a-tdmout"; 1717 reg = <0x0 0x580 0x0 0x40>; 1718 sound-name-prefix = "TDMOUT_C"; 1719 resets = <&clkc_audio AUD_RESET_TDMOUT_C>; 1720 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1721 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1722 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1723 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1724 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1725 clock-names = "pclk", "sclk", "sclk_sel", 1726 "lrclk", "lrclk_sel"; 1727 status = "disabled"; 1728 }; 1729 1730 spdifout_b: audio-controller@680 { 1731 compatible = "amlogic,g12a-spdifout", 1732 "amlogic,axg-spdifout"; 1733 reg = <0x0 0x680 0x0 0x50>; 1734 #sound-dai-cells = <0>; 1735 sound-name-prefix = "SPDIFOUT_B"; 1736 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1737 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1738 clock-names = "pclk", "mclk"; 1739 status = "disabled"; 1740 }; 1741 1742 tohdmitx: audio-controller@744 { 1743 compatible = "amlogic,g12a-tohdmitx"; 1744 reg = <0x0 0x744 0x0 0x4>; 1745 #sound-dai-cells = <1>; 1746 sound-name-prefix = "TOHDMITX"; 1747 status = "disabled"; 1748 }; 1749 }; 1750 1751 usb3_pcie_phy: phy@46000 { 1752 compatible = "amlogic,g12a-usb3-pcie-phy"; 1753 reg = <0x0 0x46000 0x0 0x2000>; 1754 clocks = <&clkc CLKID_PCIE_PLL>; 1755 clock-names = "ref_clk"; 1756 resets = <&reset RESET_PCIE_PHY>; 1757 reset-names = "phy"; 1758 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1759 assigned-clock-rates = <100000000>; 1760 #phy-cells = <1>; 1761 }; 1762 1763 eth_phy: mdio-multiplexer@4c000 { 1764 compatible = "amlogic,g12a-mdio-mux"; 1765 reg = <0x0 0x4c000 0x0 0xa4>; 1766 clocks = <&clkc CLKID_ETH_PHY>, 1767 <&xtal>, 1768 <&clkc CLKID_MPLL_50M>; 1769 clock-names = "pclk", "clkin0", "clkin1"; 1770 mdio-parent-bus = <&mdio0>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 ext_mdio: mdio@0 { 1775 reg = <0>; 1776 #address-cells = <1>; 1777 #size-cells = <0>; 1778 }; 1779 1780 int_mdio: mdio@1 { 1781 reg = <1>; 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 internal_ephy: ethernet-phy@8 { 1786 compatible = "ethernet-phy-id0180.3301", 1787 "ethernet-phy-ieee802.3-c22"; 1788 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1789 reg = <8>; 1790 max-speed = <100>; 1791 }; 1792 }; 1793 }; 1794 }; 1795 1796 aobus: bus@ff800000 { 1797 compatible = "simple-bus"; 1798 reg = <0x0 0xff800000 0x0 0x100000>; 1799 #address-cells = <2>; 1800 #size-cells = <2>; 1801 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1802 1803 rti: sys-ctrl@0 { 1804 compatible = "amlogic,meson-gx-ao-sysctrl", 1805 "simple-mfd", "syscon"; 1806 reg = <0x0 0x0 0x0 0x100>; 1807 #address-cells = <2>; 1808 #size-cells = <2>; 1809 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1810 1811 clkc_AO: clock-controller { 1812 compatible = "amlogic,meson-g12a-aoclkc"; 1813 #clock-cells = <1>; 1814 #reset-cells = <1>; 1815 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1816 clock-names = "xtal", "mpeg-clk"; 1817 }; 1818 1819 ao_pinctrl: pinctrl@14 { 1820 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1821 #address-cells = <2>; 1822 #size-cells = <2>; 1823 ranges; 1824 1825 gpio_ao: bank@14 { 1826 reg = <0x0 0x14 0x0 0x8>, 1827 <0x0 0x1c 0x0 0x8>, 1828 <0x0 0x24 0x0 0x14>; 1829 reg-names = "mux", 1830 "ds", 1831 "gpio"; 1832 gpio-controller; 1833 #gpio-cells = <2>; 1834 gpio-ranges = <&ao_pinctrl 0 0 15>; 1835 }; 1836 1837 i2c_ao_sck_pins: i2c_ao_sck_pins { 1838 mux { 1839 groups = "i2c_ao_sck"; 1840 function = "i2c_ao"; 1841 bias-disable; 1842 drive-strength-microamp = <3000>; 1843 }; 1844 }; 1845 1846 i2c_ao_sda_pins: i2c_ao_sda { 1847 mux { 1848 groups = "i2c_ao_sda"; 1849 function = "i2c_ao"; 1850 bias-disable; 1851 drive-strength-microamp = <3000>; 1852 }; 1853 }; 1854 1855 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1856 mux { 1857 groups = "i2c_ao_sck_e"; 1858 function = "i2c_ao"; 1859 bias-disable; 1860 drive-strength-microamp = <3000>; 1861 }; 1862 }; 1863 1864 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1865 mux { 1866 groups = "i2c_ao_sda_e"; 1867 function = "i2c_ao"; 1868 bias-disable; 1869 drive-strength-microamp = <3000>; 1870 }; 1871 }; 1872 1873 mclk0_ao_pins: mclk0-ao { 1874 mux { 1875 groups = "mclk0_ao"; 1876 function = "mclk0_ao"; 1877 bias-disable; 1878 drive-strength-microamp = <3000>; 1879 }; 1880 }; 1881 1882 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1883 mux { 1884 groups = "tdm_ao_b_din0"; 1885 function = "tdm_ao_b"; 1886 bias-disable; 1887 }; 1888 }; 1889 1890 spdif_ao_out_pins: spdif-ao-out { 1891 mux { 1892 groups = "spdif_ao_out"; 1893 function = "spdif_ao_out"; 1894 drive-strength-microamp = <500>; 1895 bias-disable; 1896 }; 1897 }; 1898 1899 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1900 mux { 1901 groups = "tdm_ao_b_din1"; 1902 function = "tdm_ao_b"; 1903 bias-disable; 1904 }; 1905 }; 1906 1907 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1908 mux { 1909 groups = "tdm_ao_b_din2"; 1910 function = "tdm_ao_b"; 1911 bias-disable; 1912 }; 1913 }; 1914 1915 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1916 mux { 1917 groups = "tdm_ao_b_dout0"; 1918 function = "tdm_ao_b"; 1919 bias-disable; 1920 drive-strength-microamp = <3000>; 1921 }; 1922 }; 1923 1924 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1925 mux { 1926 groups = "tdm_ao_b_dout1"; 1927 function = "tdm_ao_b"; 1928 bias-disable; 1929 drive-strength-microamp = <3000>; 1930 }; 1931 }; 1932 1933 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1934 mux { 1935 groups = "tdm_ao_b_dout2"; 1936 function = "tdm_ao_b"; 1937 bias-disable; 1938 drive-strength-microamp = <3000>; 1939 }; 1940 }; 1941 1942 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1943 mux { 1944 groups = "tdm_ao_b_fs"; 1945 function = "tdm_ao_b"; 1946 bias-disable; 1947 drive-strength-microamp = <3000>; 1948 }; 1949 }; 1950 1951 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1952 mux { 1953 groups = "tdm_ao_b_sclk"; 1954 function = "tdm_ao_b"; 1955 bias-disable; 1956 drive-strength-microamp = <3000>; 1957 }; 1958 }; 1959 1960 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1961 mux { 1962 groups = "tdm_ao_b_slv_fs"; 1963 function = "tdm_ao_b"; 1964 bias-disable; 1965 }; 1966 }; 1967 1968 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1969 mux { 1970 groups = "tdm_ao_b_slv_sclk"; 1971 function = "tdm_ao_b"; 1972 bias-disable; 1973 }; 1974 }; 1975 1976 uart_ao_a_pins: uart-a-ao { 1977 mux { 1978 groups = "uart_ao_a_tx", 1979 "uart_ao_a_rx"; 1980 function = "uart_ao_a"; 1981 bias-disable; 1982 }; 1983 }; 1984 1985 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1986 mux { 1987 groups = "uart_ao_a_cts", 1988 "uart_ao_a_rts"; 1989 function = "uart_ao_a"; 1990 bias-disable; 1991 }; 1992 }; 1993 1994 pwm_a_e_pins: pwm-a-e { 1995 mux { 1996 groups = "pwm_a_e"; 1997 function = "pwm_a_e"; 1998 bias-disable; 1999 }; 2000 }; 2001 2002 pwm_ao_a_pins: pwm-ao-a { 2003 mux { 2004 groups = "pwm_ao_a"; 2005 function = "pwm_ao_a"; 2006 bias-disable; 2007 }; 2008 }; 2009 2010 pwm_ao_b_pins: pwm-ao-b { 2011 mux { 2012 groups = "pwm_ao_b"; 2013 function = "pwm_ao_b"; 2014 bias-disable; 2015 }; 2016 }; 2017 2018 pwm_ao_c_4_pins: pwm-ao-c-4 { 2019 mux { 2020 groups = "pwm_ao_c_4"; 2021 function = "pwm_ao_c"; 2022 bias-disable; 2023 }; 2024 }; 2025 2026 pwm_ao_c_6_pins: pwm-ao-c-6 { 2027 mux { 2028 groups = "pwm_ao_c_6"; 2029 function = "pwm_ao_c"; 2030 bias-disable; 2031 }; 2032 }; 2033 2034 pwm_ao_d_5_pins: pwm-ao-d-5 { 2035 mux { 2036 groups = "pwm_ao_d_5"; 2037 function = "pwm_ao_d"; 2038 bias-disable; 2039 }; 2040 }; 2041 2042 pwm_ao_d_10_pins: pwm-ao-d-10 { 2043 mux { 2044 groups = "pwm_ao_d_10"; 2045 function = "pwm_ao_d"; 2046 bias-disable; 2047 }; 2048 }; 2049 2050 pwm_ao_d_e_pins: pwm-ao-d-e { 2051 mux { 2052 groups = "pwm_ao_d_e"; 2053 function = "pwm_ao_d"; 2054 }; 2055 }; 2056 2057 remote_input_ao_pins: remote-input-ao { 2058 mux { 2059 groups = "remote_ao_input"; 2060 function = "remote_ao_input"; 2061 bias-disable; 2062 }; 2063 }; 2064 }; 2065 }; 2066 2067 vrtc: rtc@0a8 { 2068 compatible = "amlogic,meson-vrtc"; 2069 reg = <0x0 0x000a8 0x0 0x4>; 2070 }; 2071 2072 cec_AO: cec@100 { 2073 compatible = "amlogic,meson-gx-ao-cec"; 2074 reg = <0x0 0x00100 0x0 0x14>; 2075 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2076 clocks = <&clkc_AO CLKID_AO_CEC>; 2077 clock-names = "core"; 2078 status = "disabled"; 2079 }; 2080 2081 sec_AO: ao-secure@140 { 2082 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2083 reg = <0x0 0x140 0x0 0x140>; 2084 amlogic,has-chip-id; 2085 }; 2086 2087 cecb_AO: cec@280 { 2088 compatible = "amlogic,meson-g12a-ao-cec"; 2089 reg = <0x0 0x00280 0x0 0x1c>; 2090 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2091 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2092 clock-names = "oscin"; 2093 status = "disabled"; 2094 }; 2095 2096 pwm_AO_cd: pwm@2000 { 2097 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2098 reg = <0x0 0x2000 0x0 0x20>; 2099 #pwm-cells = <3>; 2100 status = "disabled"; 2101 }; 2102 2103 uart_AO: serial@3000 { 2104 compatible = "amlogic,meson-gx-uart", 2105 "amlogic,meson-ao-uart"; 2106 reg = <0x0 0x3000 0x0 0x18>; 2107 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2108 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2109 clock-names = "xtal", "pclk", "baud"; 2110 status = "disabled"; 2111 }; 2112 2113 uart_AO_B: serial@4000 { 2114 compatible = "amlogic,meson-gx-uart", 2115 "amlogic,meson-ao-uart"; 2116 reg = <0x0 0x4000 0x0 0x18>; 2117 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2118 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2119 clock-names = "xtal", "pclk", "baud"; 2120 status = "disabled"; 2121 }; 2122 2123 i2c_AO: i2c@5000 { 2124 compatible = "amlogic,meson-axg-i2c"; 2125 status = "disabled"; 2126 reg = <0x0 0x05000 0x0 0x20>; 2127 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 clocks = <&clkc CLKID_I2C>; 2131 }; 2132 2133 pwm_AO_ab: pwm@7000 { 2134 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2135 reg = <0x0 0x7000 0x0 0x20>; 2136 #pwm-cells = <3>; 2137 status = "disabled"; 2138 }; 2139 2140 ir: ir@8000 { 2141 compatible = "amlogic,meson-gxbb-ir"; 2142 reg = <0x0 0x8000 0x0 0x20>; 2143 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2144 status = "disabled"; 2145 }; 2146 2147 saradc: adc@9000 { 2148 compatible = "amlogic,meson-g12a-saradc", 2149 "amlogic,meson-saradc"; 2150 reg = <0x0 0x9000 0x0 0x48>; 2151 #io-channel-cells = <1>; 2152 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2153 clocks = <&xtal>, 2154 <&clkc_AO CLKID_AO_SAR_ADC>, 2155 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2156 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2157 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2158 status = "disabled"; 2159 }; 2160 }; 2161 2162 vpu: vpu@ff900000 { 2163 compatible = "amlogic,meson-g12a-vpu"; 2164 reg = <0x0 0xff900000 0x0 0x100000>, 2165 <0x0 0xff63c000 0x0 0x1000>; 2166 reg-names = "vpu", "hhi"; 2167 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 amlogic,canvas = <&canvas>; 2171 2172 /* CVBS VDAC output port */ 2173 cvbs_vdac_port: port@0 { 2174 reg = <0>; 2175 }; 2176 2177 /* HDMI-TX output port */ 2178 hdmi_tx_port: port@1 { 2179 reg = <1>; 2180 2181 hdmi_tx_out: endpoint { 2182 remote-endpoint = <&hdmi_tx_in>; 2183 }; 2184 }; 2185 }; 2186 2187 gic: interrupt-controller@ffc01000 { 2188 compatible = "arm,gic-400"; 2189 reg = <0x0 0xffc01000 0 0x1000>, 2190 <0x0 0xffc02000 0 0x2000>, 2191 <0x0 0xffc04000 0 0x2000>, 2192 <0x0 0xffc06000 0 0x2000>; 2193 interrupt-controller; 2194 interrupts = <GIC_PPI 9 2195 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2196 #interrupt-cells = <3>; 2197 #address-cells = <0>; 2198 }; 2199 2200 cbus: bus@ffd00000 { 2201 compatible = "simple-bus"; 2202 reg = <0x0 0xffd00000 0x0 0x100000>; 2203 #address-cells = <2>; 2204 #size-cells = <2>; 2205 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2206 2207 reset: reset-controller@1004 { 2208 compatible = "amlogic,meson-axg-reset"; 2209 reg = <0x0 0x1004 0x0 0x9c>; 2210 #reset-cells = <1>; 2211 }; 2212 2213 gpio_intc: interrupt-controller@f080 { 2214 compatible = "amlogic,meson-g12a-gpio-intc", 2215 "amlogic,meson-gpio-intc"; 2216 reg = <0x0 0xf080 0x0 0x10>; 2217 interrupt-controller; 2218 #interrupt-cells = <2>; 2219 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2220 }; 2221 2222 pwm_ef: pwm@19000 { 2223 compatible = "amlogic,meson-g12a-ee-pwm"; 2224 reg = <0x0 0x19000 0x0 0x20>; 2225 #pwm-cells = <3>; 2226 status = "disabled"; 2227 }; 2228 2229 pwm_cd: pwm@1a000 { 2230 compatible = "amlogic,meson-g12a-ee-pwm"; 2231 reg = <0x0 0x1a000 0x0 0x20>; 2232 #pwm-cells = <3>; 2233 status = "disabled"; 2234 }; 2235 2236 pwm_ab: pwm@1b000 { 2237 compatible = "amlogic,meson-g12a-ee-pwm"; 2238 reg = <0x0 0x1b000 0x0 0x20>; 2239 #pwm-cells = <3>; 2240 status = "disabled"; 2241 }; 2242 2243 i2c3: i2c@1c000 { 2244 compatible = "amlogic,meson-axg-i2c"; 2245 status = "disabled"; 2246 reg = <0x0 0x1c000 0x0 0x20>; 2247 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2248 #address-cells = <1>; 2249 #size-cells = <0>; 2250 clocks = <&clkc CLKID_I2C>; 2251 }; 2252 2253 i2c2: i2c@1d000 { 2254 compatible = "amlogic,meson-axg-i2c"; 2255 status = "disabled"; 2256 reg = <0x0 0x1d000 0x0 0x20>; 2257 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2258 #address-cells = <1>; 2259 #size-cells = <0>; 2260 clocks = <&clkc CLKID_I2C>; 2261 }; 2262 2263 i2c1: i2c@1e000 { 2264 compatible = "amlogic,meson-axg-i2c"; 2265 status = "disabled"; 2266 reg = <0x0 0x1e000 0x0 0x20>; 2267 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2268 #address-cells = <1>; 2269 #size-cells = <0>; 2270 clocks = <&clkc CLKID_I2C>; 2271 }; 2272 2273 i2c0: i2c@1f000 { 2274 compatible = "amlogic,meson-axg-i2c"; 2275 status = "disabled"; 2276 reg = <0x0 0x1f000 0x0 0x20>; 2277 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2278 #address-cells = <1>; 2279 #size-cells = <0>; 2280 clocks = <&clkc CLKID_I2C>; 2281 }; 2282 2283 clk_msr: clock-measure@18000 { 2284 compatible = "amlogic,meson-g12a-clk-measure"; 2285 reg = <0x0 0x18000 0x0 0x10>; 2286 }; 2287 2288 uart_C: serial@22000 { 2289 compatible = "amlogic,meson-gx-uart"; 2290 reg = <0x0 0x22000 0x0 0x18>; 2291 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2292 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2293 clock-names = "xtal", "pclk", "baud"; 2294 status = "disabled"; 2295 }; 2296 2297 uart_B: serial@23000 { 2298 compatible = "amlogic,meson-gx-uart"; 2299 reg = <0x0 0x23000 0x0 0x18>; 2300 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2301 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2302 clock-names = "xtal", "pclk", "baud"; 2303 status = "disabled"; 2304 }; 2305 2306 uart_A: serial@24000 { 2307 compatible = "amlogic,meson-gx-uart"; 2308 reg = <0x0 0x24000 0x0 0x18>; 2309 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2310 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2311 clock-names = "xtal", "pclk", "baud"; 2312 status = "disabled"; 2313 }; 2314 }; 2315 2316 sd_emmc_a: sd@ffe03000 { 2317 compatible = "amlogic,meson-axg-mmc"; 2318 reg = <0x0 0xffe03000 0x0 0x800>; 2319 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2320 status = "disabled"; 2321 clocks = <&clkc CLKID_SD_EMMC_A>, 2322 <&clkc CLKID_SD_EMMC_A_CLK0>, 2323 <&clkc CLKID_FCLK_DIV2>; 2324 clock-names = "core", "clkin0", "clkin1"; 2325 resets = <&reset RESET_SD_EMMC_A>; 2326 }; 2327 2328 sd_emmc_b: sd@ffe05000 { 2329 compatible = "amlogic,meson-axg-mmc"; 2330 reg = <0x0 0xffe05000 0x0 0x800>; 2331 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2332 status = "disabled"; 2333 clocks = <&clkc CLKID_SD_EMMC_B>, 2334 <&clkc CLKID_SD_EMMC_B_CLK0>, 2335 <&clkc CLKID_FCLK_DIV2>; 2336 clock-names = "core", "clkin0", "clkin1"; 2337 resets = <&reset RESET_SD_EMMC_B>; 2338 }; 2339 2340 sd_emmc_c: mmc@ffe07000 { 2341 compatible = "amlogic,meson-axg-mmc"; 2342 reg = <0x0 0xffe07000 0x0 0x800>; 2343 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2344 status = "disabled"; 2345 clocks = <&clkc CLKID_SD_EMMC_C>, 2346 <&clkc CLKID_SD_EMMC_C_CLK0>, 2347 <&clkc CLKID_FCLK_DIV2>; 2348 clock-names = "core", "clkin0", "clkin1"; 2349 resets = <&reset RESET_SD_EMMC_C>; 2350 }; 2351 2352 usb: usb@ffe09000 { 2353 status = "disabled"; 2354 compatible = "amlogic,meson-g12a-usb-ctrl"; 2355 reg = <0x0 0xffe09000 0x0 0xa0>; 2356 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2357 #address-cells = <2>; 2358 #size-cells = <2>; 2359 ranges; 2360 2361 clocks = <&clkc CLKID_USB>; 2362 resets = <&reset RESET_USB>; 2363 2364 dr_mode = "otg"; 2365 2366 phys = <&usb2_phy0>, <&usb2_phy1>, 2367 <&usb3_pcie_phy PHY_TYPE_USB3>; 2368 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2369 2370 dwc2: usb@ff400000 { 2371 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2372 reg = <0x0 0xff400000 0x0 0x40000>; 2373 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2374 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2375 clock-names = "otg"; 2376 phys = <&usb2_phy1>; 2377 phy-names = "usb2-phy"; 2378 dr_mode = "peripheral"; 2379 g-rx-fifo-size = <192>; 2380 g-np-tx-fifo-size = <128>; 2381 g-tx-fifo-size = <128 128 16 16 16>; 2382 }; 2383 2384 dwc3: usb@ff500000 { 2385 compatible = "snps,dwc3"; 2386 reg = <0x0 0xff500000 0x0 0x100000>; 2387 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2388 dr_mode = "host"; 2389 snps,dis_u2_susphy_quirk; 2390 snps,quirk-frame-length-adjustment = <0x20>; 2391 snps,parkmode-disable-ss-quirk; 2392 }; 2393 }; 2394 2395 mali: gpu@ffe40000 { 2396 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2397 reg = <0x0 0xffe40000 0x0 0x40000>; 2398 interrupt-parent = <&gic>; 2399 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2402 interrupt-names = "gpu", "mmu", "job"; 2403 clocks = <&clkc CLKID_MALI>; 2404 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2405 2406 /* 2407 * Mali clocking is provided by two identical clock paths 2408 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2409 * free mux to safely change frequency while running. 2410 */ 2411 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2412 <&clkc CLKID_MALI_0>, 2413 <&clkc CLKID_MALI>; /* Glitch free mux */ 2414 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2415 <0>, /* Do Nothing */ 2416 <&clkc CLKID_MALI_0>; 2417 assigned-clock-rates = <0>, /* Do Nothing */ 2418 <800000000>, 2419 <0>; /* Do Nothing */ 2420 }; 2421 }; 2422 2423 timer { 2424 compatible = "arm,armv8-timer"; 2425 interrupts = <GIC_PPI 13 2426 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2427 <GIC_PPI 14 2428 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2429 <GIC_PPI 11 2430 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2431 <GIC_PPI 10 2432 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2433 arm,no-tick-in-suspend; 2434 }; 2435 2436 xtal: xtal-clk { 2437 compatible = "fixed-clock"; 2438 clock-frequency = <24000000>; 2439 clock-output-names = "xtal"; 2440 #clock-cells = <0>; 2441 }; 2442 2443}; 2444