1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a72"; 38 reg = <0x1>; 39 enable-method = "psci"; 40 clocks = <&clockgen 1 0>; 41 next-level-cache = <&l2>; 42 cpu-idle-states = <&CPU_PW20>; 43 #cooling-cells = <2>; 44 }; 45 46 l2: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 idle-states { 52 /* 53 * PSCI node is not added default, U-boot will add missing 54 * parts if it determines to use PSCI. 55 */ 56 entry-method = "arm,psci"; 57 58 CPU_PW20: cpu-pw20 { 59 compatible = "arm,idle-state"; 60 idle-state-name = "PW20"; 61 arm,psci-suspend-param = <0x0>; 62 entry-latency-us = <2000>; 63 exit-latency-us = <2000>; 64 min-residency-us = <6000>; 65 }; 66 }; 67 68 sysclk: sysclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "sysclk"; 73 }; 74 75 osc_27m: clock-osc-27m { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <27000000>; 79 clock-output-names = "phy_27m"; 80 }; 81 82 dpclk: clock-controller@f1f0000 { 83 compatible = "fsl,ls1028a-plldig"; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; 85 #clock-cells = <1>; 86 clocks = <&osc_27m>; 87 }; 88 89 aclk: clock-axi { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <650000000>; 93 clock-output-names= "aclk"; 94 }; 95 96 pclk: clock-apb { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <650000000>; 100 clock-output-names= "pclk"; 101 }; 102 103 reboot { 104 compatible ="syscon-reboot"; 105 regmap = <&rst>; 106 offset = <0>; 107 mask = <0x02>; 108 }; 109 110 timer { 111 compatible = "arm,armv8-timer"; 112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 113 IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 115 IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 117 IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 119 IRQ_TYPE_LEVEL_LOW)>; 120 }; 121 122 pmu { 123 compatible = "arm,cortex-a72-pmu"; 124 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 gic: interrupt-controller@6000000 { 128 compatible= "arm,gic-v3"; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 133 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 134 #interrupt-cells= <3>; 135 interrupt-controller; 136 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 137 IRQ_TYPE_LEVEL_LOW)>; 138 its: gic-its@6020000 { 139 compatible = "arm,gic-v3-its"; 140 msi-controller; 141 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 142 }; 143 }; 144 145 soc: soc { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 ddr: memory-controller@1080000 { 152 compatible = "fsl,qoriq-memory-controller"; 153 reg = <0x0 0x1080000 0x0 0x1000>; 154 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 155 little-endian; 156 }; 157 158 dcfg: syscon@1e00000 { 159 compatible = "fsl,ls1028a-dcfg", "syscon"; 160 reg = <0x0 0x1e00000 0x0 0x10000>; 161 little-endian; 162 }; 163 164 rst: syscon@1e60000 { 165 compatible = "syscon"; 166 reg = <0x0 0x1e60000 0x0 0x10000>; 167 little-endian; 168 }; 169 170 scfg: syscon@1fc0000 { 171 compatible = "fsl,ls1028a-scfg", "syscon"; 172 reg = <0x0 0x1fc0000 0x0 0x10000>; 173 big-endian; 174 }; 175 176 clockgen: clock-controller@1300000 { 177 compatible = "fsl,ls1028a-clockgen"; 178 reg = <0x0 0x1300000 0x0 0xa0000>; 179 #clock-cells = <2>; 180 clocks = <&sysclk>; 181 }; 182 183 i2c0: i2c@2000000 { 184 compatible = "fsl,vf610-i2c"; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 reg = <0x0 0x2000000 0x0 0x10000>; 188 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&clockgen 4 3>; 190 status = "disabled"; 191 }; 192 193 i2c1: i2c@2010000 { 194 compatible = "fsl,vf610-i2c"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 reg = <0x0 0x2010000 0x0 0x10000>; 198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&clockgen 4 3>; 200 status = "disabled"; 201 }; 202 203 i2c2: i2c@2020000 { 204 compatible = "fsl,vf610-i2c"; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 reg = <0x0 0x2020000 0x0 0x10000>; 208 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&clockgen 4 3>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@2030000 { 214 compatible = "fsl,vf610-i2c"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0x0 0x2030000 0x0 0x10000>; 218 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&clockgen 4 3>; 220 status = "disabled"; 221 }; 222 223 i2c4: i2c@2040000 { 224 compatible = "fsl,vf610-i2c"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 reg = <0x0 0x2040000 0x0 0x10000>; 228 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&clockgen 4 3>; 230 status = "disabled"; 231 }; 232 233 i2c5: i2c@2050000 { 234 compatible = "fsl,vf610-i2c"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 reg = <0x0 0x2050000 0x0 0x10000>; 238 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&clockgen 4 3>; 240 status = "disabled"; 241 }; 242 243 i2c6: i2c@2060000 { 244 compatible = "fsl,vf610-i2c"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 reg = <0x0 0x2060000 0x0 0x10000>; 248 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&clockgen 4 3>; 250 status = "disabled"; 251 }; 252 253 i2c7: i2c@2070000 { 254 compatible = "fsl,vf610-i2c"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 reg = <0x0 0x2070000 0x0 0x10000>; 258 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&clockgen 4 3>; 260 status = "disabled"; 261 }; 262 263 esdhc: mmc@2140000 { 264 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 265 reg = <0x0 0x2140000 0x0 0x10000>; 266 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 267 clock-frequency = <0>; /* fixed up by bootloader */ 268 clocks = <&clockgen 2 1>; 269 voltage-ranges = <1800 1800 3300 3300>; 270 sdhci,auto-cmd12; 271 little-endian; 272 bus-width = <4>; 273 status = "disabled"; 274 }; 275 276 esdhc1: mmc@2150000 { 277 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 278 reg = <0x0 0x2150000 0x0 0x10000>; 279 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 280 clock-frequency = <0>; /* fixed up by bootloader */ 281 clocks = <&clockgen 2 1>; 282 voltage-ranges = <1800 1800 3300 3300>; 283 sdhci,auto-cmd12; 284 broken-cd; 285 little-endian; 286 bus-width = <4>; 287 status = "disabled"; 288 }; 289 290 can0: can@2180000 { 291 compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; 292 reg = <0x0 0x2180000 0x0 0x10000>; 293 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&sysclk>, <&clockgen 4 1>; 295 clock-names = "ipg", "per"; 296 status = "disabled"; 297 }; 298 299 can1: can@2190000 { 300 compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; 301 reg = <0x0 0x2190000 0x0 0x10000>; 302 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&sysclk>, <&clockgen 4 1>; 304 clock-names = "ipg", "per"; 305 status = "disabled"; 306 }; 307 308 duart0: serial@21c0500 { 309 compatible = "fsl,ns16550", "ns16550a"; 310 reg = <0x00 0x21c0500 0x0 0x100>; 311 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clockgen 4 1>; 313 status = "disabled"; 314 }; 315 316 duart1: serial@21c0600 { 317 compatible = "fsl,ns16550", "ns16550a"; 318 reg = <0x00 0x21c0600 0x0 0x100>; 319 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&clockgen 4 1>; 321 status = "disabled"; 322 }; 323 324 edma0: dma-controller@22c0000 { 325 #dma-cells = <2>; 326 compatible = "fsl,vf610-edma"; 327 reg = <0x0 0x22c0000 0x0 0x10000>, 328 <0x0 0x22d0000 0x0 0x10000>, 329 <0x0 0x22e0000 0x0 0x10000>; 330 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 332 interrupt-names = "edma-tx", "edma-err"; 333 dma-channels = <32>; 334 clock-names = "dmamux0", "dmamux1"; 335 clocks = <&clockgen 4 1>, 336 <&clockgen 4 1>; 337 }; 338 339 gpio1: gpio@2300000 { 340 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 341 reg = <0x0 0x2300000 0x0 0x10000>; 342 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 little-endian; 348 }; 349 350 gpio2: gpio@2310000 { 351 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 352 reg = <0x0 0x2310000 0x0 0x10000>; 353 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 little-endian; 359 }; 360 361 gpio3: gpio@2320000 { 362 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 363 reg = <0x0 0x2320000 0x0 0x10000>; 364 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 little-endian; 370 }; 371 372 usb0: usb@3100000 { 373 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 374 reg = <0x0 0x3100000 0x0 0x10000>; 375 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 376 dr_mode = "host"; 377 snps,dis_rxdet_inp3_quirk; 378 snps,quirk-frame-length-adjustment = <0x20>; 379 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 380 }; 381 382 usb1: usb@3110000 { 383 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 384 reg = <0x0 0x3110000 0x0 0x10000>; 385 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 386 dr_mode = "host"; 387 snps,dis_rxdet_inp3_quirk; 388 snps,quirk-frame-length-adjustment = <0x20>; 389 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 390 }; 391 392 sata: sata@3200000 { 393 compatible = "fsl,ls1028a-ahci"; 394 reg = <0x0 0x3200000 0x0 0x10000>, 395 <0x7 0x100520 0x0 0x4>; 396 reg-names = "ahci", "sata-ecc"; 397 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clockgen 4 1>; 399 status = "disabled"; 400 }; 401 402 smmu: iommu@5000000 { 403 compatible = "arm,mmu-500"; 404 reg = <0 0x5000000 0 0x800000>; 405 #global-interrupts = <8>; 406 #iommu-cells = <1>; 407 stream-match-mask = <0x7c00>; 408 /* global secure fault */ 409 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 410 /* combined secure interrupt */ 411 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 412 /* global non-secure fault */ 413 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 414 /* combined non-secure interrupt */ 415 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 416 /* performance counter interrupts 0-7 */ 417 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 419 /* per context interrupt, 64 interrupts */ 420 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 452 }; 453 454 crypto: crypto@8000000 { 455 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 456 fsl,sec-era = <10>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 ranges = <0x0 0x00 0x8000000 0x100000>; 460 reg = <0x00 0x8000000 0x0 0x100000>; 461 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 462 dma-coherent; 463 464 sec_jr0: jr@10000 { 465 compatible = "fsl,sec-v5.0-job-ring", 466 "fsl,sec-v4.0-job-ring"; 467 reg = <0x10000 0x10000>; 468 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 469 }; 470 471 sec_jr1: jr@20000 { 472 compatible = "fsl,sec-v5.0-job-ring", 473 "fsl,sec-v4.0-job-ring"; 474 reg = <0x20000 0x10000>; 475 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 476 }; 477 478 sec_jr2: jr@30000 { 479 compatible = "fsl,sec-v5.0-job-ring", 480 "fsl,sec-v4.0-job-ring"; 481 reg = <0x30000 0x10000>; 482 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 483 }; 484 485 sec_jr3: jr@40000 { 486 compatible = "fsl,sec-v5.0-job-ring", 487 "fsl,sec-v4.0-job-ring"; 488 reg = <0x40000 0x10000>; 489 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 490 }; 491 }; 492 493 qdma: dma-controller@8380000 { 494 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 495 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 496 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 497 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 498 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "qdma-error", "qdma-queue0", 504 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 505 dma-channels = <8>; 506 block-number = <1>; 507 block-offset = <0x10000>; 508 fsl,dma-queues = <2>; 509 status-sizes = <64>; 510 queue-sizes = <64 64>; 511 }; 512 513 cluster1_core0_watchdog: watchdog@c000000 { 514 compatible = "arm,sp805", "arm,primecell"; 515 reg = <0x0 0xc000000 0x0 0x1000>; 516 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 517 clock-names = "wdog_clk", "apb_pclk"; 518 }; 519 520 cluster1_core1_watchdog: watchdog@c010000 { 521 compatible = "arm,sp805", "arm,primecell"; 522 reg = <0x0 0xc010000 0x0 0x1000>; 523 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 524 clock-names = "wdog_clk", "apb_pclk"; 525 }; 526 527 sai1: audio-controller@f100000 { 528 #sound-dai-cells = <0>; 529 compatible = "fsl,vf610-sai"; 530 reg = <0x0 0xf100000 0x0 0x10000>; 531 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 533 <&clockgen 4 1>, <&clockgen 4 1>; 534 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 535 dma-names = "tx", "rx"; 536 dmas = <&edma0 1 4>, 537 <&edma0 1 3>; 538 status = "disabled"; 539 }; 540 541 sai2: audio-controller@f110000 { 542 #sound-dai-cells = <0>; 543 compatible = "fsl,vf610-sai"; 544 reg = <0x0 0xf110000 0x0 0x10000>; 545 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 547 <&clockgen 4 1>, <&clockgen 4 1>; 548 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 549 dma-names = "tx", "rx"; 550 dmas = <&edma0 1 6>, 551 <&edma0 1 5>; 552 status = "disabled"; 553 }; 554 555 sai4: audio-controller@f130000 { 556 #sound-dai-cells = <0>; 557 compatible = "fsl,vf610-sai"; 558 reg = <0x0 0xf130000 0x0 0x10000>; 559 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 561 <&clockgen 4 1>, <&clockgen 4 1>; 562 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 563 dma-names = "tx", "rx"; 564 dmas = <&edma0 1 10>, 565 <&edma0 1 9>; 566 status = "disabled"; 567 }; 568 569 tmu: tmu@1f00000 { 570 compatible = "fsl,qoriq-tmu"; 571 reg = <0x0 0x1f80000 0x0 0x10000>; 572 interrupts = <0 23 0x4>; 573 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 574 fsl,tmu-calibration = <0x00000000 0x00000024 575 0x00000001 0x0000002b 576 0x00000002 0x00000031 577 0x00000003 0x00000038 578 0x00000004 0x0000003f 579 0x00000005 0x00000045 580 0x00000006 0x0000004c 581 0x00000007 0x00000053 582 0x00000008 0x00000059 583 0x00000009 0x00000060 584 0x0000000a 0x00000066 585 0x0000000b 0x0000006d 586 587 0x00010000 0x0000001c 588 0x00010001 0x00000024 589 0x00010002 0x0000002c 590 0x00010003 0x00000035 591 0x00010004 0x0000003d 592 0x00010005 0x00000045 593 0x00010006 0x0000004d 594 0x00010007 0x00000055 595 0x00010008 0x0000005e 596 0x00010009 0x00000066 597 0x0001000a 0x0000006e 598 599 0x00020000 0x00000018 600 0x00020001 0x00000022 601 0x00020002 0x0000002d 602 0x00020003 0x00000038 603 0x00020004 0x00000043 604 0x00020005 0x0000004d 605 0x00020006 0x00000058 606 0x00020007 0x00000063 607 0x00020008 0x0000006e 608 609 0x00030000 0x00000010 610 0x00030001 0x0000001c 611 0x00030002 0x00000029 612 0x00030003 0x00000036 613 0x00030004 0x00000042 614 0x00030005 0x0000004f 615 0x00030006 0x0000005b 616 0x00030007 0x00000068>; 617 little-endian; 618 #thermal-sensor-cells = <1>; 619 }; 620 621 thermal-zones { 622 core-cluster { 623 polling-delay-passive = <1000>; 624 polling-delay = <5000>; 625 thermal-sensors = <&tmu 0>; 626 627 trips { 628 core_cluster_alert: core-cluster-alert { 629 temperature = <85000>; 630 hysteresis = <2000>; 631 type = "passive"; 632 }; 633 634 core_cluster_crit: core-cluster-crit { 635 temperature = <95000>; 636 hysteresis = <2000>; 637 type = "critical"; 638 }; 639 }; 640 641 cooling-maps { 642 map0 { 643 trip = <&core_cluster_alert>; 644 cooling-device = 645 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 646 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 647 }; 648 }; 649 }; 650 }; 651 652 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 653 compatible = "pci-host-ecam-generic"; 654 reg = <0x01 0xf0000000 0x0 0x100000>; 655 #address-cells = <3>; 656 #size-cells = <2>; 657 #interrupt-cells = <1>; 658 msi-parent = <&its>; 659 device_type = "pci"; 660 bus-range = <0x0 0x0>; 661 dma-coherent; 662 msi-map = <0 &its 0x17 0xe>; 663 iommu-map = <0 &smmu 0x17 0xe>; 664 /* PF0-6 BAR0 - non-prefetchable memory */ 665 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 666 /* PF0-6 BAR2 - prefetchable memory */ 667 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 668 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 669 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 670 /* PF0: VF0-1 BAR2 - prefetchable memory */ 671 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 672 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 673 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 674 /* PF1: VF0-1 BAR2 - prefetchable memory */ 675 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 676 677 enetc_port0: ethernet@0,0 { 678 compatible = "fsl,enetc"; 679 reg = <0x000000 0 0 0 0>; 680 }; 681 enetc_port1: ethernet@0,1 { 682 compatible = "fsl,enetc"; 683 reg = <0x000100 0 0 0 0>; 684 }; 685 enetc_mdio_pf3: mdio@0,3 { 686 compatible = "fsl,enetc-mdio"; 687 reg = <0x000300 0 0 0 0>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 }; 691 ethernet@0,4 { 692 compatible = "fsl,enetc-ptp"; 693 reg = <0x000400 0 0 0 0>; 694 clocks = <&clockgen 2 3>; 695 little-endian; 696 }; 697 }; 698 }; 699 700 malidp0: display@f080000 { 701 compatible = "arm,mali-dp500"; 702 reg = <0x0 0xf080000 0x0 0x10000>; 703 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 704 <0 223 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "DE", "SE"; 706 clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>; 707 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 708 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 709 arm,malidp-arqos-value = <0xd000d000>; 710 711 port { 712 dp0_out: endpoint { 713 714 }; 715 }; 716 }; 717}; 718