1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2017 NXP 7 * 8 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9 * 10 */ 11 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/ { 16 compatible = "fsl,ls2080a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 serial2 = &serial2; 26 serial3 = &serial3; 27 }; 28 29 cpu: cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 reg = <0x00000000 0x80000000 0 0x80000000>; 37 /* DRAM space - 1, size : 2 GB DRAM */ 38 }; 39 40 sysclk: sysclk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <100000000>; 44 clock-output-names = "sysclk"; 45 }; 46 47 gic: interrupt-controller@6000000 { 48 compatible = "arm,gic-v3"; 49 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 50 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 51 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 52 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 53 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 54 #interrupt-cells = <3>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 ranges; 58 interrupt-controller; 59 interrupts = <1 9 0x4>; 60 61 its: gic-its@6020000 { 62 compatible = "arm,gic-v3-its"; 63 msi-controller; 64 reg = <0x0 0x6020000 0 0x20000>; 65 }; 66 }; 67 68 rstcr: syscon@1e60000 { 69 compatible = "fsl,ls2080a-rstcr", "syscon"; 70 reg = <0x0 0x1e60000 0x0 0x4>; 71 }; 72 73 reboot { 74 compatible ="syscon-reboot"; 75 regmap = <&rstcr>; 76 offset = <0x0>; 77 mask = <0x2>; 78 }; 79 80 thermal-zones { 81 cpu_thermal: cpu-thermal { 82 polling-delay-passive = <1000>; 83 polling-delay = <5000>; 84 85 thermal-sensors = <&tmu 4>; 86 87 trips { 88 cpu_alert: cpu-alert { 89 temperature = <75000>; 90 hysteresis = <2000>; 91 type = "passive"; 92 }; 93 cpu_crit: cpu-crit { 94 temperature = <85000>; 95 hysteresis = <2000>; 96 type = "critical"; 97 }; 98 }; 99 100 cooling-maps { 101 map0 { 102 trip = <&cpu_alert>; 103 cooling-device = 104 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 105 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 106 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 107 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 108 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 109 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 110 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 111 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 112 }; 113 }; 114 }; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 120 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 121 <1 11 4>, /* Virtual PPI, active-low */ 122 <1 10 4>; /* Hypervisor PPI, active-low */ 123 fsl,erratum-a008585; 124 }; 125 126 pmu { 127 compatible = "arm,armv8-pmuv3"; 128 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 129 }; 130 131 psci { 132 compatible = "arm,psci-0.2"; 133 method = "smc"; 134 }; 135 136 soc { 137 compatible = "simple-bus"; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 142 143 clockgen: clocking@1300000 { 144 compatible = "fsl,ls2080a-clockgen"; 145 reg = <0 0x1300000 0 0xa0000>; 146 #clock-cells = <2>; 147 clocks = <&sysclk>; 148 }; 149 150 dcfg: dcfg@1e00000 { 151 compatible = "fsl,ls2080a-dcfg", "syscon"; 152 reg = <0x0 0x1e00000 0x0 0x10000>; 153 little-endian; 154 }; 155 156 tmu: tmu@1f80000 { 157 compatible = "fsl,qoriq-tmu"; 158 reg = <0x0 0x1f80000 0x0 0x10000>; 159 interrupts = <0 23 0x4>; 160 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 161 fsl,tmu-calibration = <0x00000000 0x00000026 162 0x00000001 0x0000002d 163 0x00000002 0x00000032 164 0x00000003 0x00000039 165 0x00000004 0x0000003f 166 0x00000005 0x00000046 167 0x00000006 0x0000004d 168 0x00000007 0x00000054 169 0x00000008 0x0000005a 170 0x00000009 0x00000061 171 0x0000000a 0x0000006a 172 0x0000000b 0x00000071 173 174 0x00010000 0x00000025 175 0x00010001 0x0000002c 176 0x00010002 0x00000035 177 0x00010003 0x0000003d 178 0x00010004 0x00000045 179 0x00010005 0x0000004e 180 0x00010006 0x00000057 181 0x00010007 0x00000061 182 0x00010008 0x0000006b 183 0x00010009 0x00000076 184 185 0x00020000 0x00000029 186 0x00020001 0x00000033 187 0x00020002 0x0000003d 188 0x00020003 0x00000049 189 0x00020004 0x00000056 190 0x00020005 0x00000061 191 0x00020006 0x0000006d 192 193 0x00030000 0x00000021 194 0x00030001 0x0000002a 195 0x00030002 0x0000003c 196 0x00030003 0x0000004e>; 197 little-endian; 198 #thermal-sensor-cells = <1>; 199 }; 200 201 serial0: serial@21c0500 { 202 compatible = "fsl,ns16550", "ns16550a"; 203 reg = <0x0 0x21c0500 0x0 0x100>; 204 clocks = <&clockgen 4 3>; 205 interrupts = <0 32 0x4>; /* Level high type */ 206 }; 207 208 serial1: serial@21c0600 { 209 compatible = "fsl,ns16550", "ns16550a"; 210 reg = <0x0 0x21c0600 0x0 0x100>; 211 clocks = <&clockgen 4 3>; 212 interrupts = <0 32 0x4>; /* Level high type */ 213 }; 214 215 serial2: serial@21d0500 { 216 compatible = "fsl,ns16550", "ns16550a"; 217 reg = <0x0 0x21d0500 0x0 0x100>; 218 clocks = <&clockgen 4 3>; 219 interrupts = <0 33 0x4>; /* Level high type */ 220 }; 221 222 serial3: serial@21d0600 { 223 compatible = "fsl,ns16550", "ns16550a"; 224 reg = <0x0 0x21d0600 0x0 0x100>; 225 clocks = <&clockgen 4 3>; 226 interrupts = <0 33 0x4>; /* Level high type */ 227 }; 228 229 cluster1_core0_watchdog: wdt@c000000 { 230 compatible = "arm,sp805", "arm,primecell"; 231 reg = <0x0 0xc000000 0x0 0x1000>; 232 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 233 clock-names = "wdog_clk", "apb_pclk"; 234 }; 235 236 cluster1_core1_watchdog: wdt@c010000 { 237 compatible = "arm,sp805", "arm,primecell"; 238 reg = <0x0 0xc010000 0x0 0x1000>; 239 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 240 clock-names = "wdog_clk", "apb_pclk"; 241 }; 242 243 cluster2_core0_watchdog: wdt@c100000 { 244 compatible = "arm,sp805", "arm,primecell"; 245 reg = <0x0 0xc100000 0x0 0x1000>; 246 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 247 clock-names = "wdog_clk", "apb_pclk"; 248 }; 249 250 cluster2_core1_watchdog: wdt@c110000 { 251 compatible = "arm,sp805", "arm,primecell"; 252 reg = <0x0 0xc110000 0x0 0x1000>; 253 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 254 clock-names = "wdog_clk", "apb_pclk"; 255 }; 256 257 cluster3_core0_watchdog: wdt@c200000 { 258 compatible = "arm,sp805", "arm,primecell"; 259 reg = <0x0 0xc200000 0x0 0x1000>; 260 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 261 clock-names = "wdog_clk", "apb_pclk"; 262 }; 263 264 cluster3_core1_watchdog: wdt@c210000 { 265 compatible = "arm,sp805", "arm,primecell"; 266 reg = <0x0 0xc210000 0x0 0x1000>; 267 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 268 clock-names = "wdog_clk", "apb_pclk"; 269 }; 270 271 cluster4_core0_watchdog: wdt@c300000 { 272 compatible = "arm,sp805", "arm,primecell"; 273 reg = <0x0 0xc300000 0x0 0x1000>; 274 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 275 clock-names = "wdog_clk", "apb_pclk"; 276 }; 277 278 cluster4_core1_watchdog: wdt@c310000 { 279 compatible = "arm,sp805", "arm,primecell"; 280 reg = <0x0 0xc310000 0x0 0x1000>; 281 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 282 clock-names = "wdog_clk", "apb_pclk"; 283 }; 284 285 crypto: crypto@8000000 { 286 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 287 fsl,sec-era = <8>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0x0 0x00 0x8000000 0x100000>; 291 reg = <0x00 0x8000000 0x0 0x100000>; 292 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 293 dma-coherent; 294 295 sec_jr0: jr@10000 { 296 compatible = "fsl,sec-v5.0-job-ring", 297 "fsl,sec-v4.0-job-ring"; 298 reg = <0x10000 0x10000>; 299 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 300 }; 301 302 sec_jr1: jr@20000 { 303 compatible = "fsl,sec-v5.0-job-ring", 304 "fsl,sec-v4.0-job-ring"; 305 reg = <0x20000 0x10000>; 306 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 307 }; 308 309 sec_jr2: jr@30000 { 310 compatible = "fsl,sec-v5.0-job-ring", 311 "fsl,sec-v4.0-job-ring"; 312 reg = <0x30000 0x10000>; 313 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 sec_jr3: jr@40000 { 317 compatible = "fsl,sec-v5.0-job-ring", 318 "fsl,sec-v4.0-job-ring"; 319 reg = <0x40000 0x10000>; 320 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 321 }; 322 }; 323 324 console@8340020 { 325 compatible = "fsl,dpaa2-console"; 326 reg = <0x00000000 0x08340020 0 0x2>; 327 }; 328 329 ptp-timer@8b95000 { 330 compatible = "fsl,dpaa2-ptp"; 331 reg = <0x0 0x8b95000 0x0 0x100>; 332 clocks = <&clockgen 4 1>; 333 little-endian; 334 fsl,extts-fifo; 335 }; 336 337 fsl_mc: fsl-mc@80c000000 { 338 compatible = "fsl,qoriq-mc"; 339 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 340 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 341 msi-parent = <&its>; 342 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 343 dma-coherent; 344 #address-cells = <3>; 345 #size-cells = <1>; 346 347 /* 348 * Region type 0x0 - MC portals 349 * Region type 0x1 - QBMAN portals 350 */ 351 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 352 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 353 354 /* 355 * Define the maximum number of MACs present on the SoC. 356 */ 357 dpmacs { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 dpmac1: dpmac@1 { 362 compatible = "fsl,qoriq-mc-dpmac"; 363 reg = <0x1>; 364 }; 365 366 dpmac2: dpmac@2 { 367 compatible = "fsl,qoriq-mc-dpmac"; 368 reg = <0x2>; 369 }; 370 371 dpmac3: dpmac@3 { 372 compatible = "fsl,qoriq-mc-dpmac"; 373 reg = <0x3>; 374 }; 375 376 dpmac4: dpmac@4 { 377 compatible = "fsl,qoriq-mc-dpmac"; 378 reg = <0x4>; 379 }; 380 381 dpmac5: dpmac@5 { 382 compatible = "fsl,qoriq-mc-dpmac"; 383 reg = <0x5>; 384 }; 385 386 dpmac6: dpmac@6 { 387 compatible = "fsl,qoriq-mc-dpmac"; 388 reg = <0x6>; 389 }; 390 391 dpmac7: dpmac@7 { 392 compatible = "fsl,qoriq-mc-dpmac"; 393 reg = <0x7>; 394 }; 395 396 dpmac8: dpmac@8 { 397 compatible = "fsl,qoriq-mc-dpmac"; 398 reg = <0x8>; 399 }; 400 401 dpmac9: dpmac@9 { 402 compatible = "fsl,qoriq-mc-dpmac"; 403 reg = <0x9>; 404 }; 405 406 dpmac10: dpmac@a { 407 compatible = "fsl,qoriq-mc-dpmac"; 408 reg = <0xa>; 409 }; 410 411 dpmac11: dpmac@b { 412 compatible = "fsl,qoriq-mc-dpmac"; 413 reg = <0xb>; 414 }; 415 416 dpmac12: dpmac@c { 417 compatible = "fsl,qoriq-mc-dpmac"; 418 reg = <0xc>; 419 }; 420 421 dpmac13: dpmac@d { 422 compatible = "fsl,qoriq-mc-dpmac"; 423 reg = <0xd>; 424 }; 425 426 dpmac14: dpmac@e { 427 compatible = "fsl,qoriq-mc-dpmac"; 428 reg = <0xe>; 429 }; 430 431 dpmac15: dpmac@f { 432 compatible = "fsl,qoriq-mc-dpmac"; 433 reg = <0xf>; 434 }; 435 436 dpmac16: dpmac@10 { 437 compatible = "fsl,qoriq-mc-dpmac"; 438 reg = <0x10>; 439 }; 440 }; 441 }; 442 443 smmu: iommu@5000000 { 444 compatible = "arm,mmu-500"; 445 reg = <0 0x5000000 0 0x800000>; 446 #global-interrupts = <12>; 447 #iommu-cells = <1>; 448 stream-match-mask = <0x7C00>; 449 dma-coherent; 450 interrupts = <0 13 4>, /* global secure fault */ 451 <0 14 4>, /* combined secure interrupt */ 452 <0 15 4>, /* global non-secure fault */ 453 <0 16 4>, /* combined non-secure interrupt */ 454 /* performance counter interrupts 0-7 */ 455 <0 211 4>, <0 212 4>, 456 <0 213 4>, <0 214 4>, 457 <0 215 4>, <0 216 4>, 458 <0 217 4>, <0 218 4>, 459 /* per context interrupt, 64 interrupts */ 460 <0 146 4>, <0 147 4>, 461 <0 148 4>, <0 149 4>, 462 <0 150 4>, <0 151 4>, 463 <0 152 4>, <0 153 4>, 464 <0 154 4>, <0 155 4>, 465 <0 156 4>, <0 157 4>, 466 <0 158 4>, <0 159 4>, 467 <0 160 4>, <0 161 4>, 468 <0 162 4>, <0 163 4>, 469 <0 164 4>, <0 165 4>, 470 <0 166 4>, <0 167 4>, 471 <0 168 4>, <0 169 4>, 472 <0 170 4>, <0 171 4>, 473 <0 172 4>, <0 173 4>, 474 <0 174 4>, <0 175 4>, 475 <0 176 4>, <0 177 4>, 476 <0 178 4>, <0 179 4>, 477 <0 180 4>, <0 181 4>, 478 <0 182 4>, <0 183 4>, 479 <0 184 4>, <0 185 4>, 480 <0 186 4>, <0 187 4>, 481 <0 188 4>, <0 189 4>, 482 <0 190 4>, <0 191 4>, 483 <0 192 4>, <0 193 4>, 484 <0 194 4>, <0 195 4>, 485 <0 196 4>, <0 197 4>, 486 <0 198 4>, <0 199 4>, 487 <0 200 4>, <0 201 4>, 488 <0 202 4>, <0 203 4>, 489 <0 204 4>, <0 205 4>, 490 <0 206 4>, <0 207 4>, 491 <0 208 4>, <0 209 4>; 492 }; 493 494 dspi: spi@2100000 { 495 status = "disabled"; 496 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 reg = <0x0 0x2100000 0x0 0x10000>; 500 interrupts = <0 26 0x4>; /* Level high type */ 501 clocks = <&clockgen 4 3>; 502 clock-names = "dspi"; 503 spi-num-chipselects = <5>; 504 }; 505 506 esdhc: esdhc@2140000 { 507 status = "disabled"; 508 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 509 reg = <0x0 0x2140000 0x0 0x10000>; 510 interrupts = <0 28 0x4>; /* Level high type */ 511 clocks = <&clockgen 4 1>; 512 voltage-ranges = <1800 1800 3300 3300>; 513 sdhci,auto-cmd12; 514 little-endian; 515 bus-width = <4>; 516 }; 517 518 gpio0: gpio@2300000 { 519 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 520 reg = <0x0 0x2300000 0x0 0x10000>; 521 interrupts = <0 36 0x4>; /* Level high type */ 522 gpio-controller; 523 little-endian; 524 #gpio-cells = <2>; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 }; 528 529 gpio1: gpio@2310000 { 530 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 531 reg = <0x0 0x2310000 0x0 0x10000>; 532 interrupts = <0 36 0x4>; /* Level high type */ 533 gpio-controller; 534 little-endian; 535 #gpio-cells = <2>; 536 interrupt-controller; 537 #interrupt-cells = <2>; 538 }; 539 540 gpio2: gpio@2320000 { 541 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 542 reg = <0x0 0x2320000 0x0 0x10000>; 543 interrupts = <0 37 0x4>; /* Level high type */ 544 gpio-controller; 545 little-endian; 546 #gpio-cells = <2>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 }; 550 551 gpio3: gpio@2330000 { 552 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 553 reg = <0x0 0x2330000 0x0 0x10000>; 554 interrupts = <0 37 0x4>; /* Level high type */ 555 gpio-controller; 556 little-endian; 557 #gpio-cells = <2>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 }; 561 562 i2c0: i2c@2000000 { 563 status = "disabled"; 564 compatible = "fsl,vf610-i2c"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 reg = <0x0 0x2000000 0x0 0x10000>; 568 interrupts = <0 34 0x4>; /* Level high type */ 569 clock-names = "i2c"; 570 clocks = <&clockgen 4 3>; 571 }; 572 573 i2c1: i2c@2010000 { 574 status = "disabled"; 575 compatible = "fsl,vf610-i2c"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 reg = <0x0 0x2010000 0x0 0x10000>; 579 interrupts = <0 34 0x4>; /* Level high type */ 580 clock-names = "i2c"; 581 clocks = <&clockgen 4 3>; 582 }; 583 584 i2c2: i2c@2020000 { 585 status = "disabled"; 586 compatible = "fsl,vf610-i2c"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 reg = <0x0 0x2020000 0x0 0x10000>; 590 interrupts = <0 35 0x4>; /* Level high type */ 591 clock-names = "i2c"; 592 clocks = <&clockgen 4 3>; 593 }; 594 595 i2c3: i2c@2030000 { 596 status = "disabled"; 597 compatible = "fsl,vf610-i2c"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 reg = <0x0 0x2030000 0x0 0x10000>; 601 interrupts = <0 35 0x4>; /* Level high type */ 602 clock-names = "i2c"; 603 clocks = <&clockgen 4 3>; 604 }; 605 606 ifc: ifc@2240000 { 607 compatible = "fsl,ifc", "simple-bus"; 608 reg = <0x0 0x2240000 0x0 0x20000>; 609 interrupts = <0 21 0x4>; /* Level high type */ 610 little-endian; 611 #address-cells = <2>; 612 #size-cells = <1>; 613 614 ranges = <0 0 0x5 0x80000000 0x08000000 615 2 0 0x5 0x30000000 0x00010000 616 3 0 0x5 0x20000000 0x00010000>; 617 }; 618 619 qspi: spi@20c0000 { 620 status = "disabled"; 621 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <0x0 0x20c0000 0x0 0x10000>, 625 <0x0 0x20000000 0x0 0x10000000>; 626 reg-names = "QuadSPI", "QuadSPI-memory"; 627 interrupts = <0 25 0x4>; /* Level high type */ 628 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 629 clock-names = "qspi_en", "qspi"; 630 }; 631 632 pcie1: pcie@3400000 { 633 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 634 reg-names = "regs", "config"; 635 interrupts = <0 108 0x4>; /* Level high type */ 636 interrupt-names = "intr"; 637 #address-cells = <3>; 638 #size-cells = <2>; 639 device_type = "pci"; 640 dma-coherent; 641 num-viewport = <6>; 642 bus-range = <0x0 0xff>; 643 msi-parent = <&its>; 644 #interrupt-cells = <1>; 645 interrupt-map-mask = <0 0 0 7>; 646 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 647 <0000 0 0 2 &gic 0 0 0 110 4>, 648 <0000 0 0 3 &gic 0 0 0 111 4>, 649 <0000 0 0 4 &gic 0 0 0 112 4>; 650 status = "disabled"; 651 }; 652 653 pcie2: pcie@3500000 { 654 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 655 reg-names = "regs", "config"; 656 interrupts = <0 113 0x4>; /* Level high type */ 657 interrupt-names = "intr"; 658 #address-cells = <3>; 659 #size-cells = <2>; 660 device_type = "pci"; 661 dma-coherent; 662 num-viewport = <6>; 663 bus-range = <0x0 0xff>; 664 msi-parent = <&its>; 665 #interrupt-cells = <1>; 666 interrupt-map-mask = <0 0 0 7>; 667 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 668 <0000 0 0 2 &gic 0 0 0 115 4>, 669 <0000 0 0 3 &gic 0 0 0 116 4>, 670 <0000 0 0 4 &gic 0 0 0 117 4>; 671 status = "disabled"; 672 }; 673 674 pcie3: pcie@3600000 { 675 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 676 reg-names = "regs", "config"; 677 interrupts = <0 118 0x4>; /* Level high type */ 678 interrupt-names = "intr"; 679 #address-cells = <3>; 680 #size-cells = <2>; 681 device_type = "pci"; 682 dma-coherent; 683 num-viewport = <256>; 684 bus-range = <0x0 0xff>; 685 msi-parent = <&its>; 686 #interrupt-cells = <1>; 687 interrupt-map-mask = <0 0 0 7>; 688 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 689 <0000 0 0 2 &gic 0 0 0 120 4>, 690 <0000 0 0 3 &gic 0 0 0 121 4>, 691 <0000 0 0 4 &gic 0 0 0 122 4>; 692 status = "disabled"; 693 }; 694 695 pcie4: pcie@3700000 { 696 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 697 reg-names = "regs", "config"; 698 interrupts = <0 123 0x4>; /* Level high type */ 699 interrupt-names = "intr"; 700 #address-cells = <3>; 701 #size-cells = <2>; 702 device_type = "pci"; 703 dma-coherent; 704 num-viewport = <6>; 705 bus-range = <0x0 0xff>; 706 msi-parent = <&its>; 707 #interrupt-cells = <1>; 708 interrupt-map-mask = <0 0 0 7>; 709 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 710 <0000 0 0 2 &gic 0 0 0 125 4>, 711 <0000 0 0 3 &gic 0 0 0 126 4>, 712 <0000 0 0 4 &gic 0 0 0 127 4>; 713 status = "disabled"; 714 }; 715 716 sata0: sata@3200000 { 717 status = "disabled"; 718 compatible = "fsl,ls2080a-ahci"; 719 reg = <0x0 0x3200000 0x0 0x10000>; 720 interrupts = <0 133 0x4>; /* Level high type */ 721 clocks = <&clockgen 4 3>; 722 dma-coherent; 723 }; 724 725 sata1: sata@3210000 { 726 status = "disabled"; 727 compatible = "fsl,ls2080a-ahci"; 728 reg = <0x0 0x3210000 0x0 0x10000>; 729 interrupts = <0 136 0x4>; /* Level high type */ 730 clocks = <&clockgen 4 3>; 731 dma-coherent; 732 }; 733 734 usb0: usb3@3100000 { 735 status = "disabled"; 736 compatible = "snps,dwc3"; 737 reg = <0x0 0x3100000 0x0 0x10000>; 738 interrupts = <0 80 0x4>; /* Level high type */ 739 dr_mode = "host"; 740 snps,quirk-frame-length-adjustment = <0x20>; 741 snps,dis_rxdet_inp3_quirk; 742 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 743 }; 744 745 usb1: usb3@3110000 { 746 status = "disabled"; 747 compatible = "snps,dwc3"; 748 reg = <0x0 0x3110000 0x0 0x10000>; 749 interrupts = <0 81 0x4>; /* Level high type */ 750 dr_mode = "host"; 751 snps,quirk-frame-length-adjustment = <0x20>; 752 snps,dis_rxdet_inp3_quirk; 753 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 754 }; 755 756 ccn@4000000 { 757 compatible = "arm,ccn-504"; 758 reg = <0x0 0x04000000 0x0 0x01000000>; 759 interrupts = <0 12 4>; 760 }; 761 }; 762 763 ddr1: memory-controller@1080000 { 764 compatible = "fsl,qoriq-memory-controller"; 765 reg = <0x0 0x1080000 0x0 0x1000>; 766 interrupts = <0 17 0x4>; 767 little-endian; 768 }; 769 770 ddr2: memory-controller@1090000 { 771 compatible = "fsl,qoriq-memory-controller"; 772 reg = <0x0 0x1090000 0x0 0x1000>; 773 interrupts = <0 18 0x4>; 774 little-endian; 775 }; 776 777 firmware { 778 optee { 779 compatible = "linaro,optee-tz"; 780 method = "smc"; 781 }; 782 }; 783}; 784