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1/{
2		dpe: dpe@E8600000 {
3			compatible = "hisilicon,hi3660-dpe";
4			status = "ok";
5
6			reg = <0x0 0xE8600000 0x0 0x80000>,
7					<0x0 0xFFF35000 0 0x1000>,
8					<0x0 0xFFF0A000 0 0x1000>,
9					<0x0 0xFFF31000 0 0x1000>,
10					<0x0 0xE86C0000 0 0x10000>;
11			interrupts = <0 245 4>;
12
13			clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>,
14				<&crg_ctrl HI3660_PCLK_GATE_DSS>,
15				<&crg_ctrl HI3660_CLK_GATE_EDC0>,
16				<&crg_ctrl HI3660_CLK_GATE_LDI0>,
17				<&crg_ctrl HI3660_CLK_GATE_LDI1>,
18				<&sctrl HI3660_CLK_GATE_DSS_AXI_MM>,
19				<&sctrl HI3660_PCLK_GATE_MMBUF>;
20			clock-names = "aclk_dss",
21					"pclk_dss",
22					"clk_edc0",
23					"clk_ldi0",
24					"clk_ldi1",
25					"clk_dss_axi_mm",
26					"pclk_mmbuf";
27
28			dma-coherent;
29
30			port {
31				dpe_out: endpoint {
32					remote-endpoint = <&dsi_in>;
33				};
34			};
35
36			iommu_info {
37				start-addr = <0x8000>;
38				size = <0xbfff8000>;
39			};
40		};
41
42		dsi: dsi@E8601000 {
43			compatible = "hisilicon,hi3660-dsi";
44			status = "ok";
45
46			reg = <0 0xE8601000 0 0x7F000>,
47					<0 0xFFF35000 0 0x1000>;
48
49			clocks = <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>,
50					<&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>,
51					<&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>,
52					<&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>,
53					<&crg_ctrl HI3660_PCLK_GATE_DSI0>,
54					<&crg_ctrl HI3660_PCLK_GATE_DSI1>;
55			clock-names = "clk_txdphy0_ref",
56						"clk_txdphy1_ref",
57						"clk_txdphy0_cfg",
58						"clk_txdphy1_cfg",
59						"pclk_dsi0",
60						"pclk_dsi1";
61
62			#address-cells = <1>;
63			#size-cells = <0>;
64			mux-gpio = <&gpio2 4 0>;
65
66			ports {
67				#address-cells = <1>;
68				#size-cells = <0>;
69
70				port@0 {
71					reg = <0>;
72					dsi_in: endpoint {
73						remote-endpoint = <&dpe_out>;
74					};
75				};
76
77				port@1 {
78					#address-cells = <1>;
79					#size-cells = <0>;
80					reg = <1>;
81
82					dsi_out0: endpoint@0 {
83						reg = <0>;
84						remote-endpoint = <&adv7533_in>;
85					};
86
87					dsi_out1: endpoint@1 {
88						reg = <1>;
89						remote-endpoint = <&panel0_in>;
90					};
91				};
92			};
93
94			panel@1 {
95				compatible = "hisilicon,mipi-hikey";
96				#address-cells = <2>;
97				#size-cells = <2>;
98				status = "ok";
99				reg = <1>;
100				panel-width-mm = <94>;
101				panel-height-mm = <151>;
102				vdd-supply = <&ldo3>;
103				pwr-en-gpio = <&gpio27 0 0>;
104				bl-en-gpio = <&gpio27 2 0>;
105				pwm-gpio = <&gpio22 6 0>;
106
107				port {
108					panel0_in: endpoint {
109						remote-endpoint = <&dsi_out1>;
110					};
111				};
112			};
113		};
114};
115