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1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/gpio/gpio.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "MediaTek MT7622 RFB1 board";
18	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
27	};
28
29	cpus {
30		cpu@0 {
31			proc-supply = <&mt6380_vcpu_reg>;
32			sram-supply = <&mt6380_vm_reg>;
33		};
34
35		cpu@1 {
36			proc-supply = <&mt6380_vcpu_reg>;
37			sram-supply = <&mt6380_vm_reg>;
38		};
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43		poll-interval = <100>;
44
45		factory {
46			label = "factory";
47			linux,code = <BTN_0>;
48			gpios = <&pio 0 0>;
49		};
50
51		wps {
52			label = "wps";
53			linux,code = <KEY_WPS_BUTTON>;
54			gpios = <&pio 102 0>;
55		};
56	};
57
58	memory@40000000 {
59		reg = <0 0x40000000 0 0x20000000>;
60		device_type = "memory";
61	};
62
63	reg_1p8v: regulator-1p8v {
64		compatible = "regulator-fixed";
65		regulator-name = "fixed-1.8V";
66		regulator-min-microvolt = <1800000>;
67		regulator-max-microvolt = <1800000>;
68		regulator-always-on;
69	};
70
71	reg_3p3v: regulator-3p3v {
72		compatible = "regulator-fixed";
73		regulator-name = "fixed-3.3V";
74		regulator-min-microvolt = <3300000>;
75		regulator-max-microvolt = <3300000>;
76		regulator-boot-on;
77		regulator-always-on;
78	};
79
80	reg_5v: regulator-5v {
81		compatible = "regulator-fixed";
82		regulator-name = "fixed-5V";
83		regulator-min-microvolt = <5000000>;
84		regulator-max-microvolt = <5000000>;
85		regulator-boot-on;
86		regulator-always-on;
87	};
88};
89
90&bch {
91	status = "disabled";
92};
93
94&btif {
95	status = "okay";
96};
97
98&cir {
99	pinctrl-names = "default";
100	pinctrl-0 = <&irrx_pins>;
101	status = "okay";
102};
103
104&eth {
105	pinctrl-names = "default";
106	pinctrl-0 = <&eth_pins>;
107	status = "okay";
108
109	gmac1: mac@1 {
110		compatible = "mediatek,eth-mac";
111		reg = <1>;
112		phy-handle = <&phy5>;
113	};
114
115	mdio-bus {
116		#address-cells = <1>;
117		#size-cells = <0>;
118
119		phy5: ethernet-phy@5 {
120			reg = <5>;
121			phy-mode = "sgmii";
122		};
123	};
124};
125
126&i2c1 {
127	pinctrl-names = "default";
128	pinctrl-0 = <&i2c1_pins>;
129	status = "okay";
130};
131
132&i2c2 {
133	pinctrl-names = "default";
134	pinctrl-0 = <&i2c2_pins>;
135	status = "okay";
136};
137
138&mmc0 {
139	pinctrl-names = "default", "state_uhs";
140	pinctrl-0 = <&emmc_pins_default>;
141	pinctrl-1 = <&emmc_pins_uhs>;
142	status = "okay";
143	bus-width = <8>;
144	max-frequency = <50000000>;
145	cap-mmc-highspeed;
146	mmc-hs200-1_8v;
147	vmmc-supply = <&reg_3p3v>;
148	vqmmc-supply = <&reg_1p8v>;
149	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
150	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
151	non-removable;
152};
153
154&mmc1 {
155	pinctrl-names = "default", "state_uhs";
156	pinctrl-0 = <&sd0_pins_default>;
157	pinctrl-1 = <&sd0_pins_uhs>;
158	status = "okay";
159	bus-width = <4>;
160	max-frequency = <50000000>;
161	cap-sd-highspeed;
162	r_smpl = <1>;
163	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
164	vmmc-supply = <&reg_3p3v>;
165	vqmmc-supply = <&reg_3p3v>;
166	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
167	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
168};
169
170&nandc {
171	pinctrl-names = "default";
172	pinctrl-0 = <&parallel_nand_pins>;
173	status = "disabled";
174};
175
176&nor_flash {
177	pinctrl-names = "default";
178	pinctrl-0 = <&spi_nor_pins>;
179	status = "disabled";
180
181	flash@0 {
182		compatible = "jedec,spi-nor";
183		reg = <0>;
184	};
185};
186
187&pcie {
188	pinctrl-names = "default";
189	pinctrl-0 = <&pcie0_pins>;
190	status = "okay";
191
192	pcie@0,0 {
193		status = "okay";
194	};
195};
196
197&pio {
198	/* eMMC is shared pin with parallel NAND */
199	emmc_pins_default: emmc-pins-default {
200		mux {
201			function = "emmc", "emmc_rst";
202			groups = "emmc";
203		};
204
205		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
206		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
207		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
208		 */
209		conf-cmd-dat {
210			pins = "NDL0", "NDL1", "NDL2",
211			       "NDL3", "NDL4", "NDL5",
212			       "NDL6", "NDL7", "NRB";
213			input-enable;
214			bias-pull-up;
215		};
216
217		conf-clk {
218			pins = "NCLE";
219			bias-pull-down;
220		};
221	};
222
223	emmc_pins_uhs: emmc-pins-uhs {
224		mux {
225			function = "emmc";
226			groups = "emmc";
227		};
228
229		conf-cmd-dat {
230			pins = "NDL0", "NDL1", "NDL2",
231			       "NDL3", "NDL4", "NDL5",
232			       "NDL6", "NDL7", "NRB";
233			input-enable;
234			drive-strength = <4>;
235			bias-pull-up;
236		};
237
238		conf-clk {
239			pins = "NCLE";
240			drive-strength = <4>;
241			bias-pull-down;
242		};
243	};
244
245	eth_pins: eth-pins {
246		mux {
247			function = "eth";
248			groups = "mdc_mdio", "rgmii_via_gmac2";
249		};
250	};
251
252	i2c1_pins: i2c1-pins {
253		mux {
254			function = "i2c";
255			groups =  "i2c1_0";
256		};
257	};
258
259	i2c2_pins: i2c2-pins {
260		mux {
261			function = "i2c";
262			groups =  "i2c2_0";
263		};
264	};
265
266	i2s1_pins: i2s1-pins {
267		mux {
268			function = "i2s";
269			groups =  "i2s_out_mclk_bclk_ws",
270				  "i2s1_in_data",
271				  "i2s1_out_data";
272		};
273
274		conf {
275			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
276			       "I2S_WS", "I2S_MCLK";
277			drive-strength = <12>;
278			bias-pull-down;
279		};
280	};
281
282	irrx_pins: irrx-pins {
283		mux {
284			function = "ir";
285			groups =  "ir_1_rx";
286		};
287	};
288
289	irtx_pins: irtx-pins {
290		mux {
291			function = "ir";
292			groups =  "ir_1_tx";
293		};
294	};
295
296	/* Parallel nand is shared pin with eMMC */
297	parallel_nand_pins: parallel-nand-pins {
298		mux {
299			function = "flash";
300			groups = "par_nand";
301		};
302	};
303
304	pcie0_pins: pcie0-pins {
305		mux {
306			function = "pcie";
307			groups = "pcie0_pad_perst",
308				 "pcie0_1_waken",
309				 "pcie0_1_clkreq";
310		};
311	};
312
313	pcie1_pins: pcie1-pins {
314		mux {
315			function = "pcie";
316			groups = "pcie1_pad_perst",
317				 "pcie1_0_waken",
318				 "pcie1_0_clkreq";
319		};
320	};
321
322	pmic_bus_pins: pmic-bus-pins {
323		mux {
324			function = "pmic";
325			groups = "pmic_bus";
326		};
327	};
328
329	pwm7_pins: pwm1-2-pins {
330		mux {
331			function = "pwm";
332			groups = "pwm_ch7_2";
333		};
334	};
335
336	wled_pins: wled-pins {
337		mux {
338			function = "led";
339			groups = "wled";
340		};
341	};
342
343	sd0_pins_default: sd0-pins-default {
344		mux {
345			function = "sd";
346			groups = "sd_0";
347		};
348
349		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
350		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
351		 *  DAT2, DAT3, CMD, CLK for SD respectively.
352		 */
353		conf-cmd-data {
354			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
355			       "I2S2_IN","I2S4_OUT";
356			input-enable;
357			drive-strength = <8>;
358			bias-pull-up;
359		};
360		conf-clk {
361			pins = "I2S3_OUT";
362			drive-strength = <12>;
363			bias-pull-down;
364		};
365		conf-cd {
366			pins = "TXD3";
367			bias-pull-up;
368		};
369	};
370
371	sd0_pins_uhs: sd0-pins-uhs {
372		mux {
373			function = "sd";
374			groups = "sd_0";
375		};
376
377		conf-cmd-data {
378			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
379			       "I2S2_IN","I2S4_OUT";
380			input-enable;
381			bias-pull-up;
382		};
383
384		conf-clk {
385			pins = "I2S3_OUT";
386			bias-pull-down;
387		};
388	};
389
390	/* Serial NAND is shared pin with SPI-NOR */
391	serial_nand_pins: serial-nand-pins {
392		mux {
393			function = "flash";
394			groups = "snfi";
395		};
396	};
397
398	spic0_pins: spic0-pins {
399		mux {
400			function = "spi";
401			groups = "spic0_0";
402		};
403	};
404
405	spic1_pins: spic1-pins {
406		mux {
407			function = "spi";
408			groups = "spic1_0";
409		};
410	};
411
412	/* SPI-NOR is shared pin with serial NAND */
413	spi_nor_pins: spi-nor-pins {
414		mux {
415			function = "flash";
416			groups = "spi_nor";
417		};
418	};
419
420	/* serial NAND is shared pin with SPI-NOR */
421	serial_nand_pins: serial-nand-pins {
422		mux {
423			function = "flash";
424			groups = "snfi";
425		};
426	};
427
428	uart0_pins: uart0-pins {
429		mux {
430			function = "uart";
431			groups = "uart0_0_tx_rx" ;
432		};
433	};
434
435	uart2_pins: uart2-pins {
436		mux {
437			function = "uart";
438			groups = "uart2_1_tx_rx" ;
439		};
440	};
441
442	watchdog_pins: watchdog-pins {
443		mux {
444			function = "watchdog";
445			groups = "watchdog";
446		};
447	};
448};
449
450&pwm {
451	pinctrl-names = "default";
452	pinctrl-0 = <&pwm7_pins>;
453	status = "okay";
454};
455
456&pwrap {
457	pinctrl-names = "default";
458	pinctrl-0 = <&pmic_bus_pins>;
459
460	status = "okay";
461};
462
463&sata {
464	status = "okay";
465};
466
467&sata_phy {
468	status = "okay";
469};
470
471&spi0 {
472	pinctrl-names = "default";
473	pinctrl-0 = <&spic0_pins>;
474	status = "okay";
475};
476
477&spi1 {
478	pinctrl-names = "default";
479	pinctrl-0 = <&spic1_pins>;
480	status = "okay";
481};
482
483&ssusb {
484	vusb33-supply = <&reg_3p3v>;
485	vbus-supply = <&reg_5v>;
486	status = "okay";
487};
488
489&u3phy {
490	status = "okay";
491};
492
493&uart0 {
494	pinctrl-names = "default";
495	pinctrl-0 = <&uart0_pins>;
496	status = "okay";
497};
498
499&uart2 {
500	pinctrl-names = "default";
501	pinctrl-0 = <&uart2_pins>;
502	status = "okay";
503};
504
505&watchdog {
506	pinctrl-names = "default";
507	pinctrl-0 = <&watchdog_pins>;
508	status = "okay";
509};
510