1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,apr.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 memory { 20 device_type = "memory"; 21 /* We expect the bootloader to fill in the reg */ 22 reg = <0 0 0 0>; 23 }; 24 25 reserved-memory { 26 #address-cells = <2>; 27 #size-cells = <2>; 28 ranges; 29 30 mba_region: mba@91500000 { 31 reg = <0x0 0x91500000 0x0 0x200000>; 32 no-map; 33 }; 34 35 slpi_region: slpi@90b00000 { 36 reg = <0x0 0x90b00000 0x0 0xa00000>; 37 no-map; 38 }; 39 40 venus_region: venus@90400000 { 41 reg = <0x0 0x90400000 0x0 0x700000>; 42 no-map; 43 }; 44 45 adsp_region: adsp@8ea00000 { 46 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 47 no-map; 48 }; 49 50 mpss_region: mpss@88800000 { 51 reg = <0x0 0x88800000 0x0 0x6200000>; 52 no-map; 53 }; 54 55 smem_mem: smem-mem@86000000 { 56 reg = <0x0 0x86000000 0x0 0x200000>; 57 no-map; 58 }; 59 60 memory@85800000 { 61 reg = <0x0 0x85800000 0x0 0x800000>; 62 no-map; 63 }; 64 65 memory@86200000 { 66 reg = <0x0 0x86200000 0x0 0x2600000>; 67 no-map; 68 }; 69 70 rmtfs@86700000 { 71 compatible = "qcom,rmtfs-mem"; 72 73 size = <0x0 0x200000>; 74 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 75 no-map; 76 77 qcom,client-id = <1>; 78 qcom,vmid = <15>; 79 }; 80 81 zap_shader_region: gpu@8f200000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x0 0x90b00000 0x0 0xa00000>; 84 no-map; 85 }; 86 }; 87 88 cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo"; 95 reg = <0x0 0x0>; 96 enable-method = "psci"; 97 cpu-idle-states = <&CPU_SLEEP_0>; 98 capacity-dmips-mhz = <1024>; 99 next-level-cache = <&L2_0>; 100 L2_0: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 }; 104 }; 105 106 CPU1: cpu@1 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo"; 109 reg = <0x0 0x1>; 110 enable-method = "psci"; 111 cpu-idle-states = <&CPU_SLEEP_0>; 112 capacity-dmips-mhz = <1024>; 113 next-level-cache = <&L2_0>; 114 }; 115 116 CPU2: cpu@100 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo"; 119 reg = <0x0 0x100>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0>; 122 capacity-dmips-mhz = <1024>; 123 next-level-cache = <&L2_1>; 124 L2_1: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 }; 128 }; 129 130 CPU3: cpu@101 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo"; 133 reg = <0x0 0x101>; 134 enable-method = "psci"; 135 cpu-idle-states = <&CPU_SLEEP_0>; 136 capacity-dmips-mhz = <1024>; 137 next-level-cache = <&L2_1>; 138 }; 139 140 cpu-map { 141 cluster0 { 142 core0 { 143 cpu = <&CPU0>; 144 }; 145 146 core1 { 147 cpu = <&CPU1>; 148 }; 149 }; 150 151 cluster1 { 152 core0 { 153 cpu = <&CPU2>; 154 }; 155 156 core1 { 157 cpu = <&CPU3>; 158 }; 159 }; 160 }; 161 162 idle-states { 163 entry-method = "psci"; 164 165 CPU_SLEEP_0: cpu-sleep-0 { 166 compatible = "arm,idle-state"; 167 idle-state-name = "standalone-power-collapse"; 168 arm,psci-suspend-param = <0x00000004>; 169 entry-latency-us = <130>; 170 exit-latency-us = <80>; 171 min-residency-us = <300>; 172 }; 173 }; 174 }; 175 176 thermal-zones { 177 cpu0-thermal { 178 polling-delay-passive = <250>; 179 polling-delay = <1000>; 180 181 thermal-sensors = <&tsens0 3>; 182 183 trips { 184 cpu0_alert0: trip-point@0 { 185 temperature = <75000>; 186 hysteresis = <2000>; 187 type = "passive"; 188 }; 189 190 cpu0_crit: cpu_crit { 191 temperature = <110000>; 192 hysteresis = <2000>; 193 type = "critical"; 194 }; 195 }; 196 }; 197 198 cpu1-thermal { 199 polling-delay-passive = <250>; 200 polling-delay = <1000>; 201 202 thermal-sensors = <&tsens0 5>; 203 204 trips { 205 cpu1_alert0: trip-point@0 { 206 temperature = <75000>; 207 hysteresis = <2000>; 208 type = "passive"; 209 }; 210 211 cpu1_crit: cpu_crit { 212 temperature = <110000>; 213 hysteresis = <2000>; 214 type = "critical"; 215 }; 216 }; 217 }; 218 219 cpu2-thermal { 220 polling-delay-passive = <250>; 221 polling-delay = <1000>; 222 223 thermal-sensors = <&tsens0 8>; 224 225 trips { 226 cpu2_alert0: trip-point@0 { 227 temperature = <75000>; 228 hysteresis = <2000>; 229 type = "passive"; 230 }; 231 232 cpu2_crit: cpu_crit { 233 temperature = <110000>; 234 hysteresis = <2000>; 235 type = "critical"; 236 }; 237 }; 238 }; 239 240 cpu3-thermal { 241 polling-delay-passive = <250>; 242 polling-delay = <1000>; 243 244 thermal-sensors = <&tsens0 10>; 245 246 trips { 247 cpu3_alert0: trip-point@0 { 248 temperature = <75000>; 249 hysteresis = <2000>; 250 type = "passive"; 251 }; 252 253 cpu3_crit: cpu_crit { 254 temperature = <110000>; 255 hysteresis = <2000>; 256 type = "critical"; 257 }; 258 }; 259 }; 260 261 gpu-thermal-top { 262 polling-delay-passive = <250>; 263 polling-delay = <1000>; 264 265 thermal-sensors = <&tsens1 6>; 266 267 trips { 268 gpu1_alert0: trip-point@0 { 269 temperature = <90000>; 270 hysteresis = <2000>; 271 type = "hot"; 272 }; 273 }; 274 }; 275 276 gpu-thermal-bottom { 277 polling-delay-passive = <250>; 278 polling-delay = <1000>; 279 280 thermal-sensors = <&tsens1 7>; 281 282 trips { 283 gpu2_alert0: trip-point@0 { 284 temperature = <90000>; 285 hysteresis = <2000>; 286 type = "hot"; 287 }; 288 }; 289 }; 290 291 m4m-thermal { 292 polling-delay-passive = <250>; 293 polling-delay = <1000>; 294 295 thermal-sensors = <&tsens0 1>; 296 297 trips { 298 m4m_alert0: trip-point@0 { 299 temperature = <90000>; 300 hysteresis = <2000>; 301 type = "hot"; 302 }; 303 }; 304 }; 305 306 l3-or-venus-thermal { 307 polling-delay-passive = <250>; 308 polling-delay = <1000>; 309 310 thermal-sensors = <&tsens0 2>; 311 312 trips { 313 l3_or_venus_alert0: trip-point@0 { 314 temperature = <90000>; 315 hysteresis = <2000>; 316 type = "hot"; 317 }; 318 }; 319 }; 320 321 cluster0-l2-thermal { 322 polling-delay-passive = <250>; 323 polling-delay = <1000>; 324 325 thermal-sensors = <&tsens0 7>; 326 327 trips { 328 cluster0_l2_alert0: trip-point@0 { 329 temperature = <90000>; 330 hysteresis = <2000>; 331 type = "hot"; 332 }; 333 }; 334 }; 335 336 cluster1-l2-thermal { 337 polling-delay-passive = <250>; 338 polling-delay = <1000>; 339 340 thermal-sensors = <&tsens0 12>; 341 342 trips { 343 cluster1_l2_alert0: trip-point@0 { 344 temperature = <90000>; 345 hysteresis = <2000>; 346 type = "hot"; 347 }; 348 }; 349 }; 350 351 camera-thermal { 352 polling-delay-passive = <250>; 353 polling-delay = <1000>; 354 355 thermal-sensors = <&tsens1 1>; 356 357 trips { 358 camera_alert0: trip-point@0 { 359 temperature = <90000>; 360 hysteresis = <2000>; 361 type = "hot"; 362 }; 363 }; 364 }; 365 366 q6-dsp-thermal { 367 polling-delay-passive = <250>; 368 polling-delay = <1000>; 369 370 thermal-sensors = <&tsens1 2>; 371 372 trips { 373 q6_dsp_alert0: trip-point@0 { 374 temperature = <90000>; 375 hysteresis = <2000>; 376 type = "hot"; 377 }; 378 }; 379 }; 380 381 mem-thermal { 382 polling-delay-passive = <250>; 383 polling-delay = <1000>; 384 385 thermal-sensors = <&tsens1 3>; 386 387 trips { 388 mem_alert0: trip-point@0 { 389 temperature = <90000>; 390 hysteresis = <2000>; 391 type = "hot"; 392 }; 393 }; 394 }; 395 396 modemtx-thermal { 397 polling-delay-passive = <250>; 398 polling-delay = <1000>; 399 400 thermal-sensors = <&tsens1 4>; 401 402 trips { 403 modemtx_alert0: trip-point@0 { 404 temperature = <90000>; 405 hysteresis = <2000>; 406 type = "hot"; 407 }; 408 }; 409 }; 410 }; 411 412 timer { 413 compatible = "arm,armv8-timer"; 414 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 415 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 416 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 417 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 418 }; 419 420 clocks { 421 xo_board: xo_board { 422 compatible = "fixed-clock"; 423 #clock-cells = <0>; 424 clock-frequency = <19200000>; 425 clock-output-names = "xo_board"; 426 }; 427 428 sleep_clk: sleep_clk { 429 compatible = "fixed-clock"; 430 #clock-cells = <0>; 431 clock-frequency = <32764>; 432 clock-output-names = "sleep_clk"; 433 }; 434 }; 435 436 etm { 437 compatible = "qcom,coresight-remote-etm"; 438 439 out-ports { 440 port { 441 modem_etm_out_funnel_in2: endpoint { 442 remote-endpoint = 443 <&funnel_in2_in_modem_etm>; 444 }; 445 }; 446 }; 447 }; 448 449 psci { 450 compatible = "arm,psci-1.0"; 451 method = "smc"; 452 }; 453 454 firmware { 455 scm { 456 compatible = "qcom,scm-msm8996"; 457 458 qcom,dload-mode = <&tcsr 0x13000>; 459 }; 460 }; 461 462 tcsr_mutex: hwlock { 463 compatible = "qcom,tcsr-mutex"; 464 syscon = <&tcsr_mutex_regs 0 0x1000>; 465 #hwlock-cells = <1>; 466 }; 467 468 smem { 469 compatible = "qcom,smem"; 470 memory-region = <&smem_mem>; 471 hwlocks = <&tcsr_mutex 3>; 472 }; 473 474 rpm-glink { 475 compatible = "qcom,glink-rpm"; 476 477 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 478 479 qcom,rpm-msg-ram = <&rpm_msg_ram>; 480 481 mboxes = <&apcs_glb 0>; 482 483 rpm_requests { 484 compatible = "qcom,rpm-msm8996"; 485 qcom,glink-channels = "rpm_requests"; 486 487 rpmcc: qcom,rpmcc { 488 compatible = "qcom,rpmcc-msm8996"; 489 #clock-cells = <1>; 490 }; 491 492 rpmpd: power-controller { 493 compatible = "qcom,msm8996-rpmpd"; 494 #power-domain-cells = <1>; 495 operating-points-v2 = <&rpmpd_opp_table>; 496 497 rpmpd_opp_table: opp-table { 498 compatible = "operating-points-v2"; 499 500 rpmpd_opp1: opp1 { 501 opp-level = <1>; 502 }; 503 504 rpmpd_opp2: opp2 { 505 opp-level = <2>; 506 }; 507 508 rpmpd_opp3: opp3 { 509 opp-level = <3>; 510 }; 511 512 rpmpd_opp4: opp4 { 513 opp-level = <4>; 514 }; 515 516 rpmpd_opp5: opp5 { 517 opp-level = <5>; 518 }; 519 520 rpmpd_opp6: opp6 { 521 opp-level = <6>; 522 }; 523 }; 524 }; 525 526 pm8994-regulators { 527 compatible = "qcom,rpm-pm8994-regulators"; 528 529 pm8994_s1: s1 {}; 530 pm8994_s2: s2 {}; 531 pm8994_s3: s3 {}; 532 pm8994_s4: s4 {}; 533 pm8994_s5: s5 {}; 534 pm8994_s6: s6 {}; 535 pm8994_s7: s7 {}; 536 pm8994_s8: s8 {}; 537 pm8994_s9: s9 {}; 538 pm8994_s10: s10 {}; 539 pm8994_s11: s11 {}; 540 pm8994_s12: s12 {}; 541 542 pm8994_l1: l1 {}; 543 pm8994_l2: l2 {}; 544 pm8994_l3: l3 {}; 545 pm8994_l4: l4 {}; 546 pm8994_l5: l5 {}; 547 pm8994_l6: l6 {}; 548 pm8994_l7: l7 {}; 549 pm8994_l8: l8 {}; 550 pm8994_l9: l9 {}; 551 pm8994_l10: l10 {}; 552 pm8994_l11: l11 {}; 553 pm8994_l12: l12 {}; 554 pm8994_l13: l13 {}; 555 pm8994_l14: l14 {}; 556 pm8994_l15: l15 {}; 557 pm8994_l16: l16 {}; 558 pm8994_l17: l17 {}; 559 pm8994_l18: l18 {}; 560 pm8994_l19: l19 {}; 561 pm8994_l20: l20 {}; 562 pm8994_l21: l21 {}; 563 pm8994_l22: l22 {}; 564 pm8994_l23: l23 {}; 565 pm8994_l24: l24 {}; 566 pm8994_l25: l25 {}; 567 pm8994_l26: l26 {}; 568 pm8994_l27: l27 {}; 569 pm8994_l28: l28 {}; 570 pm8994_l29: l29 {}; 571 pm8994_l30: l30 {}; 572 pm8994_l31: l31 {}; 573 pm8994_l32: l32 {}; 574 }; 575 576 }; 577 }; 578 579 soc: soc { 580 #address-cells = <1>; 581 #size-cells = <1>; 582 ranges = <0 0 0 0xffffffff>; 583 compatible = "simple-bus"; 584 585 rpm_msg_ram: memory@68000 { 586 compatible = "qcom,rpm-msg-ram"; 587 reg = <0x00068000 0x6000>; 588 }; 589 590 rng: rng@83000 { 591 compatible = "qcom,prng-ee"; 592 reg = <0x00083000 0x1000>; 593 clocks = <&gcc GCC_PRNG_AHB_CLK>; 594 clock-names = "core"; 595 }; 596 597 tcsr_mutex_regs: syscon@740000 { 598 compatible = "syscon"; 599 reg = <0x00740000 0x20000>; 600 }; 601 602 tsens0: thermal-sensor@4a9000 { 603 compatible = "qcom,msm8996-tsens"; 604 reg = <0x004a9000 0x1000>, /* TM */ 605 <0x004a8000 0x1000>; /* SROT */ 606 #qcom,sensors = <13>; 607 #thermal-sensor-cells = <1>; 608 }; 609 610 tsens1: thermal-sensor@4ad000 { 611 compatible = "qcom,msm8996-tsens"; 612 reg = <0x004ad000 0x1000>, /* TM */ 613 <0x004ac000 0x1000>; /* SROT */ 614 #qcom,sensors = <8>; 615 #thermal-sensor-cells = <1>; 616 }; 617 618 tcsr: syscon@7a0000 { 619 compatible = "qcom,tcsr-msm8996", "syscon"; 620 reg = <0x007a0000 0x18000>; 621 }; 622 623 intc: interrupt-controller@9bc0000 { 624 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 625 #interrupt-cells = <3>; 626 interrupt-controller; 627 #redistributor-regions = <1>; 628 redistributor-stride = <0x0 0x40000>; 629 reg = <0x09bc0000 0x10000>, 630 <0x09c00000 0x100000>; 631 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 632 }; 633 634 apcs_glb: mailbox@9820000 { 635 compatible = "qcom,msm8996-apcs-hmss-global"; 636 reg = <0x09820000 0x1000>; 637 638 #mbox-cells = <1>; 639 }; 640 641 gcc: clock-controller@300000 { 642 compatible = "qcom,gcc-msm8996"; 643 #clock-cells = <1>; 644 #reset-cells = <1>; 645 #power-domain-cells = <1>; 646 reg = <0x00300000 0x90000>; 647 }; 648 649 stm@3002000 { 650 compatible = "arm,coresight-stm", "arm,primecell"; 651 reg = <0x3002000 0x1000>, 652 <0x8280000 0x180000>; 653 reg-names = "stm-base", "stm-stimulus-base"; 654 655 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 656 clock-names = "apb_pclk", "atclk"; 657 658 out-ports { 659 port { 660 stm_out: endpoint { 661 remote-endpoint = 662 <&funnel0_in>; 663 }; 664 }; 665 }; 666 }; 667 668 tpiu@3020000 { 669 compatible = "arm,coresight-tpiu", "arm,primecell"; 670 reg = <0x3020000 0x1000>; 671 672 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 673 clock-names = "apb_pclk", "atclk"; 674 675 in-ports { 676 port { 677 tpiu_in: endpoint { 678 remote-endpoint = 679 <&replicator_out1>; 680 }; 681 }; 682 }; 683 }; 684 685 funnel@3021000 { 686 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 687 reg = <0x3021000 0x1000>; 688 689 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 690 clock-names = "apb_pclk", "atclk"; 691 692 in-ports { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 port@7 { 697 reg = <7>; 698 funnel0_in: endpoint { 699 remote-endpoint = 700 <&stm_out>; 701 }; 702 }; 703 }; 704 705 out-ports { 706 port { 707 funnel0_out: endpoint { 708 remote-endpoint = 709 <&merge_funnel_in0>; 710 }; 711 }; 712 }; 713 }; 714 715 funnel@3022000 { 716 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 717 reg = <0x3022000 0x1000>; 718 719 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 720 clock-names = "apb_pclk", "atclk"; 721 722 in-ports { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 726 port@6 { 727 reg = <6>; 728 funnel1_in: endpoint { 729 remote-endpoint = 730 <&apss_merge_funnel_out>; 731 }; 732 }; 733 }; 734 735 out-ports { 736 port { 737 funnel1_out: endpoint { 738 remote-endpoint = 739 <&merge_funnel_in1>; 740 }; 741 }; 742 }; 743 }; 744 745 funnel@3023000 { 746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 747 reg = <0x3023000 0x1000>; 748 749 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 750 clock-names = "apb_pclk", "atclk"; 751 752 in-ports { 753 port { 754 funnel_in2_in_modem_etm: endpoint { 755 remote-endpoint = 756 <&modem_etm_out_funnel_in2>; 757 }; 758 }; 759 }; 760 761 out-ports { 762 port { 763 funnel2_out: endpoint { 764 remote-endpoint = 765 <&merge_funnel_in2>; 766 }; 767 }; 768 }; 769 }; 770 771 funnel@3025000 { 772 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 773 reg = <0x3025000 0x1000>; 774 775 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 776 clock-names = "apb_pclk", "atclk"; 777 778 in-ports { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 port@0 { 783 reg = <0>; 784 merge_funnel_in0: endpoint { 785 remote-endpoint = 786 <&funnel0_out>; 787 }; 788 }; 789 790 port@1 { 791 reg = <1>; 792 merge_funnel_in1: endpoint { 793 remote-endpoint = 794 <&funnel1_out>; 795 }; 796 }; 797 798 port@2 { 799 reg = <2>; 800 merge_funnel_in2: endpoint { 801 remote-endpoint = 802 <&funnel2_out>; 803 }; 804 }; 805 }; 806 807 out-ports { 808 port { 809 merge_funnel_out: endpoint { 810 remote-endpoint = 811 <&etf_in>; 812 }; 813 }; 814 }; 815 }; 816 817 replicator@3026000 { 818 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 819 reg = <0x3026000 0x1000>; 820 821 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 822 clock-names = "apb_pclk", "atclk"; 823 824 in-ports { 825 port { 826 replicator_in: endpoint { 827 remote-endpoint = 828 <&etf_out>; 829 }; 830 }; 831 }; 832 833 out-ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 port@0 { 838 reg = <0>; 839 replicator_out0: endpoint { 840 remote-endpoint = 841 <&etr_in>; 842 }; 843 }; 844 845 port@1 { 846 reg = <1>; 847 replicator_out1: endpoint { 848 remote-endpoint = 849 <&tpiu_in>; 850 }; 851 }; 852 }; 853 }; 854 855 etf@3027000 { 856 compatible = "arm,coresight-tmc", "arm,primecell"; 857 reg = <0x3027000 0x1000>; 858 859 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 860 clock-names = "apb_pclk", "atclk"; 861 862 in-ports { 863 port { 864 etf_in: endpoint { 865 remote-endpoint = 866 <&merge_funnel_out>; 867 }; 868 }; 869 }; 870 871 out-ports { 872 port { 873 etf_out: endpoint { 874 remote-endpoint = 875 <&replicator_in>; 876 }; 877 }; 878 }; 879 }; 880 881 etr@3028000 { 882 compatible = "arm,coresight-tmc", "arm,primecell"; 883 reg = <0x3028000 0x1000>; 884 885 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 886 clock-names = "apb_pclk", "atclk"; 887 arm,scatter-gather; 888 889 in-ports { 890 port { 891 etr_in: endpoint { 892 remote-endpoint = 893 <&replicator_out0>; 894 }; 895 }; 896 }; 897 }; 898 899 debug@3810000 { 900 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 901 reg = <0x3810000 0x1000>; 902 903 clocks = <&rpmcc RPM_QDSS_CLK>; 904 clock-names = "apb_pclk"; 905 906 cpu = <&CPU0>; 907 }; 908 909 etm@3840000 { 910 compatible = "arm,coresight-etm4x", "arm,primecell"; 911 reg = <0x3840000 0x1000>; 912 913 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 914 clock-names = "apb_pclk", "atclk"; 915 916 cpu = <&CPU0>; 917 918 out-ports { 919 port { 920 etm0_out: endpoint { 921 remote-endpoint = 922 <&apss_funnel0_in0>; 923 }; 924 }; 925 }; 926 }; 927 928 debug@3910000 { 929 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 930 reg = <0x3910000 0x1000>; 931 932 clocks = <&rpmcc RPM_QDSS_CLK>; 933 clock-names = "apb_pclk"; 934 935 cpu = <&CPU1>; 936 }; 937 938 etm@3940000 { 939 compatible = "arm,coresight-etm4x", "arm,primecell"; 940 reg = <0x3940000 0x1000>; 941 942 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 943 clock-names = "apb_pclk", "atclk"; 944 945 cpu = <&CPU1>; 946 947 out-ports { 948 port { 949 etm1_out: endpoint { 950 remote-endpoint = 951 <&apss_funnel0_in1>; 952 }; 953 }; 954 }; 955 }; 956 957 funnel@39b0000 { /* APSS Funnel 0 */ 958 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 959 reg = <0x39b0000 0x1000>; 960 961 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 962 clock-names = "apb_pclk", "atclk"; 963 964 in-ports { 965 #address-cells = <1>; 966 #size-cells = <0>; 967 968 port@0 { 969 reg = <0>; 970 apss_funnel0_in0: endpoint { 971 remote-endpoint = <&etm0_out>; 972 }; 973 }; 974 975 port@1 { 976 reg = <1>; 977 apss_funnel0_in1: endpoint { 978 remote-endpoint = <&etm1_out>; 979 }; 980 }; 981 }; 982 983 out-ports { 984 port { 985 apss_funnel0_out: endpoint { 986 remote-endpoint = 987 <&apss_merge_funnel_in0>; 988 }; 989 }; 990 }; 991 }; 992 993 debug@3a10000 { 994 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 995 reg = <0x3a10000 0x1000>; 996 997 clocks = <&rpmcc RPM_QDSS_CLK>; 998 clock-names = "apb_pclk"; 999 1000 cpu = <&CPU2>; 1001 }; 1002 1003 etm@3a40000 { 1004 compatible = "arm,coresight-etm4x", "arm,primecell"; 1005 reg = <0x3a40000 0x1000>; 1006 1007 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1008 clock-names = "apb_pclk", "atclk"; 1009 1010 cpu = <&CPU2>; 1011 1012 out-ports { 1013 port { 1014 etm2_out: endpoint { 1015 remote-endpoint = 1016 <&apss_funnel1_in0>; 1017 }; 1018 }; 1019 }; 1020 }; 1021 1022 debug@3b10000 { 1023 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1024 reg = <0x3b10000 0x1000>; 1025 1026 clocks = <&rpmcc RPM_QDSS_CLK>; 1027 clock-names = "apb_pclk"; 1028 1029 cpu = <&CPU3>; 1030 }; 1031 1032 etm@3b40000 { 1033 compatible = "arm,coresight-etm4x", "arm,primecell"; 1034 reg = <0x3b40000 0x1000>; 1035 1036 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1037 clock-names = "apb_pclk", "atclk"; 1038 1039 cpu = <&CPU3>; 1040 1041 out-ports { 1042 port { 1043 etm3_out: endpoint { 1044 remote-endpoint = 1045 <&apss_funnel1_in1>; 1046 }; 1047 }; 1048 }; 1049 }; 1050 1051 funnel@3bb0000 { /* APSS Funnel 1 */ 1052 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1053 reg = <0x3bb0000 0x1000>; 1054 1055 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1056 clock-names = "apb_pclk", "atclk"; 1057 1058 in-ports { 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 1062 port@0 { 1063 reg = <0>; 1064 apss_funnel1_in0: endpoint { 1065 remote-endpoint = <&etm2_out>; 1066 }; 1067 }; 1068 1069 port@1 { 1070 reg = <1>; 1071 apss_funnel1_in1: endpoint { 1072 remote-endpoint = <&etm3_out>; 1073 }; 1074 }; 1075 }; 1076 1077 out-ports { 1078 port { 1079 apss_funnel1_out: endpoint { 1080 remote-endpoint = 1081 <&apss_merge_funnel_in1>; 1082 }; 1083 }; 1084 }; 1085 }; 1086 1087 funnel@3bc0000 { 1088 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1089 reg = <0x3bc0000 0x1000>; 1090 1091 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1092 clock-names = "apb_pclk", "atclk"; 1093 1094 in-ports { 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 1098 port@0 { 1099 reg = <0>; 1100 apss_merge_funnel_in0: endpoint { 1101 remote-endpoint = 1102 <&apss_funnel0_out>; 1103 }; 1104 }; 1105 1106 port@1 { 1107 reg = <1>; 1108 apss_merge_funnel_in1: endpoint { 1109 remote-endpoint = 1110 <&apss_funnel1_out>; 1111 }; 1112 }; 1113 }; 1114 1115 out-ports { 1116 port { 1117 apss_merge_funnel_out: endpoint { 1118 remote-endpoint = 1119 <&funnel1_in>; 1120 }; 1121 }; 1122 }; 1123 }; 1124 1125 kryocc: clock-controller@6400000 { 1126 compatible = "qcom,apcc-msm8996"; 1127 reg = <0x06400000 0x90000>; 1128 #clock-cells = <1>; 1129 }; 1130 1131 blsp1_uart1: serial@7570000 { 1132 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1133 reg = <0x07570000 0x1000>; 1134 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1136 <&gcc GCC_BLSP1_AHB_CLK>; 1137 clock-names = "core", "iface"; 1138 status = "disabled"; 1139 }; 1140 1141 blsp1_spi0: spi@7575000 { 1142 compatible = "qcom,spi-qup-v2.2.1"; 1143 reg = <0x07575000 0x600>; 1144 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1146 <&gcc GCC_BLSP1_AHB_CLK>; 1147 clock-names = "core", "iface"; 1148 pinctrl-names = "default", "sleep"; 1149 pinctrl-0 = <&blsp1_spi0_default>; 1150 pinctrl-1 = <&blsp1_spi0_sleep>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 blsp2_i2c0: i2c@75b5000 { 1157 compatible = "qcom,i2c-qup-v2.2.1"; 1158 reg = <0x075b5000 0x1000>; 1159 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1161 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 1162 clock-names = "iface", "core"; 1163 pinctrl-names = "default", "sleep"; 1164 pinctrl-0 = <&blsp2_i2c0_default>; 1165 pinctrl-1 = <&blsp2_i2c0_sleep>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 blsp2_uart1: serial@75b0000 { 1172 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1173 reg = <0x075b0000 0x1000>; 1174 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1176 <&gcc GCC_BLSP2_AHB_CLK>; 1177 clock-names = "core", "iface"; 1178 status = "disabled"; 1179 }; 1180 1181 blsp2_i2c1: i2c@75b6000 { 1182 compatible = "qcom,i2c-qup-v2.2.1"; 1183 reg = <0x075b6000 0x1000>; 1184 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1186 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 1187 clock-names = "iface", "core"; 1188 pinctrl-names = "default", "sleep"; 1189 pinctrl-0 = <&blsp2_i2c1_default>; 1190 pinctrl-1 = <&blsp2_i2c1_sleep>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 status = "disabled"; 1194 }; 1195 1196 blsp2_uart2: serial@75b1000 { 1197 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1198 reg = <0x075b1000 0x1000>; 1199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 1201 <&gcc GCC_BLSP2_AHB_CLK>; 1202 clock-names = "core", "iface"; 1203 status = "disabled"; 1204 }; 1205 1206 blsp1_i2c2: i2c@7577000 { 1207 compatible = "qcom,i2c-qup-v2.2.1"; 1208 reg = <0x07577000 0x1000>; 1209 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1210 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1211 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1212 clock-names = "iface", "core"; 1213 pinctrl-names = "default", "sleep"; 1214 pinctrl-0 = <&blsp1_i2c2_default>; 1215 pinctrl-1 = <&blsp1_i2c2_sleep>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 1221 blsp2_spi5: spi@75ba000{ 1222 compatible = "qcom,spi-qup-v2.2.1"; 1223 reg = <0x075ba000 0x600>; 1224 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 1226 <&gcc GCC_BLSP2_AHB_CLK>; 1227 clock-names = "core", "iface"; 1228 pinctrl-names = "default", "sleep"; 1229 pinctrl-0 = <&blsp2_spi5_default>; 1230 pinctrl-1 = <&blsp2_spi5_sleep>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 sdhc2: sdhci@74a4900 { 1237 status = "disabled"; 1238 compatible = "qcom,sdhci-msm-v4"; 1239 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 1240 reg-names = "hc_mem", "core_mem"; 1241 1242 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 1243 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1244 interrupt-names = "hc_irq", "pwr_irq"; 1245 1246 clock-names = "iface", "core", "xo"; 1247 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1248 <&gcc GCC_SDCC2_APPS_CLK>, 1249 <&xo_board>; 1250 bus-width = <4>; 1251 }; 1252 1253 msmgpio: pinctrl@1010000 { 1254 compatible = "qcom,msm8996-pinctrl"; 1255 reg = <0x01010000 0x300000>; 1256 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1257 gpio-controller; 1258 #gpio-cells = <2>; 1259 interrupt-controller; 1260 #interrupt-cells = <2>; 1261 }; 1262 1263 timer@9840000 { 1264 #address-cells = <1>; 1265 #size-cells = <1>; 1266 ranges; 1267 compatible = "arm,armv7-timer-mem"; 1268 reg = <0x09840000 0x1000>; 1269 clock-frequency = <19200000>; 1270 1271 frame@9850000 { 1272 frame-number = <0>; 1273 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1275 reg = <0x09850000 0x1000>, 1276 <0x09860000 0x1000>; 1277 }; 1278 1279 frame@9870000 { 1280 frame-number = <1>; 1281 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1282 reg = <0x09870000 0x1000>; 1283 status = "disabled"; 1284 }; 1285 1286 frame@9880000 { 1287 frame-number = <2>; 1288 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1289 reg = <0x09880000 0x1000>; 1290 status = "disabled"; 1291 }; 1292 1293 frame@9890000 { 1294 frame-number = <3>; 1295 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1296 reg = <0x09890000 0x1000>; 1297 status = "disabled"; 1298 }; 1299 1300 frame@98a0000 { 1301 frame-number = <4>; 1302 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1303 reg = <0x098a0000 0x1000>; 1304 status = "disabled"; 1305 }; 1306 1307 frame@98b0000 { 1308 frame-number = <5>; 1309 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1310 reg = <0x098b0000 0x1000>; 1311 status = "disabled"; 1312 }; 1313 1314 frame@98c0000 { 1315 frame-number = <6>; 1316 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1317 reg = <0x098c0000 0x1000>; 1318 status = "disabled"; 1319 }; 1320 }; 1321 1322 spmi_bus: qcom,spmi@400f000 { 1323 compatible = "qcom,spmi-pmic-arb"; 1324 reg = <0x0400f000 0x1000>, 1325 <0x04400000 0x800000>, 1326 <0x04c00000 0x800000>, 1327 <0x05800000 0x200000>, 1328 <0x0400a000 0x002100>; 1329 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1330 interrupt-names = "periph_irq"; 1331 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1332 qcom,ee = <0>; 1333 qcom,channel = <0>; 1334 #address-cells = <2>; 1335 #size-cells = <0>; 1336 interrupt-controller; 1337 #interrupt-cells = <4>; 1338 }; 1339 1340 ufsphy: phy@627000 { 1341 compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; 1342 reg = <0x00627000 0xda8>; 1343 reg-names = "phy_mem"; 1344 #phy-cells = <0>; 1345 1346 clock-names = "ref_clk_src", "ref_clk"; 1347 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 1348 <&gcc GCC_UFS_CLKREF_CLK>; 1349 resets = <&ufshc 0>; 1350 status = "disabled"; 1351 }; 1352 1353 ufshc: ufshc@624000 { 1354 compatible = "qcom,ufshc"; 1355 reg = <0x00624000 0x2500>; 1356 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1357 1358 phys = <&ufsphy>; 1359 phy-names = "ufsphy"; 1360 1361 power-domains = <&gcc UFS_GDSC>; 1362 1363 clock-names = 1364 "core_clk_src", 1365 "core_clk", 1366 "bus_clk", 1367 "bus_aggr_clk", 1368 "iface_clk", 1369 "core_clk_unipro_src", 1370 "core_clk_unipro", 1371 "core_clk_ice", 1372 "ref_clk", 1373 "tx_lane0_sync_clk", 1374 "rx_lane0_sync_clk"; 1375 clocks = 1376 <&gcc UFS_AXI_CLK_SRC>, 1377 <&gcc GCC_UFS_AXI_CLK>, 1378 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 1379 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 1380 <&gcc GCC_UFS_AHB_CLK>, 1381 <&gcc UFS_ICE_CORE_CLK_SRC>, 1382 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1383 <&gcc GCC_UFS_ICE_CORE_CLK>, 1384 <&rpmcc RPM_SMD_LN_BB_CLK>, 1385 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1386 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 1387 freq-table-hz = 1388 <100000000 200000000>, 1389 <0 0>, 1390 <0 0>, 1391 <0 0>, 1392 <0 0>, 1393 <150000000 300000000>, 1394 <0 0>, 1395 <0 0>, 1396 <0 0>, 1397 <0 0>, 1398 <0 0>; 1399 1400 lanes-per-direction = <1>; 1401 #reset-cells = <1>; 1402 status = "disabled"; 1403 1404 ufs_variant { 1405 compatible = "qcom,ufs_variant"; 1406 }; 1407 }; 1408 1409 mmcc: clock-controller@8c0000 { 1410 compatible = "qcom,mmcc-msm8996"; 1411 #clock-cells = <1>; 1412 #reset-cells = <1>; 1413 #power-domain-cells = <1>; 1414 reg = <0x008c0000 0x40000>; 1415 assigned-clocks = <&mmcc MMPLL9_PLL>, 1416 <&mmcc MMPLL1_PLL>, 1417 <&mmcc MMPLL3_PLL>, 1418 <&mmcc MMPLL4_PLL>, 1419 <&mmcc MMPLL5_PLL>; 1420 assigned-clock-rates = <624000000>, 1421 <810000000>, 1422 <980000000>, 1423 <960000000>, 1424 <825000000>; 1425 }; 1426 1427 qfprom@74000 { 1428 compatible = "qcom,qfprom"; 1429 reg = <0x00074000 0x8ff>; 1430 #address-cells = <1>; 1431 #size-cells = <1>; 1432 1433 qusb2p_hstx_trim: hstx_trim@24e { 1434 reg = <0x24e 0x2>; 1435 bits = <5 4>; 1436 }; 1437 1438 qusb2s_hstx_trim: hstx_trim@24f { 1439 reg = <0x24f 0x1>; 1440 bits = <1 4>; 1441 }; 1442 1443 gpu_speed_bin: gpu_speed_bin@133 { 1444 reg = <0x133 0x1>; 1445 bits = <5 3>; 1446 }; 1447 }; 1448 1449 pcie_phy: phy@34000 { 1450 compatible = "qcom,msm8996-qmp-pcie-phy"; 1451 reg = <0x00034000 0x488>; 1452 #clock-cells = <1>; 1453 #address-cells = <1>; 1454 #size-cells = <1>; 1455 ranges; 1456 1457 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1458 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 1459 <&gcc GCC_PCIE_CLKREF_CLK>; 1460 clock-names = "aux", "cfg_ahb", "ref"; 1461 1462 resets = <&gcc GCC_PCIE_PHY_BCR>, 1463 <&gcc GCC_PCIE_PHY_COM_BCR>, 1464 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 1465 reset-names = "phy", "common", "cfg"; 1466 status = "disabled"; 1467 1468 pciephy_0: lane@35000 { 1469 reg = <0x00035000 0x130>, 1470 <0x00035200 0x200>, 1471 <0x00035400 0x1dc>; 1472 #phy-cells = <0>; 1473 1474 clock-output-names = "pcie_0_pipe_clk_src"; 1475 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1476 clock-names = "pipe0"; 1477 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1478 reset-names = "lane0"; 1479 }; 1480 1481 pciephy_1: lane@36000 { 1482 reg = <0x00036000 0x130>, 1483 <0x00036200 0x200>, 1484 <0x00036400 0x1dc>; 1485 #phy-cells = <0>; 1486 1487 clock-output-names = "pcie_1_pipe_clk_src"; 1488 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1489 clock-names = "pipe1"; 1490 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1491 reset-names = "lane1"; 1492 }; 1493 1494 pciephy_2: lane@37000 { 1495 reg = <0x00037000 0x130>, 1496 <0x00037200 0x200>, 1497 <0x00037400 0x1dc>; 1498 #phy-cells = <0>; 1499 1500 clock-output-names = "pcie_2_pipe_clk_src"; 1501 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1502 clock-names = "pipe2"; 1503 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1504 reset-names = "lane2"; 1505 }; 1506 }; 1507 1508 usb3phy: phy@7410000 { 1509 compatible = "qcom,msm8996-qmp-usb3-phy"; 1510 reg = <0x07410000 0x1c4>; 1511 #clock-cells = <1>; 1512 #address-cells = <1>; 1513 #size-cells = <1>; 1514 ranges; 1515 1516 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1517 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1518 <&gcc GCC_USB3_CLKREF_CLK>; 1519 clock-names = "aux", "cfg_ahb", "ref"; 1520 1521 resets = <&gcc GCC_USB3_PHY_BCR>, 1522 <&gcc GCC_USB3PHY_PHY_BCR>; 1523 reset-names = "phy", "common"; 1524 status = "disabled"; 1525 1526 ssusb_phy_0: lane@7410200 { 1527 reg = <0x07410200 0x200>, 1528 <0x07410400 0x130>, 1529 <0x07410600 0x1a8>; 1530 #phy-cells = <0>; 1531 1532 clock-output-names = "usb3_phy_pipe_clk_src"; 1533 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1534 clock-names = "pipe0"; 1535 }; 1536 }; 1537 1538 hsusb_phy1: phy@7411000 { 1539 compatible = "qcom,msm8996-qusb2-phy"; 1540 reg = <0x07411000 0x180>; 1541 #phy-cells = <0>; 1542 1543 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1544 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1545 clock-names = "cfg_ahb", "ref"; 1546 1547 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1548 nvmem-cells = <&qusb2p_hstx_trim>; 1549 status = "disabled"; 1550 }; 1551 1552 hsusb_phy2: phy@7412000 { 1553 compatible = "qcom,msm8996-qusb2-phy"; 1554 reg = <0x07412000 0x180>; 1555 #phy-cells = <0>; 1556 1557 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1558 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 1559 clock-names = "cfg_ahb", "ref"; 1560 1561 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1562 nvmem-cells = <&qusb2s_hstx_trim>; 1563 status = "disabled"; 1564 }; 1565 1566 usb2: usb@76f8800 { 1567 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1568 reg = <0x076f8800 0x400>; 1569 #address-cells = <1>; 1570 #size-cells = <1>; 1571 ranges; 1572 1573 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 1574 <&gcc GCC_USB20_MASTER_CLK>, 1575 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1576 <&gcc GCC_USB20_SLEEP_CLK>, 1577 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1578 1579 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1580 <&gcc GCC_USB20_MASTER_CLK>; 1581 assigned-clock-rates = <19200000>, <60000000>; 1582 1583 power-domains = <&gcc USB30_GDSC>; 1584 status = "disabled"; 1585 1586 dwc3@7600000 { 1587 compatible = "snps,dwc3"; 1588 reg = <0x07600000 0xcc00>; 1589 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 1590 phys = <&hsusb_phy2>; 1591 phy-names = "usb2-phy"; 1592 snps,dis_u2_susphy_quirk; 1593 snps,dis_enblslpm_quirk; 1594 }; 1595 }; 1596 1597 usb3: usb@6af8800 { 1598 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1599 reg = <0x06af8800 0x400>; 1600 #address-cells = <1>; 1601 #size-cells = <1>; 1602 ranges; 1603 1604 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 1605 <&gcc GCC_USB30_MASTER_CLK>, 1606 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1607 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1608 <&gcc GCC_USB30_SLEEP_CLK>, 1609 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1610 1611 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1612 <&gcc GCC_USB30_MASTER_CLK>; 1613 assigned-clock-rates = <19200000>, <120000000>; 1614 1615 power-domains = <&gcc USB30_GDSC>; 1616 status = "disabled"; 1617 1618 dwc3@6a00000 { 1619 compatible = "snps,dwc3"; 1620 reg = <0x06a00000 0xcc00>; 1621 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 1622 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 1623 phy-names = "usb2-phy", "usb3-phy"; 1624 snps,dis_u2_susphy_quirk; 1625 snps,dis_enblslpm_quirk; 1626 }; 1627 }; 1628 1629 vfe_smmu: iommu@da0000 { 1630 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1631 reg = <0x00da0000 0x10000>; 1632 1633 #global-interrupts = <1>; 1634 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1637 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 1638 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 1639 <&mmcc SMMU_VFE_AXI_CLK>; 1640 clock-names = "iface", 1641 "bus"; 1642 #iommu-cells = <1>; 1643 }; 1644 1645 camss: camss@a00000 { 1646 compatible = "qcom,msm8996-camss"; 1647 reg = <0x00a34000 0x1000>, 1648 <0x00a00030 0x4>, 1649 <0x00a35000 0x1000>, 1650 <0x00a00038 0x4>, 1651 <0x00a36000 0x1000>, 1652 <0x00a00040 0x4>, 1653 <0x00a30000 0x100>, 1654 <0x00a30400 0x100>, 1655 <0x00a30800 0x100>, 1656 <0x00a30c00 0x100>, 1657 <0x00a31000 0x500>, 1658 <0x00a00020 0x10>, 1659 <0x00a10000 0x1000>, 1660 <0x00a14000 0x1000>; 1661 reg-names = "csiphy0", 1662 "csiphy0_clk_mux", 1663 "csiphy1", 1664 "csiphy1_clk_mux", 1665 "csiphy2", 1666 "csiphy2_clk_mux", 1667 "csid0", 1668 "csid1", 1669 "csid2", 1670 "csid3", 1671 "ispif", 1672 "csi_clk_mux", 1673 "vfe0", 1674 "vfe1"; 1675 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1676 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1677 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1678 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1679 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1680 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1681 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1682 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1683 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1684 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1685 interrupt-names = "csiphy0", 1686 "csiphy1", 1687 "csiphy2", 1688 "csid0", 1689 "csid1", 1690 "csid2", 1691 "csid3", 1692 "ispif", 1693 "vfe0", 1694 "vfe1"; 1695 power-domains = <&mmcc VFE0_GDSC>; 1696 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1697 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1698 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1699 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1700 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1701 <&mmcc CAMSS_CSI0_AHB_CLK>, 1702 <&mmcc CAMSS_CSI0_CLK>, 1703 <&mmcc CAMSS_CSI0PHY_CLK>, 1704 <&mmcc CAMSS_CSI0PIX_CLK>, 1705 <&mmcc CAMSS_CSI0RDI_CLK>, 1706 <&mmcc CAMSS_CSI1_AHB_CLK>, 1707 <&mmcc CAMSS_CSI1_CLK>, 1708 <&mmcc CAMSS_CSI1PHY_CLK>, 1709 <&mmcc CAMSS_CSI1PIX_CLK>, 1710 <&mmcc CAMSS_CSI1RDI_CLK>, 1711 <&mmcc CAMSS_CSI2_AHB_CLK>, 1712 <&mmcc CAMSS_CSI2_CLK>, 1713 <&mmcc CAMSS_CSI2PHY_CLK>, 1714 <&mmcc CAMSS_CSI2PIX_CLK>, 1715 <&mmcc CAMSS_CSI2RDI_CLK>, 1716 <&mmcc CAMSS_CSI3_AHB_CLK>, 1717 <&mmcc CAMSS_CSI3_CLK>, 1718 <&mmcc CAMSS_CSI3PHY_CLK>, 1719 <&mmcc CAMSS_CSI3PIX_CLK>, 1720 <&mmcc CAMSS_CSI3RDI_CLK>, 1721 <&mmcc CAMSS_AHB_CLK>, 1722 <&mmcc CAMSS_VFE0_CLK>, 1723 <&mmcc CAMSS_CSI_VFE0_CLK>, 1724 <&mmcc CAMSS_VFE0_AHB_CLK>, 1725 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1726 <&mmcc CAMSS_VFE1_CLK>, 1727 <&mmcc CAMSS_CSI_VFE1_CLK>, 1728 <&mmcc CAMSS_VFE1_AHB_CLK>, 1729 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1730 <&mmcc CAMSS_VFE_AHB_CLK>, 1731 <&mmcc CAMSS_VFE_AXI_CLK>; 1732 clock-names = "top_ahb", 1733 "ispif_ahb", 1734 "csiphy0_timer", 1735 "csiphy1_timer", 1736 "csiphy2_timer", 1737 "csi0_ahb", 1738 "csi0", 1739 "csi0_phy", 1740 "csi0_pix", 1741 "csi0_rdi", 1742 "csi1_ahb", 1743 "csi1", 1744 "csi1_phy", 1745 "csi1_pix", 1746 "csi1_rdi", 1747 "csi2_ahb", 1748 "csi2", 1749 "csi2_phy", 1750 "csi2_pix", 1751 "csi2_rdi", 1752 "csi3_ahb", 1753 "csi3", 1754 "csi3_phy", 1755 "csi3_pix", 1756 "csi3_rdi", 1757 "ahb", 1758 "vfe0", 1759 "csi_vfe0", 1760 "vfe0_ahb", 1761 "vfe0_stream", 1762 "vfe1", 1763 "csi_vfe1", 1764 "vfe1_ahb", 1765 "vfe1_stream", 1766 "vfe_ahb", 1767 "vfe_axi"; 1768 iommus = <&vfe_smmu 0>, 1769 <&vfe_smmu 1>, 1770 <&vfe_smmu 2>, 1771 <&vfe_smmu 3>; 1772 status = "disabled"; 1773 ports { 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 }; 1777 }; 1778 1779 adreno_smmu: iommu@b40000 { 1780 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1781 reg = <0x00b40000 0x10000>; 1782 1783 #global-interrupts = <1>; 1784 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1787 #iommu-cells = <1>; 1788 1789 clocks = <&mmcc GPU_AHB_CLK>, 1790 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1791 clock-names = "iface", "bus"; 1792 1793 power-domains = <&mmcc GPU_GDSC>; 1794 }; 1795 1796 mdp_smmu: iommu@d00000 { 1797 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1798 reg = <0x00d00000 0x10000>; 1799 1800 #global-interrupts = <1>; 1801 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1804 #iommu-cells = <1>; 1805 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 1806 <&mmcc SMMU_MDP_AXI_CLK>; 1807 clock-names = "iface", "bus"; 1808 1809 power-domains = <&mmcc MDSS_GDSC>; 1810 }; 1811 1812 lpass_q6_smmu: iommu@1600000 { 1813 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1814 reg = <0x01600000 0x20000>; 1815 #iommu-cells = <1>; 1816 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 1817 1818 #global-interrupts = <1>; 1819 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 1832 1833 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 1834 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1835 clock-names = "iface", "bus"; 1836 }; 1837 1838 agnoc@0 { 1839 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1840 compatible = "simple-pm-bus"; 1841 #address-cells = <1>; 1842 #size-cells = <1>; 1843 ranges; 1844 1845 pcie0: pcie@600000 { 1846 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1847 status = "disabled"; 1848 power-domains = <&gcc PCIE0_GDSC>; 1849 bus-range = <0x00 0xff>; 1850 num-lanes = <1>; 1851 1852 reg = <0x00600000 0x2000>, 1853 <0x0c000000 0xf1d>, 1854 <0x0c000f20 0xa8>, 1855 <0x0c100000 0x100000>; 1856 reg-names = "parf", "dbi", "elbi","config"; 1857 1858 phys = <&pciephy_0>; 1859 phy-names = "pciephy"; 1860 1861 #address-cells = <3>; 1862 #size-cells = <2>; 1863 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1864 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1865 1866 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1867 interrupt-names = "msi"; 1868 #interrupt-cells = <1>; 1869 interrupt-map-mask = <0 0 0 0x7>; 1870 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1871 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1872 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1873 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1874 1875 pinctrl-names = "default", "sleep"; 1876 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 1877 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 1878 1879 linux,pci-domain = <0>; 1880 1881 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1882 <&gcc GCC_PCIE_0_AUX_CLK>, 1883 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1884 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1885 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1886 1887 clock-names = "pipe", 1888 "aux", 1889 "cfg", 1890 "bus_master", 1891 "bus_slave"; 1892 1893 }; 1894 1895 pcie1: pcie@608000 { 1896 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1897 power-domains = <&gcc PCIE1_GDSC>; 1898 bus-range = <0x00 0xff>; 1899 num-lanes = <1>; 1900 1901 status = "disabled"; 1902 1903 reg = <0x00608000 0x2000>, 1904 <0x0d000000 0xf1d>, 1905 <0x0d000f20 0xa8>, 1906 <0x0d100000 0x100000>; 1907 1908 reg-names = "parf", "dbi", "elbi","config"; 1909 1910 phys = <&pciephy_1>; 1911 phy-names = "pciephy"; 1912 1913 #address-cells = <3>; 1914 #size-cells = <2>; 1915 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1916 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1917 1918 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1919 interrupt-names = "msi"; 1920 #interrupt-cells = <1>; 1921 interrupt-map-mask = <0 0 0 0x7>; 1922 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1923 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1924 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1925 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1926 1927 pinctrl-names = "default", "sleep"; 1928 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 1929 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 1930 1931 linux,pci-domain = <1>; 1932 1933 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1934 <&gcc GCC_PCIE_1_AUX_CLK>, 1935 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1936 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1937 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1938 1939 clock-names = "pipe", 1940 "aux", 1941 "cfg", 1942 "bus_master", 1943 "bus_slave"; 1944 }; 1945 1946 pcie2: pcie@610000 { 1947 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 1948 power-domains = <&gcc PCIE2_GDSC>; 1949 bus-range = <0x00 0xff>; 1950 num-lanes = <1>; 1951 status = "disabled"; 1952 reg = <0x00610000 0x2000>, 1953 <0x0e000000 0xf1d>, 1954 <0x0e000f20 0xa8>, 1955 <0x0e100000 0x100000>; 1956 1957 reg-names = "parf", "dbi", "elbi","config"; 1958 1959 phys = <&pciephy_2>; 1960 phy-names = "pciephy"; 1961 1962 #address-cells = <3>; 1963 #size-cells = <2>; 1964 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1966 1967 device_type = "pci"; 1968 1969 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupt-names = "msi"; 1971 #interrupt-cells = <1>; 1972 interrupt-map-mask = <0 0 0 0x7>; 1973 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1974 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1975 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1976 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1977 1978 pinctrl-names = "default", "sleep"; 1979 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 1980 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 1981 1982 linux,pci-domain = <2>; 1983 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1984 <&gcc GCC_PCIE_2_AUX_CLK>, 1985 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1986 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1987 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1988 1989 clock-names = "pipe", 1990 "aux", 1991 "cfg", 1992 "bus_master", 1993 "bus_slave"; 1994 }; 1995 }; 1996 1997 slimbam:dma@9184000 1998 { 1999 compatible = "qcom,bam-v1.7.0"; 2000 qcom,controlled-remotely; 2001 reg = <0x09184000 0x32000>; 2002 num-channels = <31>; 2003 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 2004 #dma-cells = <1>; 2005 qcom,ee = <1>; 2006 qcom,num-ees = <2>; 2007 }; 2008 2009 slim_msm: slim@91c0000 { 2010 compatible = "qcom,slim-ngd-v1.5.0"; 2011 reg = <0x091c0000 0x2C000>; 2012 reg-names = "ctrl"; 2013 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 2014 dmas = <&slimbam 3>, <&slimbam 4>, 2015 <&slimbam 5>, <&slimbam 6>; 2016 dma-names = "rx", "tx", "tx2", "rx2"; 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 ngd@1 { 2020 reg = <1>; 2021 #address-cells = <1>; 2022 #size-cells = <1>; 2023 2024 tasha_ifd: tas-ifd { 2025 compatible = "slim217,1a0"; 2026 reg = <0 0>; 2027 }; 2028 2029 wcd9335: codec@1{ 2030 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 2031 pinctrl-names = "default"; 2032 2033 compatible = "slim217,1a0"; 2034 reg = <1 0>; 2035 2036 interrupt-parent = <&msmgpio>; 2037 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 2038 <53 IRQ_TYPE_LEVEL_HIGH>; 2039 interrupt-names = "intr1", "intr2"; 2040 interrupt-controller; 2041 #interrupt-cells = <1>; 2042 reset-gpios = <&msmgpio 64 0>; 2043 2044 slim-ifc-dev = <&tasha_ifd>; 2045 2046 #sound-dai-cells = <1>; 2047 }; 2048 }; 2049 }; 2050 2051 gpu@b00000 { 2052 compatible = "qcom,adreno-530.2", "qcom,adreno"; 2053 #stream-id-cells = <16>; 2054 2055 reg = <0x00b00000 0x3f000>; 2056 reg-names = "kgsl_3d0_reg_memory"; 2057 2058 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 2059 2060 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 2061 <&mmcc GPU_AHB_CLK>, 2062 <&mmcc GPU_GX_RBBMTIMER_CLK>, 2063 <&gcc GCC_BIMC_GFX_CLK>, 2064 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 2065 2066 clock-names = "core", 2067 "iface", 2068 "rbbmtimer", 2069 "mem", 2070 "mem_iface"; 2071 2072 power-domains = <&mmcc GPU_GDSC>; 2073 iommus = <&adreno_smmu 0>; 2074 2075 nvmem-cells = <&gpu_speed_bin>; 2076 nvmem-cell-names = "speed_bin"; 2077 2078 operating-points-v2 = <&gpu_opp_table>; 2079 2080 gpu_opp_table: opp-table { 2081 compatible ="operating-points-v2"; 2082 2083 /* 2084 * 624Mhz and 560Mhz are only available on speed 2085 * bin (1 << 0). All the rest are available on 2086 * all bins of the hardware 2087 */ 2088 opp-624000000 { 2089 opp-hz = /bits/ 64 <624000000>; 2090 opp-supported-hw = <0x01>; 2091 }; 2092 opp-560000000 { 2093 opp-hz = /bits/ 64 <560000000>; 2094 opp-supported-hw = <0x01>; 2095 }; 2096 opp-510000000 { 2097 opp-hz = /bits/ 64 <510000000>; 2098 opp-supported-hw = <0xFF>; 2099 }; 2100 opp-401800000 { 2101 opp-hz = /bits/ 64 <401800000>; 2102 opp-supported-hw = <0xFF>; 2103 }; 2104 opp-315000000 { 2105 opp-hz = /bits/ 64 <315000000>; 2106 opp-supported-hw = <0xFF>; 2107 }; 2108 opp-214000000 { 2109 opp-hz = /bits/ 64 <214000000>; 2110 opp-supported-hw = <0xFF>; 2111 }; 2112 opp-133000000 { 2113 opp-hz = /bits/ 64 <133000000>; 2114 opp-supported-hw = <0xFF>; 2115 }; 2116 }; 2117 2118 zap-shader { 2119 memory-region = <&zap_shader_region>; 2120 }; 2121 }; 2122 2123 mdss: mdss@900000 { 2124 compatible = "qcom,mdss"; 2125 2126 reg = <0x00900000 0x1000>, 2127 <0x009b0000 0x1040>, 2128 <0x009b8000 0x1040>; 2129 reg-names = "mdss_phys", 2130 "vbif_phys", 2131 "vbif_nrt_phys"; 2132 2133 power-domains = <&mmcc MDSS_GDSC>; 2134 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2135 2136 interrupt-controller; 2137 #interrupt-cells = <1>; 2138 2139 clocks = <&mmcc MDSS_AHB_CLK>; 2140 clock-names = "iface"; 2141 2142 #address-cells = <1>; 2143 #size-cells = <1>; 2144 ranges; 2145 2146 mdp: mdp@901000 { 2147 compatible = "qcom,mdp5"; 2148 reg = <0x00901000 0x90000>; 2149 reg-names = "mdp_phys"; 2150 2151 interrupt-parent = <&mdss>; 2152 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2153 2154 clocks = <&mmcc MDSS_AHB_CLK>, 2155 <&mmcc MDSS_AXI_CLK>, 2156 <&mmcc MDSS_MDP_CLK>, 2157 <&mmcc SMMU_MDP_AXI_CLK>, 2158 <&mmcc MDSS_VSYNC_CLK>; 2159 clock-names = "iface", 2160 "bus", 2161 "core", 2162 "iommu", 2163 "vsync"; 2164 2165 iommus = <&mdp_smmu 0>; 2166 2167 ports { 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 2171 port@0 { 2172 reg = <0>; 2173 mdp5_intf3_out: endpoint { 2174 remote-endpoint = <&hdmi_in>; 2175 }; 2176 }; 2177 }; 2178 }; 2179 2180 hdmi: hdmi-tx@9a0000 { 2181 compatible = "qcom,hdmi-tx-8996"; 2182 reg = <0x009a0000 0x50c>, 2183 <0x00070000 0x6158>, 2184 <0x009e0000 0xfff>; 2185 reg-names = "core_physical", 2186 "qfprom_physical", 2187 "hdcp_physical"; 2188 2189 interrupt-parent = <&mdss>; 2190 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 2191 2192 clocks = <&mmcc MDSS_MDP_CLK>, 2193 <&mmcc MDSS_AHB_CLK>, 2194 <&mmcc MDSS_HDMI_CLK>, 2195 <&mmcc MDSS_HDMI_AHB_CLK>, 2196 <&mmcc MDSS_EXTPCLK_CLK>; 2197 clock-names = 2198 "mdp_core", 2199 "iface", 2200 "core", 2201 "alt_iface", 2202 "extp"; 2203 2204 phys = <&hdmi_phy>; 2205 phy-names = "hdmi_phy"; 2206 #sound-dai-cells = <1>; 2207 2208 ports { 2209 #address-cells = <1>; 2210 #size-cells = <0>; 2211 2212 port@0 { 2213 reg = <0>; 2214 hdmi_in: endpoint { 2215 remote-endpoint = <&mdp5_intf3_out>; 2216 }; 2217 }; 2218 }; 2219 }; 2220 2221 hdmi_phy: hdmi-phy@9a0600 { 2222 #phy-cells = <0>; 2223 compatible = "qcom,hdmi-phy-8996"; 2224 reg = <0x009a0600 0x1c4>, 2225 <0x009a0a00 0x124>, 2226 <0x009a0c00 0x124>, 2227 <0x009a0e00 0x124>, 2228 <0x009a1000 0x124>, 2229 <0x009a1200 0x0c8>; 2230 reg-names = "hdmi_pll", 2231 "hdmi_tx_l0", 2232 "hdmi_tx_l1", 2233 "hdmi_tx_l2", 2234 "hdmi_tx_l3", 2235 "hdmi_phy"; 2236 2237 clocks = <&mmcc MDSS_AHB_CLK>, 2238 <&gcc GCC_HDMI_CLKREF_CLK>; 2239 clock-names = "iface", 2240 "ref"; 2241 }; 2242 }; 2243 2244 venus_smmu: arm,smmu-venus@d40000 { 2245 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2246 reg = <0xd40000 0x20000>; 2247 #global-interrupts = <1>; 2248 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2256 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2257 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 2258 <&mmcc SMMU_VIDEO_AXI_CLK>; 2259 clock-names = "iface", "bus"; 2260 #iommu-cells = <1>; 2261 status = "okay"; 2262 }; 2263 2264 video-codec@c00000 { 2265 compatible = "qcom,msm8996-venus"; 2266 reg = <0x00c00000 0xff000>; 2267 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2268 power-domains = <&mmcc VENUS_GDSC>; 2269 clocks = <&mmcc VIDEO_CORE_CLK>, 2270 <&mmcc VIDEO_AHB_CLK>, 2271 <&mmcc VIDEO_AXI_CLK>, 2272 <&mmcc VIDEO_MAXI_CLK>; 2273 clock-names = "core", "iface", "bus", "mbus"; 2274 iommus = <&venus_smmu 0x00>, 2275 <&venus_smmu 0x01>, 2276 <&venus_smmu 0x0a>, 2277 <&venus_smmu 0x07>, 2278 <&venus_smmu 0x0e>, 2279 <&venus_smmu 0x0f>, 2280 <&venus_smmu 0x08>, 2281 <&venus_smmu 0x09>, 2282 <&venus_smmu 0x0b>, 2283 <&venus_smmu 0x0c>, 2284 <&venus_smmu 0x0d>, 2285 <&venus_smmu 0x10>, 2286 <&venus_smmu 0x11>, 2287 <&venus_smmu 0x21>, 2288 <&venus_smmu 0x28>, 2289 <&venus_smmu 0x29>, 2290 <&venus_smmu 0x2b>, 2291 <&venus_smmu 0x2c>, 2292 <&venus_smmu 0x2d>, 2293 <&venus_smmu 0x31>; 2294 memory-region = <&venus_region>; 2295 status = "okay"; 2296 2297 video-decoder { 2298 compatible = "venus-decoder"; 2299 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2300 clock-names = "core"; 2301 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2302 }; 2303 2304 video-encoder { 2305 compatible = "venus-encoder"; 2306 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2307 clock-names = "core"; 2308 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2309 }; 2310 }; 2311 }; 2312 2313 sound: sound { 2314 }; 2315 2316 adsp-pil { 2317 compatible = "qcom,msm8996-adsp-pil"; 2318 2319 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 2320 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2321 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2322 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2323 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2324 interrupt-names = "wdog", "fatal", "ready", 2325 "handover", "stop-ack"; 2326 2327 clocks = <&xo_board>; 2328 clock-names = "xo"; 2329 2330 memory-region = <&adsp_region>; 2331 2332 qcom,smem-states = <&adsp_smp2p_out 0>; 2333 qcom,smem-state-names = "stop"; 2334 2335 smd-edge { 2336 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2337 2338 label = "lpass"; 2339 mboxes = <&apcs_glb 8>; 2340 qcom,smd-edge = <1>; 2341 qcom,remote-pid = <2>; 2342 #address-cells = <1>; 2343 #size-cells = <0>; 2344 apr { 2345 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 2346 compatible = "qcom,apr-v2"; 2347 qcom,smd-channels = "apr_audio_svc"; 2348 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 2352 q6core { 2353 reg = <APR_SVC_ADSP_CORE>; 2354 compatible = "qcom,q6core"; 2355 }; 2356 2357 q6afe: q6afe { 2358 compatible = "qcom,q6afe"; 2359 reg = <APR_SVC_AFE>; 2360 q6afedai: dais { 2361 compatible = "qcom,q6afe-dais"; 2362 #address-cells = <1>; 2363 #size-cells = <0>; 2364 #sound-dai-cells = <1>; 2365 hdmi@1 { 2366 reg = <1>; 2367 }; 2368 }; 2369 }; 2370 2371 q6asm: q6asm { 2372 compatible = "qcom,q6asm"; 2373 reg = <APR_SVC_ASM>; 2374 q6asmdai: dais { 2375 compatible = "qcom,q6asm-dais"; 2376 #sound-dai-cells = <1>; 2377 iommus = <&lpass_q6_smmu 1>; 2378 }; 2379 }; 2380 2381 q6adm: q6adm { 2382 compatible = "qcom,q6adm"; 2383 reg = <APR_SVC_ADM>; 2384 q6routing: routing { 2385 compatible = "qcom,q6adm-routing"; 2386 #sound-dai-cells = <0>; 2387 }; 2388 }; 2389 }; 2390 2391 }; 2392 }; 2393 2394 adsp-smp2p { 2395 compatible = "qcom,smp2p"; 2396 qcom,smem = <443>, <429>; 2397 2398 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 2399 2400 mboxes = <&apcs_glb 10>; 2401 2402 qcom,local-pid = <0>; 2403 qcom,remote-pid = <2>; 2404 2405 adsp_smp2p_out: master-kernel { 2406 qcom,entry-name = "master-kernel"; 2407 #qcom,smem-state-cells = <1>; 2408 }; 2409 2410 adsp_smp2p_in: slave-kernel { 2411 qcom,entry-name = "slave-kernel"; 2412 2413 interrupt-controller; 2414 #interrupt-cells = <2>; 2415 }; 2416 }; 2417 2418 modem-smp2p { 2419 compatible = "qcom,smp2p"; 2420 qcom,smem = <435>, <428>; 2421 2422 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 2423 2424 mboxes = <&apcs_glb 14>; 2425 2426 qcom,local-pid = <0>; 2427 qcom,remote-pid = <1>; 2428 2429 modem_smp2p_out: master-kernel { 2430 qcom,entry-name = "master-kernel"; 2431 #qcom,smem-state-cells = <1>; 2432 }; 2433 2434 modem_smp2p_in: slave-kernel { 2435 qcom,entry-name = "slave-kernel"; 2436 2437 interrupt-controller; 2438 #interrupt-cells = <2>; 2439 }; 2440 }; 2441 2442 smp2p-slpi { 2443 compatible = "qcom,smp2p"; 2444 qcom,smem = <481>, <430>; 2445 2446 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 2447 2448 mboxes = <&apcs_glb 26>; 2449 2450 qcom,local-pid = <0>; 2451 qcom,remote-pid = <3>; 2452 2453 slpi_smp2p_in: slave-kernel { 2454 qcom,entry-name = "slave-kernel"; 2455 interrupt-controller; 2456 #interrupt-cells = <2>; 2457 }; 2458 2459 slpi_smp2p_out: master-kernel { 2460 qcom,entry-name = "master-kernel"; 2461 #qcom,smem-state-cells = <1>; 2462 }; 2463 }; 2464 2465}; 2466#include "msm8996-pins.dtsi" 2467