1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/power/qcom-rpmpd.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 qcom,msm-id = <292 0x0>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 memory { 21 device_type = "memory"; 22 /* We expect the bootloader to fill in the reg */ 23 reg = <0 0 0 0>; 24 }; 25 26 reserved-memory { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 memory@85800000 { 32 reg = <0x0 0x85800000 0x0 0x800000>; 33 no-map; 34 }; 35 36 smem_mem: smem-mem@86000000 { 37 reg = <0x0 0x86000000 0x0 0x200000>; 38 no-map; 39 }; 40 41 memory@86200000 { 42 reg = <0x0 0x86200000 0x0 0x2d00000>; 43 no-map; 44 }; 45 46 rmtfs { 47 compatible = "qcom,rmtfs-mem"; 48 49 size = <0x0 0x200000>; 50 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 51 no-map; 52 53 qcom,client-id = <1>; 54 qcom,vmid = <15>; 55 }; 56 }; 57 58 clocks { 59 xo: xo-board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <19200000>; 63 clock-output-names = "xo_board"; 64 }; 65 66 sleep_clk { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <32764>; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <2>; 75 #size-cells = <0>; 76 77 CPU0: cpu@0 { 78 device_type = "cpu"; 79 compatible = "arm,armv8"; 80 reg = <0x0 0x0>; 81 enable-method = "psci"; 82 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 83 next-level-cache = <&L2_0>; 84 L2_0: l2-cache { 85 compatible = "arm,arch-cache"; 86 cache-level = <2>; 87 }; 88 L1_I_0: l1-icache { 89 compatible = "arm,arch-cache"; 90 }; 91 L1_D_0: l1-dcache { 92 compatible = "arm,arch-cache"; 93 }; 94 }; 95 96 CPU1: cpu@1 { 97 device_type = "cpu"; 98 compatible = "arm,armv8"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 102 next-level-cache = <&L2_0>; 103 L1_I_1: l1-icache { 104 compatible = "arm,arch-cache"; 105 }; 106 L1_D_1: l1-dcache { 107 compatible = "arm,arch-cache"; 108 }; 109 }; 110 111 CPU2: cpu@2 { 112 device_type = "cpu"; 113 compatible = "arm,armv8"; 114 reg = <0x0 0x2>; 115 enable-method = "psci"; 116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 117 next-level-cache = <&L2_0>; 118 L1_I_2: l1-icache { 119 compatible = "arm,arch-cache"; 120 }; 121 L1_D_2: l1-dcache { 122 compatible = "arm,arch-cache"; 123 }; 124 }; 125 126 CPU3: cpu@3 { 127 device_type = "cpu"; 128 compatible = "arm,armv8"; 129 reg = <0x0 0x3>; 130 enable-method = "psci"; 131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 132 next-level-cache = <&L2_0>; 133 L1_I_3: l1-icache { 134 compatible = "arm,arch-cache"; 135 }; 136 L1_D_3: l1-dcache { 137 compatible = "arm,arch-cache"; 138 }; 139 }; 140 141 CPU4: cpu@100 { 142 device_type = "cpu"; 143 compatible = "arm,armv8"; 144 reg = <0x0 0x100>; 145 enable-method = "psci"; 146 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 147 next-level-cache = <&L2_1>; 148 L2_1: l2-cache { 149 compatible = "arm,arch-cache"; 150 cache-level = <2>; 151 }; 152 L1_I_100: l1-icache { 153 compatible = "arm,arch-cache"; 154 }; 155 L1_D_100: l1-dcache { 156 compatible = "arm,arch-cache"; 157 }; 158 }; 159 160 CPU5: cpu@101 { 161 device_type = "cpu"; 162 compatible = "arm,armv8"; 163 reg = <0x0 0x101>; 164 enable-method = "psci"; 165 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 166 next-level-cache = <&L2_1>; 167 L1_I_101: l1-icache { 168 compatible = "arm,arch-cache"; 169 }; 170 L1_D_101: l1-dcache { 171 compatible = "arm,arch-cache"; 172 }; 173 }; 174 175 CPU6: cpu@102 { 176 device_type = "cpu"; 177 compatible = "arm,armv8"; 178 reg = <0x0 0x102>; 179 enable-method = "psci"; 180 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 181 next-level-cache = <&L2_1>; 182 L1_I_102: l1-icache { 183 compatible = "arm,arch-cache"; 184 }; 185 L1_D_102: l1-dcache { 186 compatible = "arm,arch-cache"; 187 }; 188 }; 189 190 CPU7: cpu@103 { 191 device_type = "cpu"; 192 compatible = "arm,armv8"; 193 reg = <0x0 0x103>; 194 enable-method = "psci"; 195 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 196 next-level-cache = <&L2_1>; 197 L1_I_103: l1-icache { 198 compatible = "arm,arch-cache"; 199 }; 200 L1_D_103: l1-dcache { 201 compatible = "arm,arch-cache"; 202 }; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&CPU0>; 209 }; 210 211 core1 { 212 cpu = <&CPU1>; 213 }; 214 215 core2 { 216 cpu = <&CPU2>; 217 }; 218 219 core3 { 220 cpu = <&CPU3>; 221 }; 222 }; 223 224 cluster1 { 225 core0 { 226 cpu = <&CPU4>; 227 }; 228 229 core1 { 230 cpu = <&CPU5>; 231 }; 232 233 core2 { 234 cpu = <&CPU6>; 235 }; 236 237 core3 { 238 cpu = <&CPU7>; 239 }; 240 }; 241 }; 242 243 idle-states { 244 entry-method = "psci"; 245 246 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "little-retention"; 249 /* CPU Retention (C2D), L2 Active */ 250 arm,psci-suspend-param = <0x00000002>; 251 entry-latency-us = <81>; 252 exit-latency-us = <86>; 253 min-residency-us = <504>; 254 }; 255 256 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 257 compatible = "arm,idle-state"; 258 idle-state-name = "little-power-collapse"; 259 /* CPU + L2 Power Collapse (C3, D4) */ 260 arm,psci-suspend-param = <0x40000003>; 261 entry-latency-us = <814>; 262 exit-latency-us = <4562>; 263 min-residency-us = <9183>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-retention"; 270 /* CPU Retention (C2D), L2 Active */ 271 arm,psci-suspend-param = <0x00000002>; 272 entry-latency-us = <79>; 273 exit-latency-us = <82>; 274 min-residency-us = <1302>; 275 }; 276 277 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "big-power-collapse"; 280 /* CPU + L2 Power Collapse (C3, D4) */ 281 arm,psci-suspend-param = <0x40000003>; 282 entry-latency-us = <724>; 283 exit-latency-us = <2027>; 284 min-residency-us = <9419>; 285 local-timer-stop; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm { 292 compatible = "qcom,scm-msm8998", "qcom,scm"; 293 }; 294 }; 295 296 tcsr_mutex: hwlock { 297 compatible = "qcom,tcsr-mutex"; 298 syscon = <&tcsr_mutex_regs 0 0x1000>; 299 #hwlock-cells = <1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0"; 304 method = "smc"; 305 }; 306 307 rpm-glink { 308 compatible = "qcom,glink-rpm"; 309 310 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 311 qcom,rpm-msg-ram = <&rpm_msg_ram>; 312 mboxes = <&apcs_glb 0>; 313 314 rpm_requests: rpm-requests { 315 compatible = "qcom,rpm-msm8998"; 316 qcom,glink-channels = "rpm_requests"; 317 318 rpmcc: clock-controller { 319 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 320 #clock-cells = <1>; 321 }; 322 323 rpmpd: power-controller { 324 compatible = "qcom,msm8998-rpmpd"; 325 #power-domain-cells = <1>; 326 operating-points-v2 = <&rpmpd_opp_table>; 327 328 rpmpd_opp_table: opp-table { 329 compatible = "operating-points-v2"; 330 331 rpmpd_opp_ret: opp1 { 332 opp-level = <16>; 333 }; 334 335 rpmpd_opp_ret_plus: opp2 { 336 opp-level = <32>; 337 }; 338 339 rpmpd_opp_min_svs: opp3 { 340 opp-level = <48>; 341 }; 342 343 rpmpd_opp_low_svs: opp4 { 344 opp-level = <64>; 345 }; 346 347 rpmpd_opp_svs: opp5 { 348 opp-level = <128>; 349 }; 350 351 rpmpd_opp_svs_plus: opp6 { 352 opp-level = <192>; 353 }; 354 355 rpmpd_opp_nom: opp7 { 356 opp-level = <256>; 357 }; 358 359 rpmpd_opp_nom_plus: opp8 { 360 opp-level = <320>; 361 }; 362 363 rpmpd_opp_turbo: opp9 { 364 opp-level = <384>; 365 }; 366 367 rpmpd_opp_turbo_plus: opp10 { 368 opp-level = <512>; 369 }; 370 }; 371 }; 372 }; 373 }; 374 375 smem { 376 compatible = "qcom,smem"; 377 memory-region = <&smem_mem>; 378 hwlocks = <&tcsr_mutex 3>; 379 }; 380 381 smp2p-lpass { 382 compatible = "qcom,smp2p"; 383 qcom,smem = <443>, <429>; 384 385 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 386 387 mboxes = <&apcs_glb 10>; 388 389 qcom,local-pid = <0>; 390 qcom,remote-pid = <2>; 391 392 adsp_smp2p_out: master-kernel { 393 qcom,entry-name = "master-kernel"; 394 #qcom,smem-state-cells = <1>; 395 }; 396 397 adsp_smp2p_in: slave-kernel { 398 qcom,entry-name = "slave-kernel"; 399 400 interrupt-controller; 401 #interrupt-cells = <2>; 402 }; 403 }; 404 405 smp2p-mpss { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <435>, <428>; 408 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 409 mboxes = <&apcs_glb 14>; 410 qcom,local-pid = <0>; 411 qcom,remote-pid = <1>; 412 413 modem_smp2p_out: master-kernel { 414 qcom,entry-name = "master-kernel"; 415 #qcom,smem-state-cells = <1>; 416 }; 417 418 modem_smp2p_in: slave-kernel { 419 qcom,entry-name = "slave-kernel"; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 }; 423 }; 424 425 smp2p-slpi { 426 compatible = "qcom,smp2p"; 427 qcom,smem = <481>, <430>; 428 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&apcs_glb 26>; 430 qcom,local-pid = <0>; 431 qcom,remote-pid = <3>; 432 433 slpi_smp2p_out: master-kernel { 434 qcom,entry-name = "master-kernel"; 435 #qcom,smem-state-cells = <1>; 436 }; 437 438 slpi_smp2p_in: slave-kernel { 439 qcom,entry-name = "slave-kernel"; 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 }; 443 }; 444 445 thermal-zones { 446 cpu0-thermal { 447 polling-delay-passive = <250>; 448 polling-delay = <1000>; 449 450 thermal-sensors = <&tsens0 1>; 451 452 trips { 453 cpu0_alert0: trip-point@0 { 454 temperature = <75000>; 455 hysteresis = <2000>; 456 type = "passive"; 457 }; 458 459 cpu0_crit: cpu_crit { 460 temperature = <110000>; 461 hysteresis = <2000>; 462 type = "critical"; 463 }; 464 }; 465 }; 466 467 cpu1-thermal { 468 polling-delay-passive = <250>; 469 polling-delay = <1000>; 470 471 thermal-sensors = <&tsens0 2>; 472 473 trips { 474 cpu1_alert0: trip-point@0 { 475 temperature = <75000>; 476 hysteresis = <2000>; 477 type = "passive"; 478 }; 479 480 cpu1_crit: cpu_crit { 481 temperature = <110000>; 482 hysteresis = <2000>; 483 type = "critical"; 484 }; 485 }; 486 }; 487 488 cpu2-thermal { 489 polling-delay-passive = <250>; 490 polling-delay = <1000>; 491 492 thermal-sensors = <&tsens0 3>; 493 494 trips { 495 cpu2_alert0: trip-point@0 { 496 temperature = <75000>; 497 hysteresis = <2000>; 498 type = "passive"; 499 }; 500 501 cpu2_crit: cpu_crit { 502 temperature = <110000>; 503 hysteresis = <2000>; 504 type = "critical"; 505 }; 506 }; 507 }; 508 509 cpu3-thermal { 510 polling-delay-passive = <250>; 511 polling-delay = <1000>; 512 513 thermal-sensors = <&tsens0 4>; 514 515 trips { 516 cpu3_alert0: trip-point@0 { 517 temperature = <75000>; 518 hysteresis = <2000>; 519 type = "passive"; 520 }; 521 522 cpu3_crit: cpu_crit { 523 temperature = <110000>; 524 hysteresis = <2000>; 525 type = "critical"; 526 }; 527 }; 528 }; 529 530 cpu4-thermal { 531 polling-delay-passive = <250>; 532 polling-delay = <1000>; 533 534 thermal-sensors = <&tsens0 7>; 535 536 trips { 537 cpu4_alert0: trip-point@0 { 538 temperature = <75000>; 539 hysteresis = <2000>; 540 type = "passive"; 541 }; 542 543 cpu4_crit: cpu_crit { 544 temperature = <110000>; 545 hysteresis = <2000>; 546 type = "critical"; 547 }; 548 }; 549 }; 550 551 cpu5-thermal { 552 polling-delay-passive = <250>; 553 polling-delay = <1000>; 554 555 thermal-sensors = <&tsens0 8>; 556 557 trips { 558 cpu5_alert0: trip-point@0 { 559 temperature = <75000>; 560 hysteresis = <2000>; 561 type = "passive"; 562 }; 563 564 cpu5_crit: cpu_crit { 565 temperature = <110000>; 566 hysteresis = <2000>; 567 type = "critical"; 568 }; 569 }; 570 }; 571 572 cpu6-thermal { 573 polling-delay-passive = <250>; 574 polling-delay = <1000>; 575 576 thermal-sensors = <&tsens0 9>; 577 578 trips { 579 cpu6_alert0: trip-point@0 { 580 temperature = <75000>; 581 hysteresis = <2000>; 582 type = "passive"; 583 }; 584 585 cpu6_crit: cpu_crit { 586 temperature = <110000>; 587 hysteresis = <2000>; 588 type = "critical"; 589 }; 590 }; 591 }; 592 593 cpu7-thermal { 594 polling-delay-passive = <250>; 595 polling-delay = <1000>; 596 597 thermal-sensors = <&tsens0 10>; 598 599 trips { 600 cpu7_alert0: trip-point@0 { 601 temperature = <75000>; 602 hysteresis = <2000>; 603 type = "passive"; 604 }; 605 606 cpu7_crit: cpu_crit { 607 temperature = <110000>; 608 hysteresis = <2000>; 609 type = "critical"; 610 }; 611 }; 612 }; 613 614 gpu-thermal-bottom { 615 polling-delay-passive = <250>; 616 polling-delay = <1000>; 617 618 thermal-sensors = <&tsens0 12>; 619 620 trips { 621 gpu1_alert0: trip-point@0 { 622 temperature = <90000>; 623 hysteresis = <2000>; 624 type = "hot"; 625 }; 626 }; 627 }; 628 629 gpu-thermal-top { 630 polling-delay-passive = <250>; 631 polling-delay = <1000>; 632 633 thermal-sensors = <&tsens0 13>; 634 635 trips { 636 gpu2_alert0: trip-point@0 { 637 temperature = <90000>; 638 hysteresis = <2000>; 639 type = "hot"; 640 }; 641 }; 642 }; 643 644 clust0-mhm-thermal { 645 polling-delay-passive = <250>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsens0 5>; 649 650 trips { 651 cluster0_mhm_alert0: trip-point@0 { 652 temperature = <90000>; 653 hysteresis = <2000>; 654 type = "hot"; 655 }; 656 }; 657 }; 658 659 clust1-mhm-thermal { 660 polling-delay-passive = <250>; 661 polling-delay = <1000>; 662 663 thermal-sensors = <&tsens0 6>; 664 665 trips { 666 cluster1_mhm_alert0: trip-point@0 { 667 temperature = <90000>; 668 hysteresis = <2000>; 669 type = "hot"; 670 }; 671 }; 672 }; 673 674 cluster1-l2-thermal { 675 polling-delay-passive = <250>; 676 polling-delay = <1000>; 677 678 thermal-sensors = <&tsens0 11>; 679 680 trips { 681 cluster1_l2_alert0: trip-point@0 { 682 temperature = <90000>; 683 hysteresis = <2000>; 684 type = "hot"; 685 }; 686 }; 687 }; 688 689 modem-thermal { 690 polling-delay-passive = <250>; 691 polling-delay = <1000>; 692 693 thermal-sensors = <&tsens1 1>; 694 695 trips { 696 modem_alert0: trip-point@0 { 697 temperature = <90000>; 698 hysteresis = <2000>; 699 type = "hot"; 700 }; 701 }; 702 }; 703 704 mem-thermal { 705 polling-delay-passive = <250>; 706 polling-delay = <1000>; 707 708 thermal-sensors = <&tsens1 2>; 709 710 trips { 711 mem_alert0: trip-point@0 { 712 temperature = <90000>; 713 hysteresis = <2000>; 714 type = "hot"; 715 }; 716 }; 717 }; 718 719 wlan-thermal { 720 polling-delay-passive = <250>; 721 polling-delay = <1000>; 722 723 thermal-sensors = <&tsens1 3>; 724 725 trips { 726 wlan_alert0: trip-point@0 { 727 temperature = <90000>; 728 hysteresis = <2000>; 729 type = "hot"; 730 }; 731 }; 732 }; 733 734 q6-dsp-thermal { 735 polling-delay-passive = <250>; 736 polling-delay = <1000>; 737 738 thermal-sensors = <&tsens1 4>; 739 740 trips { 741 q6_dsp_alert0: trip-point@0 { 742 temperature = <90000>; 743 hysteresis = <2000>; 744 type = "hot"; 745 }; 746 }; 747 }; 748 749 camera-thermal { 750 polling-delay-passive = <250>; 751 polling-delay = <1000>; 752 753 thermal-sensors = <&tsens1 5>; 754 755 trips { 756 camera_alert0: trip-point@0 { 757 temperature = <90000>; 758 hysteresis = <2000>; 759 type = "hot"; 760 }; 761 }; 762 }; 763 764 multimedia-thermal { 765 polling-delay-passive = <250>; 766 polling-delay = <1000>; 767 768 thermal-sensors = <&tsens1 6>; 769 770 trips { 771 multimedia_alert0: trip-point@0 { 772 temperature = <90000>; 773 hysteresis = <2000>; 774 type = "hot"; 775 }; 776 }; 777 }; 778 }; 779 780 timer { 781 compatible = "arm,armv8-timer"; 782 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 783 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 784 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 785 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 786 }; 787 788 soc: soc { 789 #address-cells = <1>; 790 #size-cells = <1>; 791 ranges = <0 0 0 0xffffffff>; 792 compatible = "simple-bus"; 793 794 gcc: clock-controller@100000 { 795 compatible = "qcom,gcc-msm8998"; 796 #clock-cells = <1>; 797 #reset-cells = <1>; 798 #power-domain-cells = <1>; 799 reg = <0x00100000 0xb0000>; 800 }; 801 802 rpm_msg_ram: memory@778000 { 803 compatible = "qcom,rpm-msg-ram"; 804 reg = <0x00778000 0x7000>; 805 }; 806 807 qfprom: qfprom@780000 { 808 compatible = "qcom,qfprom"; 809 reg = <0x00780000 0x621c>; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 813 qusb2_hstx_trim: hstx-trim@423a { 814 reg = <0x423a 0x1>; 815 bits = <0 4>; 816 }; 817 }; 818 819 tsens0: thermal@10ab000 { 820 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 821 reg = <0x010ab000 0x1000>, /* TM */ 822 <0x010aa000 0x1000>; /* SROT */ 823 824 #qcom,sensors = <14>; 825 #thermal-sensor-cells = <1>; 826 }; 827 828 tsens1: thermal@10ae000 { 829 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 830 reg = <0x010ae000 0x1000>, /* TM */ 831 <0x010ad000 0x1000>; /* SROT */ 832 833 #qcom,sensors = <8>; 834 #thermal-sensor-cells = <1>; 835 }; 836 837 anoc1_smmu: iommu@1680000 { 838 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 839 reg = <0x01680000 0x10000>; 840 #iommu-cells = <1>; 841 842 #global-interrupts = <0>; 843 interrupts = 844 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 845 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 846 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 847 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 848 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 849 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 850 }; 851 852 pcie0: pci@1c00000 { 853 compatible = "qcom,pcie-msm8996"; 854 reg = <0x01c00000 0x2000>, 855 <0x1b000000 0xf1d>, 856 <0x1b000f20 0xa8>, 857 <0x1b100000 0x100000>; 858 reg-names = "parf", "dbi", "elbi", "config"; 859 device_type = "pci"; 860 linux,pci-domain = <0>; 861 bus-range = <0x00 0xff>; 862 #address-cells = <3>; 863 #size-cells = <2>; 864 num-lanes = <1>; 865 phys = <&pciephy>; 866 phy-names = "pciephy"; 867 868 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 869 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 870 871 #interrupt-cells = <1>; 872 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "msi"; 874 interrupt-map-mask = <0 0 0 0x7>; 875 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 876 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 877 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 878 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 879 880 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 881 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 882 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 883 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 884 <&gcc GCC_PCIE_0_AUX_CLK>; 885 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 886 887 power-domains = <&gcc PCIE_0_GDSC>; 888 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 889 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 890 }; 891 892 phy@1c06000 { 893 compatible = "qcom,msm8998-qmp-pcie-phy"; 894 reg = <0x01c06000 0x18c>; 895 #address-cells = <1>; 896 #size-cells = <1>; 897 ranges; 898 899 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 900 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 901 <&gcc GCC_PCIE_CLKREF_CLK>; 902 clock-names = "aux", "cfg_ahb", "ref"; 903 904 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 905 reset-names = "phy", "common"; 906 907 vdda-phy-supply = <&vreg_l1a_0p875>; 908 vdda-pll-supply = <&vreg_l2a_1p2>; 909 910 pciephy: lane@1c06800 { 911 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 912 #phy-cells = <0>; 913 914 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 915 clock-names = "pipe0"; 916 clock-output-names = "pcie_0_pipe_clk_src"; 917 #clock-cells = <0>; 918 }; 919 }; 920 921 ufshc: ufshc@1da4000 { 922 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 923 reg = <0x01da4000 0x2500>; 924 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 925 phys = <&ufsphy_lanes>; 926 phy-names = "ufsphy"; 927 lanes-per-direction = <2>; 928 power-domains = <&gcc UFS_GDSC>; 929 #reset-cells = <1>; 930 931 clock-names = 932 "core_clk", 933 "bus_aggr_clk", 934 "iface_clk", 935 "core_clk_unipro", 936 "ref_clk", 937 "tx_lane0_sync_clk", 938 "rx_lane0_sync_clk", 939 "rx_lane1_sync_clk"; 940 clocks = 941 <&gcc GCC_UFS_AXI_CLK>, 942 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 943 <&gcc GCC_UFS_AHB_CLK>, 944 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 945 <&rpmcc RPM_SMD_LN_BB_CLK1>, 946 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 947 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 948 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 949 freq-table-hz = 950 <50000000 200000000>, 951 <0 0>, 952 <0 0>, 953 <37500000 150000000>, 954 <0 0>, 955 <0 0>, 956 <0 0>, 957 <0 0>; 958 959 resets = <&gcc GCC_UFS_BCR>; 960 reset-names = "rst"; 961 }; 962 963 ufsphy: phy@1da7000 { 964 compatible = "qcom,msm8998-qmp-ufs-phy"; 965 reg = <0x01da7000 0x18c>; 966 #address-cells = <1>; 967 #size-cells = <1>; 968 ranges; 969 970 clock-names = 971 "ref", 972 "ref_aux"; 973 clocks = 974 <&gcc GCC_UFS_CLKREF_CLK>, 975 <&gcc GCC_UFS_PHY_AUX_CLK>; 976 977 reset-names = "ufsphy"; 978 resets = <&ufshc 0>; 979 980 ufsphy_lanes: lanes@1da7400 { 981 reg = <0x01da7400 0x128>, 982 <0x01da7600 0x1fc>, 983 <0x01da7c00 0x1dc>, 984 <0x01da7800 0x128>, 985 <0x01da7a00 0x1fc>; 986 #phy-cells = <0>; 987 }; 988 }; 989 990 tcsr_mutex_regs: syscon@1f40000 { 991 compatible = "syscon"; 992 reg = <0x01f40000 0x40000>; 993 }; 994 995 tlmm: pinctrl@3400000 { 996 compatible = "qcom,msm8998-pinctrl"; 997 reg = <0x03400000 0xc00000>; 998 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 999 gpio-controller; 1000 #gpio-cells = <0x2>; 1001 interrupt-controller; 1002 #interrupt-cells = <0x2>; 1003 }; 1004 1005 stm: stm@6002000 { 1006 compatible = "arm,coresight-stm", "arm,primecell"; 1007 reg = <0x06002000 0x1000>, 1008 <0x16280000 0x180000>; 1009 reg-names = "stm-base", "stm-data-base"; 1010 status = "disabled"; 1011 1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1013 clock-names = "apb_pclk", "atclk"; 1014 1015 out-ports { 1016 port { 1017 stm_out: endpoint { 1018 remote-endpoint = <&funnel0_in7>; 1019 }; 1020 }; 1021 }; 1022 }; 1023 1024 funnel1: funnel@6041000 { 1025 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1026 reg = <0x06041000 0x1000>; 1027 status = "disabled"; 1028 1029 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1030 clock-names = "apb_pclk", "atclk"; 1031 1032 out-ports { 1033 port { 1034 funnel0_out: endpoint { 1035 remote-endpoint = 1036 <&merge_funnel_in0>; 1037 }; 1038 }; 1039 }; 1040 1041 in-ports { 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 1045 port@7 { 1046 reg = <7>; 1047 funnel0_in7: endpoint { 1048 remote-endpoint = <&stm_out>; 1049 }; 1050 }; 1051 }; 1052 }; 1053 1054 funnel2: funnel@6042000 { 1055 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1056 reg = <0x06042000 0x1000>; 1057 status = "disabled"; 1058 1059 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1060 clock-names = "apb_pclk", "atclk"; 1061 1062 out-ports { 1063 port { 1064 funnel1_out: endpoint { 1065 remote-endpoint = 1066 <&merge_funnel_in1>; 1067 }; 1068 }; 1069 }; 1070 1071 in-ports { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 1075 port@6 { 1076 reg = <6>; 1077 funnel1_in6: endpoint { 1078 remote-endpoint = 1079 <&apss_merge_funnel_out>; 1080 }; 1081 }; 1082 }; 1083 }; 1084 1085 funnel3: funnel@6045000 { 1086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1087 reg = <0x06045000 0x1000>; 1088 status = "disabled"; 1089 1090 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1091 clock-names = "apb_pclk", "atclk"; 1092 1093 out-ports { 1094 port { 1095 merge_funnel_out: endpoint { 1096 remote-endpoint = 1097 <&etf_in>; 1098 }; 1099 }; 1100 }; 1101 1102 in-ports { 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 1106 port@0 { 1107 reg = <0>; 1108 merge_funnel_in0: endpoint { 1109 remote-endpoint = 1110 <&funnel0_out>; 1111 }; 1112 }; 1113 1114 port@1 { 1115 reg = <1>; 1116 merge_funnel_in1: endpoint { 1117 remote-endpoint = 1118 <&funnel1_out>; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 replicator1: replicator@6046000 { 1125 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1126 reg = <0x06046000 0x1000>; 1127 status = "disabled"; 1128 1129 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1130 clock-names = "apb_pclk", "atclk"; 1131 1132 out-ports { 1133 port { 1134 replicator_out: endpoint { 1135 remote-endpoint = <&etr_in>; 1136 }; 1137 }; 1138 }; 1139 1140 in-ports { 1141 port { 1142 replicator_in: endpoint { 1143 remote-endpoint = <&etf_out>; 1144 }; 1145 }; 1146 }; 1147 }; 1148 1149 etf: etf@6047000 { 1150 compatible = "arm,coresight-tmc", "arm,primecell"; 1151 reg = <0x06047000 0x1000>; 1152 status = "disabled"; 1153 1154 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1155 clock-names = "apb_pclk", "atclk"; 1156 1157 out-ports { 1158 port { 1159 etf_out: endpoint { 1160 remote-endpoint = 1161 <&replicator_in>; 1162 }; 1163 }; 1164 }; 1165 1166 in-ports { 1167 port { 1168 etf_in: endpoint { 1169 remote-endpoint = 1170 <&merge_funnel_out>; 1171 }; 1172 }; 1173 }; 1174 }; 1175 1176 etr: etr@6048000 { 1177 compatible = "arm,coresight-tmc", "arm,primecell"; 1178 reg = <0x06048000 0x1000>; 1179 status = "disabled"; 1180 1181 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1182 clock-names = "apb_pclk", "atclk"; 1183 arm,scatter-gather; 1184 1185 in-ports { 1186 port { 1187 etr_in: endpoint { 1188 remote-endpoint = 1189 <&replicator_out>; 1190 }; 1191 }; 1192 }; 1193 }; 1194 1195 etm1: etm@7840000 { 1196 compatible = "arm,coresight-etm4x", "arm,primecell"; 1197 reg = <0x07840000 0x1000>; 1198 status = "disabled"; 1199 1200 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1201 clock-names = "apb_pclk", "atclk"; 1202 1203 cpu = <&CPU0>; 1204 1205 out-ports { 1206 port { 1207 etm0_out: endpoint { 1208 remote-endpoint = 1209 <&apss_funnel_in0>; 1210 }; 1211 }; 1212 }; 1213 }; 1214 1215 etm2: etm@7940000 { 1216 compatible = "arm,coresight-etm4x", "arm,primecell"; 1217 reg = <0x07940000 0x1000>; 1218 status = "disabled"; 1219 1220 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1221 clock-names = "apb_pclk", "atclk"; 1222 1223 cpu = <&CPU1>; 1224 1225 out-ports { 1226 port { 1227 etm1_out: endpoint { 1228 remote-endpoint = 1229 <&apss_funnel_in1>; 1230 }; 1231 }; 1232 }; 1233 }; 1234 1235 etm3: etm@7a40000 { 1236 compatible = "arm,coresight-etm4x", "arm,primecell"; 1237 reg = <0x07a40000 0x1000>; 1238 status = "disabled"; 1239 1240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1241 clock-names = "apb_pclk", "atclk"; 1242 1243 cpu = <&CPU2>; 1244 1245 out-ports { 1246 port { 1247 etm2_out: endpoint { 1248 remote-endpoint = 1249 <&apss_funnel_in2>; 1250 }; 1251 }; 1252 }; 1253 }; 1254 1255 etm4: etm@7b40000 { 1256 compatible = "arm,coresight-etm4x", "arm,primecell"; 1257 reg = <0x07b40000 0x1000>; 1258 status = "disabled"; 1259 1260 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1261 clock-names = "apb_pclk", "atclk"; 1262 1263 cpu = <&CPU3>; 1264 1265 out-ports { 1266 port { 1267 etm3_out: endpoint { 1268 remote-endpoint = 1269 <&apss_funnel_in3>; 1270 }; 1271 }; 1272 }; 1273 }; 1274 1275 funnel4: funnel@7b60000 { /* APSS Funnel */ 1276 compatible = "arm,coresight-etm4x", "arm,primecell"; 1277 reg = <0x07b60000 0x1000>; 1278 status = "disabled"; 1279 1280 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1281 clock-names = "apb_pclk", "atclk"; 1282 1283 out-ports { 1284 port { 1285 apss_funnel_out: endpoint { 1286 remote-endpoint = 1287 <&apss_merge_funnel_in>; 1288 }; 1289 }; 1290 }; 1291 1292 in-ports { 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 1296 port@0 { 1297 reg = <0>; 1298 apss_funnel_in0: endpoint { 1299 remote-endpoint = 1300 <&etm0_out>; 1301 }; 1302 }; 1303 1304 port@1 { 1305 reg = <1>; 1306 apss_funnel_in1: endpoint { 1307 remote-endpoint = 1308 <&etm1_out>; 1309 }; 1310 }; 1311 1312 port@2 { 1313 reg = <2>; 1314 apss_funnel_in2: endpoint { 1315 remote-endpoint = 1316 <&etm2_out>; 1317 }; 1318 }; 1319 1320 port@3 { 1321 reg = <3>; 1322 apss_funnel_in3: endpoint { 1323 remote-endpoint = 1324 <&etm3_out>; 1325 }; 1326 }; 1327 1328 port@4 { 1329 reg = <4>; 1330 apss_funnel_in4: endpoint { 1331 remote-endpoint = 1332 <&etm4_out>; 1333 }; 1334 }; 1335 1336 port@5 { 1337 reg = <5>; 1338 apss_funnel_in5: endpoint { 1339 remote-endpoint = 1340 <&etm5_out>; 1341 }; 1342 }; 1343 1344 port@6 { 1345 reg = <6>; 1346 apss_funnel_in6: endpoint { 1347 remote-endpoint = 1348 <&etm6_out>; 1349 }; 1350 }; 1351 1352 port@7 { 1353 reg = <7>; 1354 apss_funnel_in7: endpoint { 1355 remote-endpoint = 1356 <&etm7_out>; 1357 }; 1358 }; 1359 }; 1360 }; 1361 1362 funnel5: funnel@7b70000 { 1363 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1364 reg = <0x07b70000 0x1000>; 1365 status = "disabled"; 1366 1367 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1368 clock-names = "apb_pclk", "atclk"; 1369 1370 out-ports { 1371 port { 1372 apss_merge_funnel_out: endpoint { 1373 remote-endpoint = 1374 <&funnel1_in6>; 1375 }; 1376 }; 1377 }; 1378 1379 in-ports { 1380 port { 1381 apss_merge_funnel_in: endpoint { 1382 remote-endpoint = 1383 <&apss_funnel_out>; 1384 }; 1385 }; 1386 }; 1387 }; 1388 1389 etm5: etm@7c40000 { 1390 compatible = "arm,coresight-etm4x", "arm,primecell"; 1391 reg = <0x07c40000 0x1000>; 1392 status = "disabled"; 1393 1394 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1395 clock-names = "apb_pclk", "atclk"; 1396 1397 cpu = <&CPU4>; 1398 1399 out-ports { 1400 port{ 1401 etm4_out: endpoint { 1402 remote-endpoint = <&apss_funnel_in4>; 1403 }; 1404 }; 1405 }; 1406 }; 1407 1408 etm6: etm@7d40000 { 1409 compatible = "arm,coresight-etm4x", "arm,primecell"; 1410 reg = <0x07d40000 0x1000>; 1411 status = "disabled"; 1412 1413 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1414 clock-names = "apb_pclk", "atclk"; 1415 1416 cpu = <&CPU5>; 1417 1418 out-ports { 1419 port{ 1420 etm5_out: endpoint { 1421 remote-endpoint = <&apss_funnel_in5>; 1422 }; 1423 }; 1424 }; 1425 }; 1426 1427 etm7: etm@7e40000 { 1428 compatible = "arm,coresight-etm4x", "arm,primecell"; 1429 reg = <0x07e40000 0x1000>; 1430 status = "disabled"; 1431 1432 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1433 clock-names = "apb_pclk", "atclk"; 1434 1435 cpu = <&CPU6>; 1436 1437 out-ports { 1438 port{ 1439 etm6_out: endpoint { 1440 remote-endpoint = <&apss_funnel_in6>; 1441 }; 1442 }; 1443 }; 1444 }; 1445 1446 etm8: etm@7f40000 { 1447 compatible = "arm,coresight-etm4x", "arm,primecell"; 1448 reg = <0x07f40000 0x1000>; 1449 status = "disabled"; 1450 1451 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1452 clock-names = "apb_pclk", "atclk"; 1453 1454 cpu = <&CPU7>; 1455 1456 out-ports { 1457 port{ 1458 etm7_out: endpoint { 1459 remote-endpoint = <&apss_funnel_in7>; 1460 }; 1461 }; 1462 }; 1463 }; 1464 1465 spmi_bus: spmi@800f000 { 1466 compatible = "qcom,spmi-pmic-arb"; 1467 reg = <0x0800f000 0x1000>, 1468 <0x08400000 0x1000000>, 1469 <0x09400000 0x1000000>, 1470 <0x0a400000 0x220000>, 1471 <0x0800a000 0x3000>; 1472 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1473 interrupt-names = "periph_irq"; 1474 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1475 qcom,ee = <0>; 1476 qcom,channel = <0>; 1477 #address-cells = <2>; 1478 #size-cells = <0>; 1479 interrupt-controller; 1480 #interrupt-cells = <4>; 1481 cell-index = <0>; 1482 }; 1483 1484 usb3: usb@a8f8800 { 1485 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 1486 reg = <0x0a8f8800 0x400>; 1487 status = "disabled"; 1488 #address-cells = <1>; 1489 #size-cells = <1>; 1490 ranges; 1491 1492 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1493 <&gcc GCC_USB30_MASTER_CLK>, 1494 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 1495 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1496 <&gcc GCC_USB30_SLEEP_CLK>; 1497 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1498 "sleep"; 1499 1500 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1501 <&gcc GCC_USB30_MASTER_CLK>; 1502 assigned-clock-rates = <19200000>, <120000000>; 1503 1504 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1506 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1507 1508 power-domains = <&gcc USB_30_GDSC>; 1509 1510 resets = <&gcc GCC_USB_30_BCR>; 1511 1512 usb3_dwc3: dwc3@a800000 { 1513 compatible = "snps,dwc3"; 1514 reg = <0x0a800000 0xcd00>; 1515 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1516 snps,dis_u2_susphy_quirk; 1517 snps,dis_enblslpm_quirk; 1518 phys = <&qusb2phy>, <&usb1_ssphy>; 1519 phy-names = "usb2-phy", "usb3-phy"; 1520 snps,has-lpm-erratum; 1521 snps,hird-threshold = /bits/ 8 <0x10>; 1522 }; 1523 }; 1524 1525 usb3phy: phy@c010000 { 1526 compatible = "qcom,msm8998-qmp-usb3-phy"; 1527 reg = <0x0c010000 0x18c>; 1528 status = "disabled"; 1529 #clock-cells = <1>; 1530 #address-cells = <1>; 1531 #size-cells = <1>; 1532 ranges; 1533 1534 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1535 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1536 <&gcc GCC_USB3_CLKREF_CLK>; 1537 clock-names = "aux", "cfg_ahb", "ref"; 1538 1539 resets = <&gcc GCC_USB3_PHY_BCR>, 1540 <&gcc GCC_USB3PHY_PHY_BCR>; 1541 reset-names = "phy", "common"; 1542 1543 usb1_ssphy: lane@c010200 { 1544 reg = <0xc010200 0x128>, 1545 <0xc010400 0x200>, 1546 <0xc010c00 0x20c>, 1547 <0xc010600 0x128>, 1548 <0xc010800 0x200>; 1549 #phy-cells = <0>; 1550 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1551 clock-names = "pipe0"; 1552 clock-output-names = "usb3_phy_pipe_clk_src"; 1553 }; 1554 }; 1555 1556 qusb2phy: phy@c012000 { 1557 compatible = "qcom,msm8998-qusb2-phy"; 1558 reg = <0x0c012000 0x2a8>; 1559 status = "disabled"; 1560 #phy-cells = <0>; 1561 1562 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1563 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1564 clock-names = "cfg_ahb", "ref"; 1565 1566 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1567 1568 nvmem-cells = <&qusb2_hstx_trim>; 1569 }; 1570 1571 sdhc2: sdhci@c0a4900 { 1572 compatible = "qcom,sdhci-msm-v4"; 1573 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 1574 reg-names = "hc_mem", "core_mem"; 1575 1576 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1578 interrupt-names = "hc_irq", "pwr_irq"; 1579 1580 clock-names = "iface", "core", "xo"; 1581 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1582 <&gcc GCC_SDCC2_APPS_CLK>, 1583 <&xo>; 1584 bus-width = <4>; 1585 status = "disabled"; 1586 }; 1587 1588 blsp1_i2c1: i2c@c175000 { 1589 compatible = "qcom,i2c-qup-v2.2.1"; 1590 reg = <0x0c175000 0x600>; 1591 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1592 1593 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1594 <&gcc GCC_BLSP1_AHB_CLK>; 1595 clock-names = "core", "iface"; 1596 clock-frequency = <400000>; 1597 1598 status = "disabled"; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 }; 1602 1603 blsp1_i2c2: i2c@c176000 { 1604 compatible = "qcom,i2c-qup-v2.2.1"; 1605 reg = <0x0c176000 0x600>; 1606 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1607 1608 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1609 <&gcc GCC_BLSP1_AHB_CLK>; 1610 clock-names = "core", "iface"; 1611 clock-frequency = <400000>; 1612 1613 status = "disabled"; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 }; 1617 1618 blsp1_i2c3: i2c@c177000 { 1619 compatible = "qcom,i2c-qup-v2.2.1"; 1620 reg = <0x0c177000 0x600>; 1621 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1622 1623 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1624 <&gcc GCC_BLSP1_AHB_CLK>; 1625 clock-names = "core", "iface"; 1626 clock-frequency = <400000>; 1627 1628 status = "disabled"; 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 }; 1632 1633 blsp1_i2c4: i2c@c178000 { 1634 compatible = "qcom,i2c-qup-v2.2.1"; 1635 reg = <0x0c178000 0x600>; 1636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1637 1638 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1639 <&gcc GCC_BLSP1_AHB_CLK>; 1640 clock-names = "core", "iface"; 1641 clock-frequency = <400000>; 1642 1643 status = "disabled"; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 }; 1647 1648 blsp1_i2c5: i2c@c179000 { 1649 compatible = "qcom,i2c-qup-v2.2.1"; 1650 reg = <0x0c179000 0x600>; 1651 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1652 1653 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1654 <&gcc GCC_BLSP1_AHB_CLK>; 1655 clock-names = "core", "iface"; 1656 clock-frequency = <400000>; 1657 1658 status = "disabled"; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 }; 1662 1663 blsp1_i2c6: i2c@c17a000 { 1664 compatible = "qcom,i2c-qup-v2.2.1"; 1665 reg = <0x0c17a000 0x600>; 1666 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1667 1668 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1669 <&gcc GCC_BLSP1_AHB_CLK>; 1670 clock-names = "core", "iface"; 1671 clock-frequency = <400000>; 1672 1673 status = "disabled"; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 }; 1677 1678 blsp2_uart1: serial@c1b0000 { 1679 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1680 reg = <0x0c1b0000 0x1000>; 1681 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1682 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1683 <&gcc GCC_BLSP2_AHB_CLK>; 1684 clock-names = "core", "iface"; 1685 status = "disabled"; 1686 }; 1687 1688 blsp2_i2c0: i2c@c1b5000 { 1689 compatible = "qcom,i2c-qup-v2.2.1"; 1690 reg = <0x0c1b5000 0x600>; 1691 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1692 1693 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1694 <&gcc GCC_BLSP2_AHB_CLK>; 1695 clock-names = "core", "iface"; 1696 clock-frequency = <400000>; 1697 1698 status = "disabled"; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 }; 1702 1703 blsp2_i2c1: i2c@c1b6000 { 1704 compatible = "qcom,i2c-qup-v2.2.1"; 1705 reg = <0x0c1b6000 0x600>; 1706 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1707 1708 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1709 <&gcc GCC_BLSP2_AHB_CLK>; 1710 clock-names = "core", "iface"; 1711 clock-frequency = <400000>; 1712 1713 status = "disabled"; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 }; 1717 1718 blsp2_i2c2: i2c@c1b7000 { 1719 compatible = "qcom,i2c-qup-v2.2.1"; 1720 reg = <0x0c1b7000 0x600>; 1721 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1722 1723 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1724 <&gcc GCC_BLSP2_AHB_CLK>; 1725 clock-names = "core", "iface"; 1726 clock-frequency = <400000>; 1727 1728 status = "disabled"; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 }; 1732 1733 blsp2_i2c3: i2c@c1b8000 { 1734 compatible = "qcom,i2c-qup-v2.2.1"; 1735 reg = <0x0c1b8000 0x600>; 1736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1737 1738 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1739 <&gcc GCC_BLSP2_AHB_CLK>; 1740 clock-names = "core", "iface"; 1741 clock-frequency = <400000>; 1742 1743 status = "disabled"; 1744 #address-cells = <1>; 1745 #size-cells = <0>; 1746 }; 1747 1748 blsp2_i2c4: i2c@c1b9000 { 1749 compatible = "qcom,i2c-qup-v2.2.1"; 1750 reg = <0x0c1b9000 0x600>; 1751 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1752 1753 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1754 <&gcc GCC_BLSP2_AHB_CLK>; 1755 clock-names = "core", "iface"; 1756 clock-frequency = <400000>; 1757 1758 status = "disabled"; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 }; 1762 1763 blsp2_i2c5: i2c@c1ba000 { 1764 compatible = "qcom,i2c-qup-v2.2.1"; 1765 reg = <0x0c1ba000 0x600>; 1766 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1767 1768 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1769 <&gcc GCC_BLSP2_AHB_CLK>; 1770 clock-names = "core", "iface"; 1771 clock-frequency = <400000>; 1772 1773 status = "disabled"; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 }; 1777 1778 apcs_glb: mailbox@17911000 { 1779 compatible = "qcom,msm8998-apcs-hmss-global"; 1780 reg = <0x17911000 0x1000>; 1781 1782 #mbox-cells = <1>; 1783 }; 1784 1785 timer@17920000 { 1786 #address-cells = <1>; 1787 #size-cells = <1>; 1788 ranges; 1789 compatible = "arm,armv7-timer-mem"; 1790 reg = <0x17920000 0x1000>; 1791 1792 frame@17921000 { 1793 frame-number = <0>; 1794 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1796 reg = <0x17921000 0x1000>, 1797 <0x17922000 0x1000>; 1798 }; 1799 1800 frame@17923000 { 1801 frame-number = <1>; 1802 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1803 reg = <0x17923000 0x1000>; 1804 status = "disabled"; 1805 }; 1806 1807 frame@17924000 { 1808 frame-number = <2>; 1809 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1810 reg = <0x17924000 0x1000>; 1811 status = "disabled"; 1812 }; 1813 1814 frame@17925000 { 1815 frame-number = <3>; 1816 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1817 reg = <0x17925000 0x1000>; 1818 status = "disabled"; 1819 }; 1820 1821 frame@17926000 { 1822 frame-number = <4>; 1823 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1824 reg = <0x17926000 0x1000>; 1825 status = "disabled"; 1826 }; 1827 1828 frame@17927000 { 1829 frame-number = <5>; 1830 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1831 reg = <0x17927000 0x1000>; 1832 status = "disabled"; 1833 }; 1834 1835 frame@17928000 { 1836 frame-number = <6>; 1837 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1838 reg = <0x17928000 0x1000>; 1839 status = "disabled"; 1840 }; 1841 }; 1842 1843 intc: interrupt-controller@17a00000 { 1844 compatible = "arm,gic-v3"; 1845 reg = <0x17a00000 0x10000>, /* GICD */ 1846 <0x17b00000 0x100000>; /* GICR * 8 */ 1847 #interrupt-cells = <3>; 1848 #address-cells = <1>; 1849 #size-cells = <1>; 1850 ranges; 1851 interrupt-controller; 1852 #redistributor-regions = <1>; 1853 redistributor-stride = <0x0 0x20000>; 1854 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1855 }; 1856 }; 1857}; 1858 1859#include "msm8998-pins.dtsi" 1860