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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a774c0-sysc.h>
11
12/ {
13	compatible = "renesas,r8a774c0";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	/*
18	 * The external audio clocks are configured as 0 Hz fixed frequency
19	 * clocks by default.
20	 * Boards that provide audio clocks should override them.
21	 */
22	audio_clk_a: audio_clk_a {
23		compatible = "fixed-clock";
24		#clock-cells = <0>;
25		clock-frequency = <0>;
26	};
27
28	audio_clk_b: audio_clk_b {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31		clock-frequency = <0>;
32	};
33
34	audio_clk_c: audio_clk_c {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <0>;
38	};
39
40	/* External CAN clock - to be overridden by boards that provide it */
41	can_clk: can {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <0>;
45	};
46
47	cluster1_opp: opp_table10 {
48		compatible = "operating-points-v2";
49		opp-shared;
50		opp-800000000 {
51			opp-hz = /bits/ 64 <800000000>;
52			clock-latency-ns = <300000>;
53		};
54		opp-1000000000 {
55			opp-hz = /bits/ 64 <1000000000>;
56			clock-latency-ns = <300000>;
57		};
58		opp-1200000000 {
59			opp-hz = /bits/ 64 <1200000000>;
60			clock-latency-ns = <300000>;
61			opp-suspend;
62		};
63	};
64
65	cpus {
66		#address-cells = <1>;
67		#size-cells = <0>;
68
69		a53_0: cpu@0 {
70			compatible = "arm,cortex-a53";
71			reg = <0>;
72			device_type = "cpu";
73			power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
74			next-level-cache = <&L2_CA53>;
75			enable-method = "psci";
76			clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
77			operating-points-v2 = <&cluster1_opp>;
78		};
79
80		a53_1: cpu@1 {
81			compatible = "arm,cortex-a53";
82			reg = <1>;
83			device_type = "cpu";
84			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
85			next-level-cache = <&L2_CA53>;
86			enable-method = "psci";
87			clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
88			operating-points-v2 = <&cluster1_opp>;
89		};
90
91		L2_CA53: cache-controller-0 {
92			compatible = "cache";
93			power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
94			cache-unified;
95			cache-level = <2>;
96		};
97	};
98
99	extal_clk: extal {
100		compatible = "fixed-clock";
101		#clock-cells = <0>;
102		/* This value must be overridden by the board */
103		clock-frequency = <0>;
104	};
105
106	/* External PCIe clock - can be overridden by the board */
107	pcie_bus_clk: pcie_bus {
108		compatible = "fixed-clock";
109		#clock-cells = <0>;
110		clock-frequency = <0>;
111	};
112
113	pmu_a53 {
114		compatible = "arm,cortex-a53-pmu";
115		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
116				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
117		interrupt-affinity = <&a53_0>, <&a53_1>;
118	};
119
120	psci {
121		compatible = "arm,psci-1.0", "arm,psci-0.2";
122		method = "smc";
123	};
124
125	/* External SCIF clock - to be overridden by boards that provide it */
126	scif_clk: scif {
127		compatible = "fixed-clock";
128		#clock-cells = <0>;
129		clock-frequency = <0>;
130	};
131
132	soc: soc {
133		compatible = "simple-bus";
134		interrupt-parent = <&gic>;
135		#address-cells = <2>;
136		#size-cells = <2>;
137		ranges;
138
139		rwdt: watchdog@e6020000 {
140			compatible = "renesas,r8a774c0-wdt",
141				     "renesas,rcar-gen3-wdt";
142			reg = <0 0xe6020000 0 0x0c>;
143			clocks = <&cpg CPG_MOD 402>;
144			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
145			resets = <&cpg 402>;
146			status = "disabled";
147		};
148
149		gpio0: gpio@e6050000 {
150			compatible = "renesas,gpio-r8a774c0",
151				     "renesas,rcar-gen3-gpio";
152			reg = <0 0xe6050000 0 0x50>;
153			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
154			#gpio-cells = <2>;
155			gpio-controller;
156			gpio-ranges = <&pfc 0 0 18>;
157			#interrupt-cells = <2>;
158			interrupt-controller;
159			clocks = <&cpg CPG_MOD 912>;
160			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
161			resets = <&cpg 912>;
162		};
163
164		gpio1: gpio@e6051000 {
165			compatible = "renesas,gpio-r8a774c0",
166				     "renesas,rcar-gen3-gpio";
167			reg = <0 0xe6051000 0 0x50>;
168			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
169			#gpio-cells = <2>;
170			gpio-controller;
171			gpio-ranges = <&pfc 0 32 23>;
172			#interrupt-cells = <2>;
173			interrupt-controller;
174			clocks = <&cpg CPG_MOD 911>;
175			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
176			resets = <&cpg 911>;
177		};
178
179		gpio2: gpio@e6052000 {
180			compatible = "renesas,gpio-r8a774c0",
181				     "renesas,rcar-gen3-gpio";
182			reg = <0 0xe6052000 0 0x50>;
183			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
184			#gpio-cells = <2>;
185			gpio-controller;
186			gpio-ranges = <&pfc 0 64 26>;
187			#interrupt-cells = <2>;
188			interrupt-controller;
189			clocks = <&cpg CPG_MOD 910>;
190			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
191			resets = <&cpg 910>;
192		};
193
194		gpio3: gpio@e6053000 {
195			compatible = "renesas,gpio-r8a774c0",
196				     "renesas,rcar-gen3-gpio";
197			reg = <0 0xe6053000 0 0x50>;
198			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
199			#gpio-cells = <2>;
200			gpio-controller;
201			gpio-ranges = <&pfc 0 96 16>;
202			#interrupt-cells = <2>;
203			interrupt-controller;
204			clocks = <&cpg CPG_MOD 909>;
205			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
206			resets = <&cpg 909>;
207		};
208
209		gpio4: gpio@e6054000 {
210			compatible = "renesas,gpio-r8a774c0",
211				     "renesas,rcar-gen3-gpio";
212			reg = <0 0xe6054000 0 0x50>;
213			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
214			#gpio-cells = <2>;
215			gpio-controller;
216			gpio-ranges = <&pfc 0 128 11>;
217			#interrupt-cells = <2>;
218			interrupt-controller;
219			clocks = <&cpg CPG_MOD 908>;
220			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
221			resets = <&cpg 908>;
222		};
223
224		gpio5: gpio@e6055000 {
225			compatible = "renesas,gpio-r8a774c0",
226				     "renesas,rcar-gen3-gpio";
227			reg = <0 0xe6055000 0 0x50>;
228			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
229			#gpio-cells = <2>;
230			gpio-controller;
231			gpio-ranges = <&pfc 0 160 20>;
232			#interrupt-cells = <2>;
233			interrupt-controller;
234			clocks = <&cpg CPG_MOD 907>;
235			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
236			resets = <&cpg 907>;
237		};
238
239		gpio6: gpio@e6055400 {
240			compatible = "renesas,gpio-r8a774c0",
241				     "renesas,rcar-gen3-gpio";
242			reg = <0 0xe6055400 0 0x50>;
243			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
244			#gpio-cells = <2>;
245			gpio-controller;
246			gpio-ranges = <&pfc 0 192 18>;
247			#interrupt-cells = <2>;
248			interrupt-controller;
249			clocks = <&cpg CPG_MOD 906>;
250			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
251			resets = <&cpg 906>;
252		};
253
254		pfc: pin-controller@e6060000 {
255			compatible = "renesas,pfc-r8a774c0";
256			reg = <0 0xe6060000 0 0x508>;
257		};
258
259		cmt0: timer@e60f0000 {
260			compatible = "renesas,r8a774c0-cmt0",
261				     "renesas,rcar-gen3-cmt0";
262			reg = <0 0xe60f0000 0 0x1004>;
263			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
264				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
265			clocks = <&cpg CPG_MOD 303>;
266			clock-names = "fck";
267			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
268			resets = <&cpg 303>;
269			status = "disabled";
270		};
271
272		cmt1: timer@e6130000 {
273			compatible = "renesas,r8a774c0-cmt1",
274				     "renesas,rcar-gen3-cmt1";
275			reg = <0 0xe6130000 0 0x1004>;
276			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
277				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
278				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
279				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
280				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
281				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
282				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
283				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
284			clocks = <&cpg CPG_MOD 302>;
285			clock-names = "fck";
286			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
287			resets = <&cpg 302>;
288			status = "disabled";
289		};
290
291		cmt2: timer@e6140000 {
292			compatible = "renesas,r8a774c0-cmt1",
293				     "renesas,rcar-gen3-cmt1";
294			reg = <0 0xe6140000 0 0x1004>;
295			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
296				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
297				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
298				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
299				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
300				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
301				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
302				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
303			clocks = <&cpg CPG_MOD 301>;
304			clock-names = "fck";
305			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
306			resets = <&cpg 301>;
307			status = "disabled";
308		};
309
310		cmt3: timer@e6148000 {
311			compatible = "renesas,r8a774c0-cmt1",
312				     "renesas,rcar-gen3-cmt1";
313			reg = <0 0xe6148000 0 0x1004>;
314			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
315				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
316				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
317				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
318				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
319				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
320				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
321				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
322			clocks = <&cpg CPG_MOD 300>;
323			clock-names = "fck";
324			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
325			resets = <&cpg 300>;
326			status = "disabled";
327		};
328
329		cpg: clock-controller@e6150000 {
330			compatible = "renesas,r8a774c0-cpg-mssr";
331			reg = <0 0xe6150000 0 0x1000>;
332			clocks = <&extal_clk>;
333			clock-names = "extal";
334			#clock-cells = <2>;
335			#power-domain-cells = <0>;
336			#reset-cells = <1>;
337		};
338
339		rst: reset-controller@e6160000 {
340			compatible = "renesas,r8a774c0-rst";
341			reg = <0 0xe6160000 0 0x0200>;
342		};
343
344		sysc: system-controller@e6180000 {
345			compatible = "renesas,r8a774c0-sysc";
346			reg = <0 0xe6180000 0 0x0400>;
347			#power-domain-cells = <1>;
348		};
349
350		thermal: thermal@e6190000 {
351			compatible = "renesas,thermal-r8a774c0";
352			reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
353			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
354				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
355				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&cpg CPG_MOD 522>;
357			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
358			resets = <&cpg 522>;
359			#thermal-sensor-cells = <0>;
360		};
361
362		intc_ex: interrupt-controller@e61c0000 {
363			compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
364			#interrupt-cells = <2>;
365			interrupt-controller;
366			reg = <0 0xe61c0000 0 0x200>;
367			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
368				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
369				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
370				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
371				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
372				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
373			clocks = <&cpg CPG_MOD 407>;
374			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
375			resets = <&cpg 407>;
376		};
377
378		tmu0: timer@e61e0000 {
379			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
380			reg = <0 0xe61e0000 0 0x30>;
381			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
382				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
383				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
384			clocks = <&cpg CPG_MOD 125>;
385			clock-names = "fck";
386			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
387			resets = <&cpg 125>;
388			status = "disabled";
389		};
390
391		tmu1: timer@e6fc0000 {
392			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
393			reg = <0 0xe6fc0000 0 0x30>;
394			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
395				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
396				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
397			clocks = <&cpg CPG_MOD 124>;
398			clock-names = "fck";
399			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
400			resets = <&cpg 124>;
401			status = "disabled";
402		};
403
404		tmu2: timer@e6fd0000 {
405			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
406			reg = <0 0xe6fd0000 0 0x30>;
407			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
408				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
409				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
410			clocks = <&cpg CPG_MOD 123>;
411			clock-names = "fck";
412			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
413			resets = <&cpg 123>;
414			status = "disabled";
415		};
416
417		tmu3: timer@e6fe0000 {
418			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
419			reg = <0 0xe6fe0000 0 0x30>;
420			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
421				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
422				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
423			clocks = <&cpg CPG_MOD 122>;
424			clock-names = "fck";
425			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
426			resets = <&cpg 122>;
427			status = "disabled";
428		};
429
430		tmu4: timer@ffc00000 {
431			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
432			reg = <0 0xffc00000 0 0x30>;
433			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
434				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
435				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
436			clocks = <&cpg CPG_MOD 121>;
437			clock-names = "fck";
438			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
439			resets = <&cpg 121>;
440			status = "disabled";
441		};
442
443		i2c0: i2c@e6500000 {
444			#address-cells = <1>;
445			#size-cells = <0>;
446			compatible = "renesas,i2c-r8a774c0",
447				     "renesas,rcar-gen3-i2c";
448			reg = <0 0xe6500000 0 0x40>;
449			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
450			clocks = <&cpg CPG_MOD 931>;
451			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
452			resets = <&cpg 931>;
453			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
454			       <&dmac2 0x91>, <&dmac2 0x90>;
455			dma-names = "tx", "rx", "tx", "rx";
456			i2c-scl-internal-delay-ns = <110>;
457			status = "disabled";
458		};
459
460		i2c1: i2c@e6508000 {
461			#address-cells = <1>;
462			#size-cells = <0>;
463			compatible = "renesas,i2c-r8a774c0",
464				     "renesas,rcar-gen3-i2c";
465			reg = <0 0xe6508000 0 0x40>;
466			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
467			clocks = <&cpg CPG_MOD 930>;
468			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
469			resets = <&cpg 930>;
470			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
471			       <&dmac2 0x93>, <&dmac2 0x92>;
472			dma-names = "tx", "rx", "tx", "rx";
473			i2c-scl-internal-delay-ns = <6>;
474			status = "disabled";
475		};
476
477		i2c2: i2c@e6510000 {
478			#address-cells = <1>;
479			#size-cells = <0>;
480			compatible = "renesas,i2c-r8a774c0",
481				     "renesas,rcar-gen3-i2c";
482			reg = <0 0xe6510000 0 0x40>;
483			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
484			clocks = <&cpg CPG_MOD 929>;
485			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
486			resets = <&cpg 929>;
487			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
488			       <&dmac2 0x95>, <&dmac2 0x94>;
489			dma-names = "tx", "rx", "tx", "rx";
490			i2c-scl-internal-delay-ns = <6>;
491			status = "disabled";
492		};
493
494		i2c3: i2c@e66d0000 {
495			#address-cells = <1>;
496			#size-cells = <0>;
497			compatible = "renesas,i2c-r8a774c0",
498				     "renesas,rcar-gen3-i2c";
499			reg = <0 0xe66d0000 0 0x40>;
500			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
501			clocks = <&cpg CPG_MOD 928>;
502			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
503			resets = <&cpg 928>;
504			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
505			dma-names = "tx", "rx";
506			i2c-scl-internal-delay-ns = <110>;
507			status = "disabled";
508		};
509
510		i2c4: i2c@e66d8000 {
511			#address-cells = <1>;
512			#size-cells = <0>;
513			compatible = "renesas,i2c-r8a774c0",
514				     "renesas,rcar-gen3-i2c";
515			reg = <0 0xe66d8000 0 0x40>;
516			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
517			clocks = <&cpg CPG_MOD 927>;
518			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
519			resets = <&cpg 927>;
520			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
521			dma-names = "tx", "rx";
522			i2c-scl-internal-delay-ns = <6>;
523			status = "disabled";
524		};
525
526		i2c5: i2c@e66e0000 {
527			#address-cells = <1>;
528			#size-cells = <0>;
529			compatible = "renesas,i2c-r8a774c0",
530				     "renesas,rcar-gen3-i2c";
531			reg = <0 0xe66e0000 0 0x40>;
532			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
533			clocks = <&cpg CPG_MOD 919>;
534			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
535			resets = <&cpg 919>;
536			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
537			dma-names = "tx", "rx";
538			i2c-scl-internal-delay-ns = <6>;
539			status = "disabled";
540		};
541
542		i2c6: i2c@e66e8000 {
543			#address-cells = <1>;
544			#size-cells = <0>;
545			compatible = "renesas,i2c-r8a774c0",
546				     "renesas,rcar-gen3-i2c";
547			reg = <0 0xe66e8000 0 0x40>;
548			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
549			clocks = <&cpg CPG_MOD 918>;
550			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
551			resets = <&cpg 918>;
552			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
553			dma-names = "tx", "rx";
554			i2c-scl-internal-delay-ns = <6>;
555			status = "disabled";
556		};
557
558		i2c7: i2c@e6690000 {
559			#address-cells = <1>;
560			#size-cells = <0>;
561			compatible = "renesas,i2c-r8a774c0",
562				     "renesas,rcar-gen3-i2c";
563			reg = <0 0xe6690000 0 0x40>;
564			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
565			clocks = <&cpg CPG_MOD 1003>;
566			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
567			resets = <&cpg 1003>;
568			i2c-scl-internal-delay-ns = <6>;
569			status = "disabled";
570		};
571
572		i2c_dvfs: i2c@e60b0000 {
573			#address-cells = <1>;
574			#size-cells = <0>;
575			compatible = "renesas,iic-r8a774c0";
576			reg = <0 0xe60b0000 0 0x15>;
577			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
578			clocks = <&cpg CPG_MOD 926>;
579			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
580			resets = <&cpg 926>;
581			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
582			dma-names = "tx", "rx";
583			status = "disabled";
584		};
585
586		hscif0: serial@e6540000 {
587			compatible = "renesas,hscif-r8a774c0",
588				     "renesas,rcar-gen3-hscif",
589				     "renesas,hscif";
590			reg = <0 0xe6540000 0 0x60>;
591			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
592			clocks = <&cpg CPG_MOD 520>,
593				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
594				 <&scif_clk>;
595			clock-names = "fck", "brg_int", "scif_clk";
596			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
597			       <&dmac2 0x31>, <&dmac2 0x30>;
598			dma-names = "tx", "rx", "tx", "rx";
599			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
600			resets = <&cpg 520>;
601			status = "disabled";
602		};
603
604		hscif1: serial@e6550000 {
605			compatible = "renesas,hscif-r8a774c0",
606				     "renesas,rcar-gen3-hscif",
607				     "renesas,hscif";
608			reg = <0 0xe6550000 0 0x60>;
609			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
610			clocks = <&cpg CPG_MOD 519>,
611				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
612				 <&scif_clk>;
613			clock-names = "fck", "brg_int", "scif_clk";
614			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
615			       <&dmac2 0x33>, <&dmac2 0x32>;
616			dma-names = "tx", "rx", "tx", "rx";
617			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
618			resets = <&cpg 519>;
619			status = "disabled";
620		};
621
622		hscif2: serial@e6560000 {
623			compatible = "renesas,hscif-r8a774c0",
624				     "renesas,rcar-gen3-hscif",
625				     "renesas,hscif";
626			reg = <0 0xe6560000 0 0x60>;
627			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
628			clocks = <&cpg CPG_MOD 518>,
629				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
630				 <&scif_clk>;
631			clock-names = "fck", "brg_int", "scif_clk";
632			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
633			       <&dmac2 0x35>, <&dmac2 0x34>;
634			dma-names = "tx", "rx", "tx", "rx";
635			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
636			resets = <&cpg 518>;
637			status = "disabled";
638		};
639
640		hscif3: serial@e66a0000 {
641			compatible = "renesas,hscif-r8a774c0",
642				     "renesas,rcar-gen3-hscif",
643				     "renesas,hscif";
644			reg = <0 0xe66a0000 0 0x60>;
645			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
646			clocks = <&cpg CPG_MOD 517>,
647				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
648				 <&scif_clk>;
649			clock-names = "fck", "brg_int", "scif_clk";
650			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
651			dma-names = "tx", "rx";
652			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
653			resets = <&cpg 517>;
654			status = "disabled";
655		};
656
657		hscif4: serial@e66b0000 {
658			compatible = "renesas,hscif-r8a774c0",
659				     "renesas,rcar-gen3-hscif",
660				     "renesas,hscif";
661			reg = <0 0xe66b0000 0 0x60>;
662			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
663			clocks = <&cpg CPG_MOD 516>,
664				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
665				 <&scif_clk>;
666			clock-names = "fck", "brg_int", "scif_clk";
667			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
668			dma-names = "tx", "rx";
669			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
670			resets = <&cpg 516>;
671			status = "disabled";
672		};
673
674		hsusb: usb@e6590000 {
675			compatible = "renesas,usbhs-r8a774c0",
676				     "renesas,rcar-gen3-usbhs";
677			reg = <0 0xe6590000 0 0x200>;
678			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
679			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
680			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
681			       <&usb_dmac1 0>, <&usb_dmac1 1>;
682			dma-names = "ch0", "ch1", "ch2", "ch3";
683			renesas,buswait = <11>;
684			phys = <&usb2_phy0 3>;
685			phy-names = "usb";
686			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
687			resets = <&cpg 704>, <&cpg 703>;
688			status = "disabled";
689		};
690
691		usb_dmac0: dma-controller@e65a0000 {
692			compatible = "renesas,r8a774c0-usb-dmac",
693				     "renesas,usb-dmac";
694			reg = <0 0xe65a0000 0 0x100>;
695			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
696				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
697			interrupt-names = "ch0", "ch1";
698			clocks = <&cpg CPG_MOD 330>;
699			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
700			resets = <&cpg 330>;
701			#dma-cells = <1>;
702			dma-channels = <2>;
703		};
704
705		usb_dmac1: dma-controller@e65b0000 {
706			compatible = "renesas,r8a774c0-usb-dmac",
707				     "renesas,usb-dmac";
708			reg = <0 0xe65b0000 0 0x100>;
709			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
710				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
711			interrupt-names = "ch0", "ch1";
712			clocks = <&cpg CPG_MOD 331>;
713			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
714			resets = <&cpg 331>;
715			#dma-cells = <1>;
716			dma-channels = <2>;
717		};
718
719		dmac0: dma-controller@e6700000 {
720			compatible = "renesas,dmac-r8a774c0",
721				     "renesas,rcar-dmac";
722			reg = <0 0xe6700000 0 0x10000>;
723			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
724				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
725				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
726				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
727				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
728				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
729				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
730				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
731				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
732				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
733				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
734				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
735				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
736				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
737				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
738				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
739				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
740			interrupt-names = "error",
741					"ch0", "ch1", "ch2", "ch3",
742					"ch4", "ch5", "ch6", "ch7",
743					"ch8", "ch9", "ch10", "ch11",
744					"ch12", "ch13", "ch14", "ch15";
745			clocks = <&cpg CPG_MOD 219>;
746			clock-names = "fck";
747			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
748			resets = <&cpg 219>;
749			#dma-cells = <1>;
750			dma-channels = <16>;
751			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
752			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
753			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
754			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
755			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
756			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
757			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
758			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
759		};
760
761		dmac1: dma-controller@e7300000 {
762			compatible = "renesas,dmac-r8a774c0",
763				     "renesas,rcar-dmac";
764			reg = <0 0xe7300000 0 0x10000>;
765			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
766				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
767				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
768				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
769				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
770				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
771				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
772				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
773				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
774				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
775				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
776				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
777				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
778				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
779				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
780				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
781				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
782			interrupt-names = "error",
783					"ch0", "ch1", "ch2", "ch3",
784					"ch4", "ch5", "ch6", "ch7",
785					"ch8", "ch9", "ch10", "ch11",
786					"ch12", "ch13", "ch14", "ch15";
787			clocks = <&cpg CPG_MOD 218>;
788			clock-names = "fck";
789			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
790			resets = <&cpg 218>;
791			#dma-cells = <1>;
792			dma-channels = <16>;
793			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
794			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
795			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
796			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
797			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
798			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
799			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
800			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
801		};
802
803		dmac2: dma-controller@e7310000 {
804			compatible = "renesas,dmac-r8a774c0",
805				     "renesas,rcar-dmac";
806			reg = <0 0xe7310000 0 0x10000>;
807			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
808				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
809				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
810				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
811				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
812				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
813				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
814				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
815				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
816				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
817				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
818				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
819				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
820				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
821				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
822				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
823				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
824			interrupt-names = "error",
825					"ch0", "ch1", "ch2", "ch3",
826					"ch4", "ch5", "ch6", "ch7",
827					"ch8", "ch9", "ch10", "ch11",
828					"ch12", "ch13", "ch14", "ch15";
829			clocks = <&cpg CPG_MOD 217>;
830			clock-names = "fck";
831			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
832			resets = <&cpg 217>;
833			#dma-cells = <1>;
834			dma-channels = <16>;
835			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
836			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
837			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
838			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
839			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
840			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
841			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
842			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
843		};
844
845		ipmmu_ds0: mmu@e6740000 {
846			compatible = "renesas,ipmmu-r8a774c0";
847			reg = <0 0xe6740000 0 0x1000>;
848			renesas,ipmmu-main = <&ipmmu_mm 0>;
849			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
850			#iommu-cells = <1>;
851		};
852
853		ipmmu_ds1: mmu@e7740000 {
854			compatible = "renesas,ipmmu-r8a774c0";
855			reg = <0 0xe7740000 0 0x1000>;
856			renesas,ipmmu-main = <&ipmmu_mm 1>;
857			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
858			#iommu-cells = <1>;
859		};
860
861		ipmmu_hc: mmu@e6570000 {
862			compatible = "renesas,ipmmu-r8a774c0";
863			reg = <0 0xe6570000 0 0x1000>;
864			renesas,ipmmu-main = <&ipmmu_mm 2>;
865			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
866			#iommu-cells = <1>;
867		};
868
869		ipmmu_mm: mmu@e67b0000 {
870			compatible = "renesas,ipmmu-r8a774c0";
871			reg = <0 0xe67b0000 0 0x1000>;
872			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
873				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
874			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
875			#iommu-cells = <1>;
876		};
877
878		ipmmu_mp: mmu@ec670000 {
879			compatible = "renesas,ipmmu-r8a774c0";
880			reg = <0 0xec670000 0 0x1000>;
881			renesas,ipmmu-main = <&ipmmu_mm 4>;
882			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
883			#iommu-cells = <1>;
884		};
885
886		ipmmu_pv0: mmu@fd800000 {
887			compatible = "renesas,ipmmu-r8a774c0";
888			reg = <0 0xfd800000 0 0x1000>;
889			renesas,ipmmu-main = <&ipmmu_mm 6>;
890			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
891			#iommu-cells = <1>;
892		};
893
894		ipmmu_vc0: mmu@fe6b0000 {
895			compatible = "renesas,ipmmu-r8a774c0";
896			reg = <0 0xfe6b0000 0 0x1000>;
897			renesas,ipmmu-main = <&ipmmu_mm 12>;
898			power-domains = <&sysc R8A774C0_PD_A3VC>;
899			#iommu-cells = <1>;
900		};
901
902		ipmmu_vi0: mmu@febd0000 {
903			compatible = "renesas,ipmmu-r8a774c0";
904			reg = <0 0xfebd0000 0 0x1000>;
905			renesas,ipmmu-main = <&ipmmu_mm 14>;
906			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
907			#iommu-cells = <1>;
908		};
909
910		ipmmu_vp0: mmu@fe990000 {
911			compatible = "renesas,ipmmu-r8a774c0";
912			reg = <0 0xfe990000 0 0x1000>;
913			renesas,ipmmu-main = <&ipmmu_mm 16>;
914			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
915			#iommu-cells = <1>;
916		};
917
918		avb: ethernet@e6800000 {
919			compatible = "renesas,etheravb-r8a774c0",
920				     "renesas,etheravb-rcar-gen3";
921			reg = <0 0xe6800000 0 0x800>;
922			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
923				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
924				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
925				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
926				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
927				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
928				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
929				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
930				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
931				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
932				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
933				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
934				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
935				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
936				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
937				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
938				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
939				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
940				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
941				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
942				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
943				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
944				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
945				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
946				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
947			interrupt-names = "ch0", "ch1", "ch2", "ch3",
948					  "ch4", "ch5", "ch6", "ch7",
949					  "ch8", "ch9", "ch10", "ch11",
950					  "ch12", "ch13", "ch14", "ch15",
951					  "ch16", "ch17", "ch18", "ch19",
952					  "ch20", "ch21", "ch22", "ch23",
953					  "ch24";
954			clocks = <&cpg CPG_MOD 812>;
955			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
956			resets = <&cpg 812>;
957			phy-mode = "rgmii";
958			iommus = <&ipmmu_ds0 16>;
959			#address-cells = <1>;
960			#size-cells = <0>;
961			status = "disabled";
962		};
963
964		can0: can@e6c30000 {
965			compatible = "renesas,can-r8a774c0",
966				     "renesas,rcar-gen3-can";
967			reg = <0 0xe6c30000 0 0x1000>;
968			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
969			clocks = <&cpg CPG_MOD 916>,
970				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
971				 <&can_clk>;
972			clock-names = "clkp1", "clkp2", "can_clk";
973			assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
974			assigned-clock-rates = <40000000>;
975			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
976			resets = <&cpg 916>;
977			status = "disabled";
978		};
979
980		can1: can@e6c38000 {
981			compatible = "renesas,can-r8a774c0",
982				     "renesas,rcar-gen3-can";
983			reg = <0 0xe6c38000 0 0x1000>;
984			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
985			clocks = <&cpg CPG_MOD 915>,
986				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
987				 <&can_clk>;
988			clock-names = "clkp1", "clkp2", "can_clk";
989			assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
990			assigned-clock-rates = <40000000>;
991			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
992			resets = <&cpg 915>;
993			status = "disabled";
994		};
995
996		canfd: can@e66c0000 {
997			compatible = "renesas,r8a774c0-canfd",
998				     "renesas,rcar-gen3-canfd";
999			reg = <0 0xe66c0000 0 0x8000>;
1000			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1001				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1002			clocks = <&cpg CPG_MOD 914>,
1003				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1004				 <&can_clk>;
1005			clock-names = "fck", "canfd", "can_clk";
1006			assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1007			assigned-clock-rates = <40000000>;
1008			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1009			resets = <&cpg 914>;
1010			status = "disabled";
1011
1012			channel0 {
1013				status = "disabled";
1014			};
1015
1016			channel1 {
1017				status = "disabled";
1018			};
1019		};
1020
1021		pwm0: pwm@e6e30000 {
1022			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1023			reg = <0 0xe6e30000 0 0x8>;
1024			clocks = <&cpg CPG_MOD 523>;
1025			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1026			resets = <&cpg 523>;
1027			#pwm-cells = <2>;
1028			status = "disabled";
1029		};
1030
1031		pwm1: pwm@e6e31000 {
1032			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1033			reg = <0 0xe6e31000 0 0x8>;
1034			clocks = <&cpg CPG_MOD 523>;
1035			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1036			resets = <&cpg 523>;
1037			#pwm-cells = <2>;
1038			status = "disabled";
1039		};
1040
1041		pwm2: pwm@e6e32000 {
1042			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1043			reg = <0 0xe6e32000 0 0x8>;
1044			clocks = <&cpg CPG_MOD 523>;
1045			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1046			resets = <&cpg 523>;
1047			#pwm-cells = <2>;
1048			status = "disabled";
1049		};
1050
1051		pwm3: pwm@e6e33000 {
1052			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1053			reg = <0 0xe6e33000 0 0x8>;
1054			clocks = <&cpg CPG_MOD 523>;
1055			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1056			resets = <&cpg 523>;
1057			#pwm-cells = <2>;
1058			status = "disabled";
1059		};
1060
1061		pwm4: pwm@e6e34000 {
1062			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1063			reg = <0 0xe6e34000 0 0x8>;
1064			clocks = <&cpg CPG_MOD 523>;
1065			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1066			resets = <&cpg 523>;
1067			#pwm-cells = <2>;
1068			status = "disabled";
1069		};
1070
1071		pwm5: pwm@e6e35000 {
1072			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1073			reg = <0 0xe6e35000 0 0x8>;
1074			clocks = <&cpg CPG_MOD 523>;
1075			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1076			resets = <&cpg 523>;
1077			#pwm-cells = <2>;
1078			status = "disabled";
1079		};
1080
1081		pwm6: pwm@e6e36000 {
1082			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1083			reg = <0 0xe6e36000 0 0x8>;
1084			clocks = <&cpg CPG_MOD 523>;
1085			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1086			resets = <&cpg 523>;
1087			#pwm-cells = <2>;
1088			status = "disabled";
1089		};
1090
1091		scif0: serial@e6e60000 {
1092			compatible = "renesas,scif-r8a774c0",
1093				     "renesas,rcar-gen3-scif", "renesas,scif";
1094			reg = <0 0xe6e60000 0 64>;
1095			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1096			clocks = <&cpg CPG_MOD 207>,
1097				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1098				 <&scif_clk>;
1099			clock-names = "fck", "brg_int", "scif_clk";
1100			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1101			       <&dmac2 0x51>, <&dmac2 0x50>;
1102			dma-names = "tx", "rx", "tx", "rx";
1103			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1104			resets = <&cpg 207>;
1105			status = "disabled";
1106		};
1107
1108		scif1: serial@e6e68000 {
1109			compatible = "renesas,scif-r8a774c0",
1110				     "renesas,rcar-gen3-scif", "renesas,scif";
1111			reg = <0 0xe6e68000 0 64>;
1112			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1113			clocks = <&cpg CPG_MOD 206>,
1114				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1115				 <&scif_clk>;
1116			clock-names = "fck", "brg_int", "scif_clk";
1117			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1118			       <&dmac2 0x53>, <&dmac2 0x52>;
1119			dma-names = "tx", "rx", "tx", "rx";
1120			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1121			resets = <&cpg 206>;
1122			status = "disabled";
1123		};
1124
1125		scif2: serial@e6e88000 {
1126			compatible = "renesas,scif-r8a774c0",
1127				     "renesas,rcar-gen3-scif", "renesas,scif";
1128			reg = <0 0xe6e88000 0 64>;
1129			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1130			clocks = <&cpg CPG_MOD 310>,
1131				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1132				 <&scif_clk>;
1133			clock-names = "fck", "brg_int", "scif_clk";
1134			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1135			       <&dmac2 0x13>, <&dmac2 0x12>;
1136			dma-names = "tx", "rx", "tx", "rx";
1137			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1138			resets = <&cpg 310>;
1139			status = "disabled";
1140		};
1141
1142		scif3: serial@e6c50000 {
1143			compatible = "renesas,scif-r8a774c0",
1144				     "renesas,rcar-gen3-scif", "renesas,scif";
1145			reg = <0 0xe6c50000 0 64>;
1146			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1147			clocks = <&cpg CPG_MOD 204>,
1148				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1149				 <&scif_clk>;
1150			clock-names = "fck", "brg_int", "scif_clk";
1151			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1152			dma-names = "tx", "rx";
1153			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1154			resets = <&cpg 204>;
1155			status = "disabled";
1156		};
1157
1158		scif4: serial@e6c40000 {
1159			compatible = "renesas,scif-r8a774c0",
1160				     "renesas,rcar-gen3-scif", "renesas,scif";
1161			reg = <0 0xe6c40000 0 64>;
1162			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1163			clocks = <&cpg CPG_MOD 203>,
1164				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1165				 <&scif_clk>;
1166			clock-names = "fck", "brg_int", "scif_clk";
1167			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1168			dma-names = "tx", "rx";
1169			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1170			resets = <&cpg 203>;
1171			status = "disabled";
1172		};
1173
1174		scif5: serial@e6f30000 {
1175			compatible = "renesas,scif-r8a774c0",
1176				     "renesas,rcar-gen3-scif", "renesas,scif";
1177			reg = <0 0xe6f30000 0 64>;
1178			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1179			clocks = <&cpg CPG_MOD 202>,
1180				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1181				 <&scif_clk>;
1182			clock-names = "fck", "brg_int", "scif_clk";
1183			dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1184			dma-names = "tx", "rx";
1185			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1186			resets = <&cpg 202>;
1187			status = "disabled";
1188		};
1189
1190		msiof0: spi@e6e90000 {
1191			compatible = "renesas,msiof-r8a774c0",
1192				     "renesas,rcar-gen3-msiof";
1193			reg = <0 0xe6e90000 0 0x0064>;
1194			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1195			clocks = <&cpg CPG_MOD 211>;
1196			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1197			       <&dmac2 0x41>, <&dmac2 0x40>;
1198			dma-names = "tx", "rx", "tx", "rx";
1199			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1200			resets = <&cpg 211>;
1201			#address-cells = <1>;
1202			#size-cells = <0>;
1203			status = "disabled";
1204		};
1205
1206		msiof1: spi@e6ea0000 {
1207			compatible = "renesas,msiof-r8a774c0",
1208				     "renesas,rcar-gen3-msiof";
1209			reg = <0 0xe6ea0000 0 0x0064>;
1210			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1211			clocks = <&cpg CPG_MOD 210>;
1212			dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1213			dma-names = "tx", "rx";
1214			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215			resets = <&cpg 210>;
1216			#address-cells = <1>;
1217			#size-cells = <0>;
1218			status = "disabled";
1219		};
1220
1221		msiof2: spi@e6c00000 {
1222			compatible = "renesas,msiof-r8a774c0",
1223				     "renesas,rcar-gen3-msiof";
1224			reg = <0 0xe6c00000 0 0x0064>;
1225			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1226			clocks = <&cpg CPG_MOD 209>;
1227			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1228			dma-names = "tx", "rx";
1229			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230			resets = <&cpg 209>;
1231			#address-cells = <1>;
1232			#size-cells = <0>;
1233			status = "disabled";
1234		};
1235
1236		msiof3: spi@e6c10000 {
1237			compatible = "renesas,msiof-r8a774c0",
1238				     "renesas,rcar-gen3-msiof";
1239			reg = <0 0xe6c10000 0 0x0064>;
1240			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1241			clocks = <&cpg CPG_MOD 208>;
1242			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1243			dma-names = "tx", "rx";
1244			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245			resets = <&cpg 208>;
1246			#address-cells = <1>;
1247			#size-cells = <0>;
1248			status = "disabled";
1249		};
1250
1251		vin4: video@e6ef4000 {
1252			compatible = "renesas,vin-r8a774c0";
1253			reg = <0 0xe6ef4000 0 0x1000>;
1254			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1255			clocks = <&cpg CPG_MOD 807>;
1256			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1257			resets = <&cpg 807>;
1258			renesas,id = <4>;
1259			status = "disabled";
1260
1261			ports {
1262				#address-cells = <1>;
1263				#size-cells = <0>;
1264
1265				port@1 {
1266					#address-cells = <1>;
1267					#size-cells = <0>;
1268
1269					reg = <1>;
1270
1271					vin4csi40: endpoint@2 {
1272						reg = <2>;
1273						remote-endpoint= <&csi40vin4>;
1274					};
1275				};
1276			};
1277		};
1278
1279		vin5: video@e6ef5000 {
1280			compatible = "renesas,vin-r8a774c0";
1281			reg = <0 0xe6ef5000 0 0x1000>;
1282			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1283			clocks = <&cpg CPG_MOD 806>;
1284			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1285			resets = <&cpg 806>;
1286			renesas,id = <5>;
1287			status = "disabled";
1288
1289			ports {
1290				#address-cells = <1>;
1291				#size-cells = <0>;
1292
1293				port@1 {
1294					#address-cells = <1>;
1295					#size-cells = <0>;
1296
1297					reg = <1>;
1298
1299					vin5csi40: endpoint@2 {
1300						reg = <2>;
1301						remote-endpoint= <&csi40vin5>;
1302					};
1303				};
1304			};
1305		};
1306
1307		rcar_sound: sound@ec500000 {
1308			/*
1309			 * #sound-dai-cells is required
1310			 *
1311			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
1312			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
1313			 */
1314			/*
1315			 * #clock-cells is required for audio_clkout0/1/2/3
1316			 *
1317			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
1318			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
1319			 */
1320			compatible = "renesas,rcar_sound-r8a774c0",
1321				     "renesas,rcar_sound-gen3";
1322			reg =	<0 0xec500000 0 0x1000>, /* SCU */
1323				<0 0xec5a0000 0 0x100>,  /* ADG */
1324				<0 0xec540000 0 0x1000>, /* SSIU */
1325				<0 0xec541000 0 0x280>,  /* SSI */
1326				<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
1327			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1328
1329			clocks = <&cpg CPG_MOD 1005>,
1330				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1331				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1332				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1333				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1334				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1335				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1336				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1337				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1338				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1339				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1340				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1341				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1342				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1343				 <&audio_clk_a>, <&audio_clk_b>,
1344				 <&audio_clk_c>,
1345				 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1346			clock-names = "ssi-all",
1347				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1348				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1349				      "ssi.1", "ssi.0",
1350				      "src.9", "src.8", "src.7", "src.6",
1351				      "src.5", "src.4", "src.3", "src.2",
1352				      "src.1", "src.0",
1353				      "mix.1", "mix.0",
1354				      "ctu.1", "ctu.0",
1355				      "dvc.0", "dvc.1",
1356				      "clk_a", "clk_b", "clk_c", "clk_i";
1357			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1358			resets = <&cpg 1005>,
1359				 <&cpg 1006>, <&cpg 1007>,
1360				 <&cpg 1008>, <&cpg 1009>,
1361				 <&cpg 1010>, <&cpg 1011>,
1362				 <&cpg 1012>, <&cpg 1013>,
1363				 <&cpg 1014>, <&cpg 1015>;
1364			reset-names = "ssi-all",
1365				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1366				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1367				      "ssi.1", "ssi.0";
1368			status = "disabled";
1369
1370			rcar_sound,ctu {
1371				ctu00: ctu-0 { };
1372				ctu01: ctu-1 { };
1373				ctu02: ctu-2 { };
1374				ctu03: ctu-3 { };
1375				ctu10: ctu-4 { };
1376				ctu11: ctu-5 { };
1377				ctu12: ctu-6 { };
1378				ctu13: ctu-7 { };
1379			};
1380
1381			rcar_sound,dvc {
1382				dvc0: dvc-0 {
1383					dmas = <&audma0 0xbc>;
1384					dma-names = "tx";
1385				};
1386				dvc1: dvc-1 {
1387					dmas = <&audma0 0xbe>;
1388					dma-names = "tx";
1389				};
1390			};
1391
1392			rcar_sound,mix {
1393				mix0: mix-0 { };
1394				mix1: mix-1 { };
1395			};
1396
1397			rcar_sound,src {
1398				src0: src-0 {
1399					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1400					dmas = <&audma0 0x85>, <&audma0 0x9a>;
1401					dma-names = "rx", "tx";
1402				};
1403				src1: src-1 {
1404					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1405					dmas = <&audma0 0x87>, <&audma0 0x9c>;
1406					dma-names = "rx", "tx";
1407				};
1408				src2: src-2 {
1409					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1410					dmas = <&audma0 0x89>, <&audma0 0x9e>;
1411					dma-names = "rx", "tx";
1412				};
1413				src3: src-3 {
1414					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1415					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1416					dma-names = "rx", "tx";
1417				};
1418				src4: src-4 {
1419					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1420					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1421					dma-names = "rx", "tx";
1422				};
1423				src5: src-5 {
1424					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1425					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1426					dma-names = "rx", "tx";
1427				};
1428				src6: src-6 {
1429					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1430					dmas = <&audma0 0x91>, <&audma0 0xb4>;
1431					dma-names = "rx", "tx";
1432				};
1433				src7: src-7 {
1434					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1435					dmas = <&audma0 0x93>, <&audma0 0xb6>;
1436					dma-names = "rx", "tx";
1437				};
1438				src8: src-8 {
1439					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1440					dmas = <&audma0 0x95>, <&audma0 0xb8>;
1441					dma-names = "rx", "tx";
1442				};
1443				src9: src-9 {
1444					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1445					dmas = <&audma0 0x97>, <&audma0 0xba>;
1446					dma-names = "rx", "tx";
1447				};
1448			};
1449
1450			rcar_sound,ssi {
1451				ssi0: ssi-0 {
1452					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1453					dmas = <&audma0 0x01>, <&audma0 0x02>,
1454					       <&audma0 0x15>, <&audma0 0x16>;
1455					dma-names = "rx", "tx", "rxu", "txu";
1456				};
1457				ssi1: ssi-1 {
1458					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1459					dmas = <&audma0 0x03>, <&audma0 0x04>,
1460					       <&audma0 0x49>, <&audma0 0x4a>;
1461					dma-names = "rx", "tx", "rxu", "txu";
1462				};
1463				ssi2: ssi-2 {
1464					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1465					dmas = <&audma0 0x05>, <&audma0 0x06>,
1466					       <&audma0 0x63>, <&audma0 0x64>;
1467					dma-names = "rx", "tx", "rxu", "txu";
1468				};
1469				ssi3: ssi-3 {
1470					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1471					dmas = <&audma0 0x07>, <&audma0 0x08>,
1472					       <&audma0 0x6f>, <&audma0 0x70>;
1473					dma-names = "rx", "tx", "rxu", "txu";
1474				};
1475				ssi4: ssi-4 {
1476					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1477					dmas = <&audma0 0x09>, <&audma0 0x0a>,
1478					       <&audma0 0x71>, <&audma0 0x72>;
1479					dma-names = "rx", "tx", "rxu", "txu";
1480				};
1481				ssi5: ssi-5 {
1482					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1483					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1484					       <&audma0 0x73>, <&audma0 0x74>;
1485					dma-names = "rx", "tx", "rxu", "txu";
1486				};
1487				ssi6: ssi-6 {
1488					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1489					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1490					       <&audma0 0x75>, <&audma0 0x76>;
1491					dma-names = "rx", "tx", "rxu", "txu";
1492				};
1493				ssi7: ssi-7 {
1494					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1495					dmas = <&audma0 0x0f>, <&audma0 0x10>,
1496					       <&audma0 0x79>, <&audma0 0x7a>;
1497					dma-names = "rx", "tx", "rxu", "txu";
1498				};
1499				ssi8: ssi-8 {
1500					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1501					dmas = <&audma0 0x11>, <&audma0 0x12>,
1502					       <&audma0 0x7b>, <&audma0 0x7c>;
1503					dma-names = "rx", "tx", "rxu", "txu";
1504				};
1505				ssi9: ssi-9 {
1506					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1507					dmas = <&audma0 0x13>, <&audma0 0x14>,
1508					       <&audma0 0x7d>, <&audma0 0x7e>;
1509					dma-names = "rx", "tx", "rxu", "txu";
1510				};
1511			};
1512		};
1513
1514		audma0: dma-controller@ec700000 {
1515			compatible = "renesas,dmac-r8a774c0",
1516				     "renesas,rcar-dmac";
1517			reg = <0 0xec700000 0 0x10000>;
1518			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1519				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1520				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1521				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1522				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1523				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1524				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1525				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1526				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1527				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1528				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1529				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1530				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1531				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1532				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1533				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1534				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1535			interrupt-names = "error",
1536					"ch0", "ch1", "ch2", "ch3",
1537					"ch4", "ch5", "ch6", "ch7",
1538					"ch8", "ch9", "ch10", "ch11",
1539					"ch12", "ch13", "ch14", "ch15";
1540			clocks = <&cpg CPG_MOD 502>;
1541			clock-names = "fck";
1542			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1543			resets = <&cpg 502>;
1544			#dma-cells = <1>;
1545			dma-channels = <16>;
1546			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1547				 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1548				 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1549				 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1550				 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1551				 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1552				 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1553				 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1554		};
1555
1556		xhci0: usb@ee000000 {
1557			compatible = "renesas,xhci-r8a774c0",
1558				     "renesas,rcar-gen3-xhci";
1559			reg = <0 0xee000000 0 0xc00>;
1560			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1561			clocks = <&cpg CPG_MOD 328>;
1562			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1563			resets = <&cpg 328>;
1564			status = "disabled";
1565		};
1566
1567		usb3_peri0: usb@ee020000 {
1568			compatible = "renesas,r8a774c0-usb3-peri",
1569				     "renesas,rcar-gen3-usb3-peri";
1570			reg = <0 0xee020000 0 0x400>;
1571			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1572			clocks = <&cpg CPG_MOD 328>;
1573			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1574			resets = <&cpg 328>;
1575			status = "disabled";
1576		};
1577
1578		ohci0: usb@ee080000 {
1579			compatible = "generic-ohci";
1580			reg = <0 0xee080000 0 0x100>;
1581			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1582			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1583			phys = <&usb2_phy0 1>;
1584			phy-names = "usb";
1585			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1586			resets = <&cpg 703>, <&cpg 704>;
1587			status = "disabled";
1588		};
1589
1590		ehci0: usb@ee080100 {
1591			compatible = "generic-ehci";
1592			reg = <0 0xee080100 0 0x100>;
1593			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1594			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1595			phys = <&usb2_phy0 2>;
1596			phy-names = "usb";
1597			companion = <&ohci0>;
1598			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1599			resets = <&cpg 703>, <&cpg 704>;
1600			status = "disabled";
1601		};
1602
1603		usb2_phy0: usb-phy@ee080200 {
1604			compatible = "renesas,usb2-phy-r8a774c0",
1605				     "renesas,rcar-gen3-usb2-phy";
1606			reg = <0 0xee080200 0 0x700>;
1607			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1608			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1609			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1610			resets = <&cpg 703>, <&cpg 704>;
1611			#phy-cells = <1>;
1612			status = "disabled";
1613		};
1614
1615		sdhi0: sd@ee100000 {
1616			compatible = "renesas,sdhi-r8a774c0",
1617				     "renesas,rcar-gen3-sdhi";
1618			reg = <0 0xee100000 0 0x2000>;
1619			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1620			clocks = <&cpg CPG_MOD 314>;
1621			max-frequency = <200000000>;
1622			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1623			resets = <&cpg 314>;
1624			status = "disabled";
1625		};
1626
1627		sdhi1: sd@ee120000 {
1628			compatible = "renesas,sdhi-r8a774c0",
1629				     "renesas,rcar-gen3-sdhi";
1630			reg = <0 0xee120000 0 0x2000>;
1631			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1632			clocks = <&cpg CPG_MOD 313>;
1633			max-frequency = <200000000>;
1634			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1635			resets = <&cpg 313>;
1636			status = "disabled";
1637		};
1638
1639		sdhi3: sd@ee160000 {
1640			compatible = "renesas,sdhi-r8a774c0",
1641				     "renesas,rcar-gen3-sdhi";
1642			reg = <0 0xee160000 0 0x2000>;
1643			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1644			clocks = <&cpg CPG_MOD 311>;
1645			max-frequency = <200000000>;
1646			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1647			resets = <&cpg 311>;
1648			status = "disabled";
1649		};
1650
1651		gic: interrupt-controller@f1010000 {
1652			compatible = "arm,gic-400";
1653			#interrupt-cells = <3>;
1654			#address-cells = <0>;
1655			interrupt-controller;
1656			reg = <0x0 0xf1010000 0 0x1000>,
1657			      <0x0 0xf1020000 0 0x20000>,
1658			      <0x0 0xf1040000 0 0x20000>,
1659			      <0x0 0xf1060000 0 0x20000>;
1660			interrupts = <GIC_PPI 9
1661					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1662			clocks = <&cpg CPG_MOD 408>;
1663			clock-names = "clk";
1664			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1665			resets = <&cpg 408>;
1666		};
1667
1668		pciec0: pcie@fe000000 {
1669			compatible = "renesas,pcie-r8a774c0",
1670				     "renesas,pcie-rcar-gen3";
1671			reg = <0 0xfe000000 0 0x80000>;
1672			#address-cells = <3>;
1673			#size-cells = <2>;
1674			bus-range = <0x00 0xff>;
1675			device_type = "pci";
1676			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1677				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1678				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1679				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1680			/* Map all possible DDR as inbound ranges */
1681			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1682			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1683				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1684				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1685			#interrupt-cells = <1>;
1686			interrupt-map-mask = <0 0 0 0>;
1687			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1688			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1689			clock-names = "pcie", "pcie_bus";
1690			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1691			resets = <&cpg 319>;
1692			status = "disabled";
1693		};
1694
1695		vspb0: vsp@fe960000 {
1696			compatible = "renesas,vsp2";
1697			reg = <0 0xfe960000 0 0x8000>;
1698			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1699			clocks = <&cpg CPG_MOD 626>;
1700			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1701			resets = <&cpg 626>;
1702			renesas,fcp = <&fcpvb0>;
1703		};
1704
1705		vspd0: vsp@fea20000 {
1706			compatible = "renesas,vsp2";
1707			reg = <0 0xfea20000 0 0x7000>;
1708			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1709			clocks = <&cpg CPG_MOD 623>;
1710			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1711			resets = <&cpg 623>;
1712			renesas,fcp = <&fcpvd0>;
1713		};
1714
1715		vspd1: vsp@fea28000 {
1716			compatible = "renesas,vsp2";
1717			reg = <0 0xfea28000 0 0x7000>;
1718			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1719			clocks = <&cpg CPG_MOD 622>;
1720			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1721			resets = <&cpg 622>;
1722			renesas,fcp = <&fcpvd1>;
1723		};
1724
1725		vspi0: vsp@fe9a0000 {
1726			compatible = "renesas,vsp2";
1727			reg = <0 0xfe9a0000 0 0x8000>;
1728			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1729			clocks = <&cpg CPG_MOD 631>;
1730			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1731			resets = <&cpg 631>;
1732			renesas,fcp = <&fcpvi0>;
1733		};
1734
1735		fcpvb0: fcp@fe96f000 {
1736			compatible = "renesas,fcpv";
1737			reg = <0 0xfe96f000 0 0x200>;
1738			clocks = <&cpg CPG_MOD 607>;
1739			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1740			resets = <&cpg 607>;
1741			iommus = <&ipmmu_vp0 5>;
1742		};
1743
1744		fcpvd0: fcp@fea27000 {
1745			compatible = "renesas,fcpv";
1746			reg = <0 0xfea27000 0 0x200>;
1747			clocks = <&cpg CPG_MOD 603>;
1748			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1749			resets = <&cpg 603>;
1750			iommus = <&ipmmu_vi0 8>;
1751		};
1752
1753		fcpvd1: fcp@fea2f000 {
1754			compatible = "renesas,fcpv";
1755			reg = <0 0xfea2f000 0 0x200>;
1756			clocks = <&cpg CPG_MOD 602>;
1757			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1758			resets = <&cpg 602>;
1759			iommus = <&ipmmu_vi0 9>;
1760		};
1761
1762		fcpvi0: fcp@fe9af000 {
1763			compatible = "renesas,fcpv";
1764			reg = <0 0xfe9af000 0 0x200>;
1765			clocks = <&cpg CPG_MOD 611>;
1766			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1767			resets = <&cpg 611>;
1768			iommus = <&ipmmu_vp0 8>;
1769		};
1770
1771		csi40: csi2@feaa0000 {
1772			compatible = "renesas,r8a774c0-csi2";
1773			reg = <0 0xfeaa0000 0 0x10000>;
1774			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1775			clocks = <&cpg CPG_MOD 716>;
1776			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1777			resets = <&cpg 716>;
1778			status = "disabled";
1779
1780			ports {
1781				#address-cells = <1>;
1782				#size-cells = <0>;
1783
1784				port@1 {
1785					#address-cells = <1>;
1786					#size-cells = <0>;
1787
1788					reg = <1>;
1789
1790					csi40vin4: endpoint@0 {
1791						reg = <0>;
1792						remote-endpoint = <&vin4csi40>;
1793					};
1794					csi40vin5: endpoint@1 {
1795						reg = <1>;
1796						remote-endpoint = <&vin5csi40>;
1797					};
1798				};
1799			};
1800		};
1801
1802		du: display@feb00000 {
1803			compatible = "renesas,du-r8a774c0";
1804			reg = <0 0xfeb00000 0 0x40000>;
1805			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1806				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1807			clocks = <&cpg CPG_MOD 724>,
1808				 <&cpg CPG_MOD 723>;
1809			clock-names = "du.0", "du.1";
1810			vsps = <&vspd0 0>, <&vspd1 0>;
1811			status = "disabled";
1812
1813			ports {
1814				#address-cells = <1>;
1815				#size-cells = <0>;
1816
1817				port@0 {
1818					reg = <0>;
1819					du_out_rgb: endpoint {
1820					};
1821				};
1822
1823				port@1 {
1824					reg = <1>;
1825					du_out_lvds0: endpoint {
1826						remote-endpoint = <&lvds0_in>;
1827					};
1828				};
1829
1830				port@2 {
1831					reg = <2>;
1832					du_out_lvds1: endpoint {
1833						remote-endpoint = <&lvds1_in>;
1834					};
1835				};
1836			};
1837		};
1838
1839		lvds0: lvds-encoder@feb90000 {
1840			compatible = "renesas,r8a774c0-lvds";
1841			reg = <0 0xfeb90000 0 0x20>;
1842			clocks = <&cpg CPG_MOD 727>;
1843			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1844			resets = <&cpg 727>;
1845			status = "disabled";
1846
1847			renesas,companion = <&lvds1>;
1848
1849			ports {
1850				#address-cells = <1>;
1851				#size-cells = <0>;
1852
1853				port@0 {
1854					reg = <0>;
1855					lvds0_in: endpoint {
1856						remote-endpoint = <&du_out_lvds0>;
1857					};
1858				};
1859
1860				port@1 {
1861					reg = <1>;
1862					lvds0_out: endpoint {
1863					};
1864				};
1865			};
1866		};
1867
1868		lvds1: lvds-encoder@feb90100 {
1869			compatible = "renesas,r8a774c0-lvds";
1870			reg = <0 0xfeb90100 0 0x20>;
1871			clocks = <&cpg CPG_MOD 727>;
1872			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1873			resets = <&cpg 726>;
1874			status = "disabled";
1875
1876			ports {
1877				#address-cells = <1>;
1878				#size-cells = <0>;
1879
1880				port@0 {
1881					reg = <0>;
1882					lvds1_in: endpoint {
1883						remote-endpoint = <&du_out_lvds1>;
1884					};
1885				};
1886
1887				port@1 {
1888					reg = <1>;
1889					lvds1_out: endpoint {
1890					};
1891				};
1892			};
1893		};
1894
1895		prr: chipid@fff00044 {
1896			compatible = "renesas,prr";
1897			reg = <0 0xfff00044 0 4>;
1898		};
1899	};
1900
1901	thermal-zones {
1902		cpu-thermal {
1903			polling-delay-passive = <250>;
1904			polling-delay = <1000>;
1905			thermal-sensors = <&thermal>;
1906
1907			cooling-maps {
1908			};
1909
1910			trips {
1911				cpu-crit {
1912					temperature = <120000>;
1913					hysteresis = <2000>;
1914					type = "critical";
1915				};
1916			};
1917		};
1918	};
1919
1920	timer {
1921		compatible = "arm,armv8-timer";
1922		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1923				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1924				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1925				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1926	};
1927
1928	/* External USB clocks - can be overridden by the board */
1929	usb3s0_clk: usb3s0 {
1930		compatible = "fixed-clock";
1931		#clock-cells = <0>;
1932		clock-frequency = <0>;
1933	};
1934
1935	usb_extal_clk: usb_extal {
1936		compatible = "fixed-clock";
1937		#clock-cells = <0>;
1938		clock-frequency = <0>;
1939	};
1940};
1941