1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru (and derivatives) board device tree source 4 * 5 * Copyright 2016-2017 Google, Inc 6 */ 7 8#include <dt-bindings/input/input.h> 9#include "rk3399.dtsi" 10#include "rk3399-op1-opp.dtsi" 11 12/ { 13 chosen { 14 stdout-path = "serial2:115200n8"; 15 }; 16 17 /* 18 * Power Tree 19 * 20 * In general an attempt is made to include all rails called out by 21 * the schematic as long as those rails interact in some way with 22 * the AP. AKA: 23 * - Rails that only connect to the EC (or devices that the EC talks to) 24 * are not included. 25 * - Rails _are_ included if the rails go to the AP even if the AP 26 * doesn't currently care about them / they are always on. The idea 27 * here is that it makes it easier to map to the schematic or extend 28 * later. 29 * 30 * If two rails are substantially the same from the AP's point of 31 * view, though, we won't create a full fixed regulator. We'll just 32 * put the child rail as an alias of the parent rail. Sometimes rails 33 * look the same to the AP because one of these is true: 34 * - The EC controls the enable and the EC always enables a rail as 35 * long as the AP is running. 36 * - The rails are actually connected to each other by a jumper and 37 * the distinction is just there to add clarity/flexibility to the 38 * schematic. 39 */ 40 41 ppvar_sys: ppvar-sys { 42 compatible = "regulator-fixed"; 43 regulator-name = "ppvar_sys"; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 pp1200_lpddr: pp1200-lpddr { 49 compatible = "regulator-fixed"; 50 regulator-name = "pp1200_lpddr"; 51 52 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 53 regulator-always-on; 54 regulator-boot-on; 55 regulator-min-microvolt = <1200000>; 56 regulator-max-microvolt = <1200000>; 57 58 vin-supply = <&ppvar_sys>; 59 }; 60 61 pp1800: pp1800 { 62 compatible = "regulator-fixed"; 63 regulator-name = "pp1800"; 64 65 /* Always on when ppvar_sys shows power good */ 66 regulator-always-on; 67 regulator-boot-on; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <1800000>; 70 71 vin-supply = <&ppvar_sys>; 72 }; 73 74 pp3300: pp3300 { 75 compatible = "regulator-fixed"; 76 regulator-name = "pp3300"; 77 78 /* Always on; plain and simple */ 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 84 vin-supply = <&ppvar_sys>; 85 }; 86 87 pp5000: pp5000 { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp5000"; 90 91 /* EC turns on w/ pp5000_en; always on for AP */ 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-min-microvolt = <5000000>; 95 regulator-max-microvolt = <5000000>; 96 97 vin-supply = <&ppvar_sys>; 98 }; 99 100 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 101 compatible = "pwm-regulator"; 102 regulator-name = "ppvar_bigcpu_pwm"; 103 104 pwms = <&pwm1 0 3337 0>; 105 pwm-supply = <&ppvar_sys>; 106 pwm-dutycycle-range = <100 0>; 107 pwm-dutycycle-unit = <100>; 108 109 /* EC turns on w/ ap_core_en; always on for AP */ 110 regulator-always-on; 111 regulator-boot-on; 112 regulator-min-microvolt = <800107>; 113 regulator-max-microvolt = <1302232>; 114 }; 115 116 ppvar_bigcpu: ppvar-bigcpu { 117 compatible = "vctrl-regulator"; 118 regulator-name = "ppvar_bigcpu"; 119 120 regulator-min-microvolt = <800107>; 121 regulator-max-microvolt = <1302232>; 122 123 ctrl-supply = <&ppvar_bigcpu_pwm>; 124 ctrl-voltage-range = <800107 1302232>; 125 126 regulator-settling-time-up-us = <322>; 127 }; 128 129 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 130 compatible = "pwm-regulator"; 131 regulator-name = "ppvar_litcpu_pwm"; 132 133 pwms = <&pwm2 0 3337 0>; 134 pwm-supply = <&ppvar_sys>; 135 pwm-dutycycle-range = <100 0>; 136 pwm-dutycycle-unit = <100>; 137 138 /* EC turns on w/ ap_core_en; always on for AP */ 139 regulator-always-on; 140 regulator-boot-on; 141 regulator-min-microvolt = <797743>; 142 regulator-max-microvolt = <1307837>; 143 }; 144 145 ppvar_litcpu: ppvar-litcpu { 146 compatible = "vctrl-regulator"; 147 regulator-name = "ppvar_litcpu"; 148 149 regulator-min-microvolt = <797743>; 150 regulator-max-microvolt = <1307837>; 151 152 ctrl-supply = <&ppvar_litcpu_pwm>; 153 ctrl-voltage-range = <797743 1307837>; 154 155 regulator-settling-time-up-us = <384>; 156 }; 157 158 ppvar_gpu_pwm: ppvar-gpu-pwm { 159 compatible = "pwm-regulator"; 160 regulator-name = "ppvar_gpu_pwm"; 161 162 pwms = <&pwm0 0 3337 0>; 163 pwm-supply = <&ppvar_sys>; 164 pwm-dutycycle-range = <100 0>; 165 pwm-dutycycle-unit = <100>; 166 167 /* EC turns on w/ ap_core_en; always on for AP */ 168 regulator-always-on; 169 regulator-boot-on; 170 regulator-min-microvolt = <786384>; 171 regulator-max-microvolt = <1217747>; 172 }; 173 174 ppvar_gpu: ppvar-gpu { 175 compatible = "vctrl-regulator"; 176 regulator-name = "ppvar_gpu"; 177 178 regulator-min-microvolt = <786384>; 179 regulator-max-microvolt = <1217747>; 180 181 ctrl-supply = <&ppvar_gpu_pwm>; 182 ctrl-voltage-range = <786384 1217747>; 183 184 regulator-settling-time-up-us = <390>; 185 }; 186 187 /* EC turns on w/ pp900_ddrpll_en */ 188 pp900_ddrpll: pp900-ap { 189 }; 190 191 /* EC turns on w/ pp900_pll_en */ 192 pp900_pll: pp900-ap { 193 }; 194 195 /* EC turns on w/ pp900_pmu_en */ 196 pp900_pmu: pp900-ap { 197 }; 198 199 /* EC turns on w/ pp1800_s0_en_l */ 200 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 201 }; 202 203 /* EC turns on w/ pp1800_avdd_en_l */ 204 pp1800_avdd: pp1800 { 205 }; 206 207 /* EC turns on w/ pp1800_lid_en_l */ 208 pp1800_lid: pp1800_mic: pp1800 { 209 }; 210 211 /* EC turns on w/ lpddr_pwr_en */ 212 pp1800_lpddr: pp1800 { 213 }; 214 215 /* EC turns on w/ pp1800_pmu_en_l */ 216 pp1800_pmu: pp1800 { 217 }; 218 219 /* EC turns on w/ pp1800_usb_en_l */ 220 pp1800_usb: pp1800 { 221 }; 222 223 pp3000_sd_slot: pp3000-sd-slot { 224 compatible = "regulator-fixed"; 225 regulator-name = "pp3000_sd_slot"; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&sd_slot_pwr_en>; 228 229 enable-active-high; 230 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 231 232 vin-supply = <&pp3000>; 233 }; 234 235 /* 236 * Technically, this is a small abuse of 'regulator-gpio'; this 237 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 238 * always on though, so it is sufficient to simply control the mux 239 * here. 240 */ 241 ppvar_sd_card_io: ppvar-sd-card-io { 242 compatible = "regulator-gpio"; 243 regulator-name = "ppvar_sd_card_io"; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 246 247 enable-active-high; 248 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 249 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 250 states = <1800000 0x1 251 3000000 0x0>; 252 253 regulator-min-microvolt = <1800000>; 254 regulator-max-microvolt = <3000000>; 255 }; 256 257 /* EC turns on w/ pp3300_trackpad_en_l */ 258 pp3300_trackpad: pp3300-trackpad { 259 }; 260 261 /* EC turns on w/ usb_a_en */ 262 pp5000_usb_a_vbus: pp5000 { 263 }; 264 265 ap_rtc_clk: ap-rtc-clk { 266 compatible = "fixed-clock"; 267 clock-frequency = <32768>; 268 clock-output-names = "xin32k"; 269 #clock-cells = <0>; 270 }; 271 272 max98357a: max98357a { 273 compatible = "maxim,max98357a"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&sdmode_en>; 276 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 277 sdmode-delay = <2>; 278 #sound-dai-cells = <0>; 279 status = "okay"; 280 }; 281 282 sound: sound { 283 compatible = "rockchip,rk3399-gru-sound"; 284 rockchip,cpu = <&i2s0 &spdif>; 285 }; 286}; 287 288&cdn_dp { 289 status = "okay"; 290}; 291 292/* 293 * Set some suspend operating points to avoid OVP in suspend 294 * 295 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 296 * from wherever they're at back to the "default" operating point (whatever 297 * voltage we get when we set the PWM pins to "input"). 298 * 299 * This quick transition under light load has the possibility to trigger the 300 * regulator "over voltage protection" (OVP). 301 * 302 * To make extra certain that we don't hit this OVP at suspend time, we'll 303 * transition to a voltage that's much closer to the default (~1.0 V) so that 304 * there will not be a big jump. Technically we only need to get within 200 mV 305 * of the default voltage, but the speed here should be fast enough and we need 306 * suspend/resume to be rock solid. 307 */ 308 309&cluster0_opp { 310 opp05 { 311 opp-suspend; 312 }; 313}; 314 315&cluster1_opp { 316 opp06 { 317 opp-suspend; 318 }; 319}; 320 321&cpu_l0 { 322 cpu-supply = <&ppvar_litcpu>; 323}; 324 325&cpu_l1 { 326 cpu-supply = <&ppvar_litcpu>; 327}; 328 329&cpu_l2 { 330 cpu-supply = <&ppvar_litcpu>; 331}; 332 333&cpu_l3 { 334 cpu-supply = <&ppvar_litcpu>; 335}; 336 337&cpu_b0 { 338 cpu-supply = <&ppvar_bigcpu>; 339}; 340 341&cpu_b1 { 342 cpu-supply = <&ppvar_bigcpu>; 343}; 344 345 346&cru { 347 assigned-clocks = 348 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 349 <&cru PLL_NPLL>, 350 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 351 <&cru PCLK_PERIHP>, 352 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 353 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 354 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 355 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 356 <&cru ACLK_GIC_PRE>, 357 <&cru PCLK_DDR>; 358 assigned-clock-rates = 359 <600000000>, <800000000>, 360 <1000000000>, 361 <150000000>, <75000000>, 362 <37500000>, 363 <100000000>, <100000000>, 364 <50000000>, <800000000>, 365 <100000000>, <50000000>, 366 <400000000>, <400000000>, 367 <200000000>, 368 <200000000>; 369}; 370 371&emmc_phy { 372 status = "okay"; 373}; 374 375&gpu { 376 mali-supply = <&ppvar_gpu>; 377 status = "okay"; 378}; 379 380ap_i2c_ts: &i2c3 { 381 status = "okay"; 382 383 clock-frequency = <400000>; 384 385 /* These are relatively safe rise/fall times */ 386 i2c-scl-falling-time-ns = <50>; 387 i2c-scl-rising-time-ns = <300>; 388}; 389 390ap_i2c_audio: &i2c8 { 391 status = "okay"; 392 393 clock-frequency = <400000>; 394 395 /* These are relatively safe rise/fall times */ 396 i2c-scl-falling-time-ns = <50>; 397 i2c-scl-rising-time-ns = <300>; 398 399 codec: da7219@1a { 400 compatible = "dlg,da7219"; 401 reg = <0x1a>; 402 interrupt-parent = <&gpio1>; 403 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 404 clocks = <&cru SCLK_I2S_8CH_OUT>; 405 clock-names = "mclk"; 406 dlg,micbias-lvl = <2600>; 407 dlg,mic-amp-in-sel = "diff"; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&headset_int_l>; 410 VDD-supply = <&pp1800>; 411 VDDMIC-supply = <&pp3300>; 412 VDDIO-supply = <&pp1800>; 413 414 da7219_aad { 415 dlg,adc-1bit-rpt = <1>; 416 dlg,btn-avg = <4>; 417 dlg,btn-cfg = <50>; 418 dlg,mic-det-thr = <500>; 419 dlg,jack-ins-deb = <20>; 420 dlg,jack-det-rate = "32ms_64ms"; 421 dlg,jack-rem-deb = <1>; 422 423 dlg,a-d-btn-thr = <0xa>; 424 dlg,d-b-btn-thr = <0x16>; 425 dlg,b-c-btn-thr = <0x21>; 426 dlg,c-mic-btn-thr = <0x3E>; 427 }; 428 }; 429}; 430 431&i2s0 { 432 status = "okay"; 433}; 434 435&io_domains { 436 status = "okay"; 437 438 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 439 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 440 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 441 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 442}; 443 444&pcie0 { 445 status = "okay"; 446 447 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 450 vpcie3v3-supply = <&pp3300_wifi_bt>; 451 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 452 vpcie0v9-supply = <&pp900_pcie>; 453 454 pci_rootport: pcie@0,0 { 455 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 456 #address-cells = <3>; 457 #size-cells = <2>; 458 ranges; 459 }; 460}; 461 462&pcie_phy { 463 status = "okay"; 464}; 465 466&pmu_io_domains { 467 status = "okay"; 468 469 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 470}; 471 472&pwm0 { 473 status = "okay"; 474}; 475 476&pwm1 { 477 status = "okay"; 478}; 479 480&pwm2 { 481 status = "okay"; 482}; 483 484&pwm3 { 485 status = "okay"; 486}; 487 488&sdhci { 489 /* 490 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 491 * same (or nearly the same) performance for all eMMC that are intended 492 * to be used. 493 */ 494 assigned-clock-rates = <150000000>; 495 496 bus-width = <8>; 497 mmc-hs400-1_8v; 498 mmc-hs400-enhanced-strobe; 499 non-removable; 500 status = "okay"; 501}; 502 503&sdmmc { 504 status = "okay"; 505 506 /* 507 * Note: configure "sdmmc_cd" as card detect even though it's actually 508 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 509 * should be ignoring card detect anyway. Specifying the pin as 510 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 511 * turned on that the system will still make sure the port is 512 * configured as SDMMC and not JTAG. 513 */ 514 pinctrl-names = "default"; 515 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio 516 &sdmmc_bus4>; 517 518 bus-width = <4>; 519 cap-mmc-highspeed; 520 cap-sd-highspeed; 521 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 522 disable-wp; 523 sd-uhs-sdr12; 524 sd-uhs-sdr25; 525 sd-uhs-sdr50; 526 sd-uhs-sdr104; 527 vmmc-supply = <&pp3000_sd_slot>; 528 vqmmc-supply = <&ppvar_sd_card_io>; 529}; 530 531&spdif { 532 status = "okay"; 533 534 /* 535 * SPDIF is routed internally to DP; we either don't use these pins, or 536 * mux them to something else. 537 */ 538 /delete-property/ pinctrl-0; 539 /delete-property/ pinctrl-names; 540}; 541 542&spi1 { 543 status = "okay"; 544 545 pinctrl-names = "default", "sleep"; 546 pinctrl-1 = <&spi1_sleep>; 547 548 spiflash@0 { 549 compatible = "jedec,spi-nor"; 550 reg = <0>; 551 552 /* May run faster once verified. */ 553 spi-max-frequency = <10000000>; 554 }; 555}; 556 557&spi2 { 558 status = "okay"; 559}; 560 561&spi5 { 562 status = "okay"; 563 564 cros_ec: ec@0 { 565 compatible = "google,cros-ec-spi"; 566 reg = <0>; 567 interrupt-parent = <&gpio0>; 568 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&ec_ap_int_l>; 571 spi-max-frequency = <3000000>; 572 573 i2c_tunnel: i2c-tunnel { 574 compatible = "google,cros-ec-i2c-tunnel"; 575 google,remote-bus = <4>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 }; 579 580 usbc_extcon0: extcon@0 { 581 compatible = "google,extcon-usbc-cros-ec"; 582 google,usb-port-id = <0>; 583 584 #extcon-cells = <0>; 585 }; 586 }; 587}; 588 589&tsadc { 590 status = "okay"; 591 592 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 593 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 594}; 595 596&tcphy0 { 597 status = "okay"; 598 extcon = <&usbc_extcon0>; 599}; 600 601&u2phy0 { 602 status = "okay"; 603}; 604 605&u2phy0_host { 606 status = "okay"; 607}; 608 609&u2phy1_host { 610 status = "okay"; 611}; 612 613&u2phy0_otg { 614 status = "okay"; 615}; 616 617&u2phy1_otg { 618 status = "okay"; 619}; 620 621&uart2 { 622 status = "okay"; 623}; 624 625&usb_host0_ohci { 626 status = "okay"; 627}; 628 629&usbdrd3_0 { 630 status = "okay"; 631 extcon = <&usbc_extcon0>; 632}; 633 634&usbdrd_dwc3_0 { 635 status = "okay"; 636 dr_mode = "host"; 637}; 638 639&vopb { 640 status = "okay"; 641}; 642 643&vopb_mmu { 644 status = "okay"; 645}; 646 647&vopl { 648 status = "okay"; 649}; 650 651&vopl_mmu { 652 status = "okay"; 653}; 654 655#include <arm/cros-ec-keyboard.dtsi> 656#include <arm/cros-ec-sbs.dtsi> 657 658&pinctrl { 659 /* 660 * pinctrl settings for pins that have no real owners. 661 * 662 * At the moment settings are identical for S0 and S3, but if we later 663 * need to configure things differently for S3 we'll adjust here. 664 */ 665 pinctrl-names = "default"; 666 pinctrl-0 = < 667 &ap_pwroff /* AP will auto-assert this when in S3 */ 668 &clk_32k /* This pin is always 32k on gru boards */ 669 >; 670 671 pcfg_output_low: pcfg-output-low { 672 output-low; 673 }; 674 675 pcfg_output_high: pcfg-output-high { 676 output-high; 677 }; 678 679 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 680 bias-disable; 681 drive-strength = <8>; 682 }; 683 684 backlight-enable { 685 bl_en: bl-en { 686 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 687 }; 688 }; 689 690 cros-ec { 691 ec_ap_int_l: ec-ap-int-l { 692 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 693 }; 694 }; 695 696 discrete-regulators { 697 sd_io_pwr_en: sd-io-pwr-en { 698 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO 699 &pcfg_pull_none>; 700 }; 701 702 sd_pwr_1800_sel: sd-pwr-1800-sel { 703 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 704 &pcfg_pull_none>; 705 }; 706 707 sd_slot_pwr_en: sd-slot-pwr-en { 708 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO 709 &pcfg_pull_none>; 710 }; 711 }; 712 713 codec { 714 /* Has external pullup */ 715 headset_int_l: headset-int-l { 716 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 717 }; 718 719 mic_int: mic-int { 720 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; 721 }; 722 }; 723 724 max98357a { 725 sdmode_en: sdmode-en { 726 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 727 }; 728 }; 729 730 pcie { 731 pcie_clkreqn_cpm: pci-clkreqn-cpm { 732 /* 733 * Since our pcie doesn't support ClockPM(CPM), we want 734 * to hack this as gpio, so the EP could be able to 735 * de-assert it along and make ClockPM(CPM) work. 736 */ 737 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 738 }; 739 }; 740 741 sdmmc { 742 /* 743 * We run sdmmc at max speed; bump up drive strength. 744 * We also have external pulls, so disable the internal ones. 745 */ 746 sdmmc_bus4: sdmmc-bus4 { 747 rockchip,pins = 748 <4 RK_PB0 1 &pcfg_pull_none_8ma>, 749 <4 RK_PB1 1 &pcfg_pull_none_8ma>, 750 <4 RK_PB2 1 &pcfg_pull_none_8ma>, 751 <4 RK_PB3 1 &pcfg_pull_none_8ma>; 752 }; 753 754 sdmmc_clk: sdmmc-clk { 755 rockchip,pins = 756 <4 RK_PB4 1 &pcfg_pull_none_8ma>; 757 }; 758 759 sdmmc_cmd: sdmmc-cmd { 760 rockchip,pins = 761 <4 RK_PB5 1 &pcfg_pull_none_8ma>; 762 }; 763 764 /* 765 * In our case the official card detect is hooked to ground 766 * to avoid getting access to JTAG just by sticking something 767 * in the SD card slot (see the force_jtag bit in the TRM). 768 * 769 * We still configure it as card detect because it doesn't 770 * hurt and dw_mmc will ignore it. We make sure to disable 771 * the pull though so we don't burn needless power. 772 */ 773 sdmmc_cd: sdmmc-cd { 774 rockchip,pins = 775 <0 RK_PA7 1 &pcfg_pull_none>; 776 }; 777 778 /* This is where we actually hook up CD; has external pull */ 779 sdmmc_cd_gpio: sdmmc-cd-gpio { 780 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 781 }; 782 }; 783 784 spi1 { 785 spi1_sleep: spi1-sleep { 786 /* 787 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 788 * prevent leakage. 789 */ 790 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, 791 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, 792 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, 793 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; 794 }; 795 }; 796 797 touchscreen { 798 touch_int_l: touch-int-l { 799 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 800 }; 801 802 touch_reset_l: touch-reset-l { 803 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 804 }; 805 }; 806 807 trackpad { 808 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 809 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; 810 }; 811 812 trackpad_int_l: trackpad-int-l { 813 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 814 }; 815 }; 816 817 wifi: wifi { 818 wlan_module_reset_l: wlan-module-reset-l { 819 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 820 }; 821 822 bt_host_wake_l: bt-host-wake-l { 823 /* Kevin has an external pull up, but Gru does not */ 824 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 825 }; 826 }; 827 828 write-protect { 829 ap_fw_wp: ap-fw-wp { 830 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 831 }; 832 }; 833}; 834