1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Ralink RT288x SoC PCI register definitions
4 *
5 * Copyright (C) 2009 John Crispin <john@phrozen.org>
6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 *
8 * Parts of this file are based on Ralink's 2.6.21 BSP
9 */
10
11 #include <linux/delay.h>
12 #include <linux/types.h>
13 #include <linux/pci.h>
14 #include <linux/io.h>
15 #include <linux/init.h>
16 #include <linux/of_platform.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_pci.h>
19
20 #include <asm/mach-ralink/rt288x.h>
21
22 #define RT2880_PCI_BASE 0x00440000
23 #define RT288X_CPU_IRQ_PCI 4
24
25 #define RT2880_PCI_MEM_BASE 0x20000000
26 #define RT2880_PCI_MEM_SIZE 0x10000000
27 #define RT2880_PCI_IO_BASE 0x00460000
28 #define RT2880_PCI_IO_SIZE 0x00010000
29
30 #define RT2880_PCI_REG_PCICFG_ADDR 0x00
31 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
32 #define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
33 #define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
34 #define RT2880_PCI_REG_CONFIG_ADDR 0x20
35 #define RT2880_PCI_REG_CONFIG_DATA 0x24
36 #define RT2880_PCI_REG_MEMBASE 0x28
37 #define RT2880_PCI_REG_IOBASE 0x2c
38 #define RT2880_PCI_REG_ID 0x30
39 #define RT2880_PCI_REG_CLASS 0x34
40 #define RT2880_PCI_REG_SUBID 0x38
41 #define RT2880_PCI_REG_ARBCTL 0x80
42
43 static void __iomem *rt2880_pci_base;
44 static DEFINE_SPINLOCK(rt2880_pci_lock);
45
rt2880_pci_reg_read(u32 reg)46 static u32 rt2880_pci_reg_read(u32 reg)
47 {
48 return readl(rt2880_pci_base + reg);
49 }
50
rt2880_pci_reg_write(u32 val,u32 reg)51 static void rt2880_pci_reg_write(u32 val, u32 reg)
52 {
53 writel(val, rt2880_pci_base + reg);
54 }
55
rt2880_pci_get_cfgaddr(unsigned int bus,unsigned int slot,unsigned int func,unsigned int where)56 static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
57 unsigned int func, unsigned int where)
58 {
59 return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
60 0x80000000);
61 }
62
rt2880_pci_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)63 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
64 int where, int size, u32 *val)
65 {
66 unsigned long flags;
67 u32 address;
68 u32 data;
69
70 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
71 PCI_FUNC(devfn), where);
72
73 spin_lock_irqsave(&rt2880_pci_lock, flags);
74 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
75 data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
76 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
77
78 switch (size) {
79 case 1:
80 *val = (data >> ((where & 3) << 3)) & 0xff;
81 break;
82 case 2:
83 *val = (data >> ((where & 3) << 3)) & 0xffff;
84 break;
85 case 4:
86 *val = data;
87 break;
88 }
89
90 return PCIBIOS_SUCCESSFUL;
91 }
92
rt2880_pci_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)93 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
94 int where, int size, u32 val)
95 {
96 unsigned long flags;
97 u32 address;
98 u32 data;
99
100 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
101 PCI_FUNC(devfn), where);
102
103 spin_lock_irqsave(&rt2880_pci_lock, flags);
104 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
105 data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
106
107 switch (size) {
108 case 1:
109 data = (data & ~(0xff << ((where & 3) << 3))) |
110 (val << ((where & 3) << 3));
111 break;
112 case 2:
113 data = (data & ~(0xffff << ((where & 3) << 3))) |
114 (val << ((where & 3) << 3));
115 break;
116 case 4:
117 data = val;
118 break;
119 }
120
121 rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
122 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
123
124 return PCIBIOS_SUCCESSFUL;
125 }
126
127 static struct pci_ops rt2880_pci_ops = {
128 .read = rt2880_pci_config_read,
129 .write = rt2880_pci_config_write,
130 };
131
132 static struct resource rt2880_pci_mem_resource = {
133 .name = "PCI MEM space",
134 .start = RT2880_PCI_MEM_BASE,
135 .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
136 .flags = IORESOURCE_MEM,
137 };
138
139 static struct resource rt2880_pci_io_resource = {
140 .name = "PCI IO space",
141 .start = RT2880_PCI_IO_BASE,
142 .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
143 .flags = IORESOURCE_IO,
144 };
145
146 static struct pci_controller rt2880_pci_controller = {
147 .pci_ops = &rt2880_pci_ops,
148 .mem_resource = &rt2880_pci_mem_resource,
149 .io_resource = &rt2880_pci_io_resource,
150 };
151
rt2880_pci_read_u32(unsigned long reg)152 static inline u32 rt2880_pci_read_u32(unsigned long reg)
153 {
154 unsigned long flags;
155 u32 address;
156 u32 ret;
157
158 address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
159
160 spin_lock_irqsave(&rt2880_pci_lock, flags);
161 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
162 ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
163 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
164
165 return ret;
166 }
167
rt2880_pci_write_u32(unsigned long reg,u32 val)168 static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
169 {
170 unsigned long flags;
171 u32 address;
172
173 address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
174
175 spin_lock_irqsave(&rt2880_pci_lock, flags);
176 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
177 rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
178 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
179 }
180
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)181 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
182 {
183 int irq = -1;
184
185 if (dev->bus->number != 0)
186 return irq;
187
188 switch (PCI_SLOT(dev->devfn)) {
189 case 0x00:
190 break;
191 case 0x11:
192 irq = RT288X_CPU_IRQ_PCI;
193 break;
194 default:
195 pr_err("%s:%s[%d] trying to alloc unknown pci irq\n",
196 __FILE__, __func__, __LINE__);
197 BUG();
198 break;
199 }
200
201 return irq;
202 }
203
rt288x_pci_probe(struct platform_device * pdev)204 static int rt288x_pci_probe(struct platform_device *pdev)
205 {
206 void __iomem *io_map_base;
207
208 rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
209
210 io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
211 rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
212 set_io_port_base((unsigned long) io_map_base);
213
214 ioport_resource.start = RT2880_PCI_IO_BASE;
215 ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
216
217 rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
218 udelay(1);
219
220 rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
221 rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
222 rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
223 rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
224 rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
225 rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
226 rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
227 rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
228 rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
229
230 rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
231 (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
232
233 rt2880_pci_controller.of_node = pdev->dev.of_node;
234
235 register_pci_controller(&rt2880_pci_controller);
236 return 0;
237 }
238
pcibios_plat_dev_init(struct pci_dev * dev)239 int pcibios_plat_dev_init(struct pci_dev *dev)
240 {
241 static bool slot0_init;
242
243 /*
244 * Nobody seems to initialize slot 0, but this platform requires it, so
245 * do it once when some other slot is being enabled. The PCI subsystem
246 * should configure other slots properly, so no need to do anything
247 * special for those.
248 */
249 if (!slot0_init && dev->bus->number == 0) {
250 u16 cmd;
251 u32 bar0;
252
253 slot0_init = true;
254
255 pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
256 0x08000000);
257 pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
258 &bar0);
259
260 pci_bus_read_config_word(dev->bus, 0, PCI_COMMAND, &cmd);
261 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
262 pci_bus_write_config_word(dev->bus, 0, PCI_COMMAND, cmd);
263 }
264
265 return 0;
266 }
267
268 static const struct of_device_id rt288x_pci_match[] = {
269 { .compatible = "ralink,rt288x-pci" },
270 {},
271 };
272
273 static struct platform_driver rt288x_pci_driver = {
274 .probe = rt288x_pci_probe,
275 .driver = {
276 .name = "rt288x-pci",
277 .of_match_table = rt288x_pci_match,
278 },
279 };
280
pcibios_init(void)281 int __init pcibios_init(void)
282 {
283 int ret = platform_driver_register(&rt288x_pci_driver);
284
285 if (ret)
286 pr_info("rt288x-pci: Error registering platform driver!");
287
288 return ret;
289 }
290
291 arch_initcall(pcibios_init);
292