1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Interrupt handing routines for NEC VR4100 series. 4 * 5 * Copyright (C) 2005-2007 Yoichi Yuasa <yuasa@linux-mips.org> 6 */ 7 #include <linux/export.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 11 #include <asm/irq_cpu.h> 12 #include <asm/vr41xx/irq.h> 13 14 typedef struct irq_cascade { 15 int (*get_irq)(unsigned int); 16 } irq_cascade_t; 17 18 static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; 19 20 static struct irqaction cascade_irqaction = { 21 .handler = no_action, 22 .name = "cascade", 23 .flags = IRQF_NO_THREAD, 24 }; 25 cascade_irq(unsigned int irq,int (* get_irq)(unsigned int))26int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int)) 27 { 28 int retval = 0; 29 30 if (irq >= NR_IRQS) 31 return -EINVAL; 32 33 if (irq_cascade[irq].get_irq != NULL) 34 free_irq(irq, NULL); 35 36 irq_cascade[irq].get_irq = get_irq; 37 38 if (get_irq != NULL) { 39 retval = setup_irq(irq, &cascade_irqaction); 40 if (retval < 0) 41 irq_cascade[irq].get_irq = NULL; 42 } 43 44 return retval; 45 } 46 47 EXPORT_SYMBOL_GPL(cascade_irq); 48 irq_dispatch(unsigned int irq)49static void irq_dispatch(unsigned int irq) 50 { 51 irq_cascade_t *cascade; 52 53 if (irq >= NR_IRQS) { 54 atomic_inc(&irq_err_count); 55 return; 56 } 57 58 cascade = irq_cascade + irq; 59 if (cascade->get_irq != NULL) { 60 struct irq_desc *desc = irq_to_desc(irq); 61 struct irq_data *idata = irq_desc_get_irq_data(desc); 62 struct irq_chip *chip = irq_desc_get_chip(desc); 63 int ret; 64 65 if (chip->irq_mask_ack) 66 chip->irq_mask_ack(idata); 67 else { 68 chip->irq_mask(idata); 69 chip->irq_ack(idata); 70 } 71 ret = cascade->get_irq(irq); 72 irq = ret; 73 if (ret < 0) 74 atomic_inc(&irq_err_count); 75 else 76 irq_dispatch(irq); 77 if (!irqd_irq_disabled(idata) && chip->irq_unmask) 78 chip->irq_unmask(idata); 79 } else 80 do_IRQ(irq); 81 } 82 plat_irq_dispatch(void)83asmlinkage void plat_irq_dispatch(void) 84 { 85 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 86 87 if (pending & CAUSEF_IP7) 88 do_IRQ(TIMER_IRQ); 89 else if (pending & 0x7800) { 90 if (pending & CAUSEF_IP3) 91 irq_dispatch(INT1_IRQ); 92 else if (pending & CAUSEF_IP4) 93 irq_dispatch(INT2_IRQ); 94 else if (pending & CAUSEF_IP5) 95 irq_dispatch(INT3_IRQ); 96 else if (pending & CAUSEF_IP6) 97 irq_dispatch(INT4_IRQ); 98 } else if (pending & CAUSEF_IP2) 99 irq_dispatch(INT0_IRQ); 100 else if (pending & CAUSEF_IP0) 101 do_IRQ(MIPS_SOFTINT0_IRQ); 102 else if (pending & CAUSEF_IP1) 103 do_IRQ(MIPS_SOFTINT1_IRQ); 104 else 105 spurious_interrupt(); 106 } 107 arch_init_irq(void)108void __init arch_init_irq(void) 109 { 110 mips_cpu_irq_init(); 111 } 112