1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
3 #define _ASM_POWERPC_NOHASH_32_PGTABLE_H
4
5 #define __ARCH_USE_5LEVEL_HACK
6 #include <asm-generic/pgtable-nopmd.h>
7
8 #ifndef __ASSEMBLY__
9 #include <linux/sched.h>
10 #include <linux/threads.h>
11 #include <asm/mmu.h> /* For sub-arch specific PPC_PIN_SIZE */
12 #include <asm/asm-405.h>
13
14 #ifdef CONFIG_44x
15 extern int icache_44x_need_flush;
16 #endif
17
18 #endif /* __ASSEMBLY__ */
19
20 #define PTE_INDEX_SIZE PTE_SHIFT
21 #define PMD_INDEX_SIZE 0
22 #define PUD_INDEX_SIZE 0
23 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
24
25 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
26 #define PUD_CACHE_INDEX PUD_INDEX_SIZE
27
28 #ifndef __ASSEMBLY__
29 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
30 #define PMD_TABLE_SIZE 0
31 #define PUD_TABLE_SIZE 0
32 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
33 #endif /* __ASSEMBLY__ */
34
35 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
36 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
37
38 /*
39 * The normal case is that PTEs are 32-bits and we have a 1-page
40 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
41 *
42 * For any >32-bit physical address platform, we can use the following
43 * two level page table layout where the pgdir is 8KB and the MS 13 bits
44 * are an index to the second level table. The combined pgdir/pmd first
45 * level has 2048 entries and the second level has 512 64-bit PTE entries.
46 * -Matt
47 */
48 /* PGDIR_SHIFT determines what a top-level page table entry can map */
49 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
50 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
51 #define PGDIR_MASK (~(PGDIR_SIZE-1))
52
53 /* Bits to mask out from a PGD to get to the PUD page */
54 #define PGD_MASKED_BITS 0
55
56 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
57 #define FIRST_USER_ADDRESS 0UL
58
59 #define pte_ERROR(e) \
60 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
61 (unsigned long long)pte_val(e))
62 #define pgd_ERROR(e) \
63 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
64
65 #ifndef __ASSEMBLY__
66
67 int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot);
68
69 #endif /* !__ASSEMBLY__ */
70
71
72 /*
73 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
74 * value (for now) on others, from where we can start layout kernel
75 * virtual space that goes below PKMAP and FIXMAP
76 */
77 #include <asm/fixmap.h>
78
79 /*
80 * ioremap_bot starts at that address. Early ioremaps move down from there,
81 * until mem_init() at which point this becomes the top of the vmalloc
82 * and ioremap space
83 */
84 #ifdef CONFIG_HIGHMEM
85 #define IOREMAP_TOP PKMAP_BASE
86 #else
87 #define IOREMAP_TOP FIXADDR_START
88 #endif
89
90 /* PPC32 shares vmalloc area with ioremap */
91 #define IOREMAP_START VMALLOC_START
92 #define IOREMAP_END VMALLOC_END
93
94 /*
95 * Just any arbitrary offset to the start of the vmalloc VM area: the
96 * current 16MB value just means that there will be a 64MB "hole" after the
97 * physical memory until the kernel virtual memory starts. That means that
98 * any out-of-bounds memory accesses will hopefully be caught.
99 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
100 * area for the same reason. ;)
101 *
102 * We no longer map larger than phys RAM with the BATs so we don't have
103 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
104 * about clashes between our early calls to ioremap() that start growing down
105 * from IOREMAP_TOP being run into the VM area allocations (growing upwards
106 * from VMALLOC_START). For this reason we have ioremap_bot to check when
107 * we actually run into our mappings setup in the early boot with the VM
108 * system. This really does become a problem for machines with good amounts
109 * of RAM. -- Cort
110 */
111 #define VMALLOC_OFFSET (0x1000000) /* 16M */
112 #ifdef PPC_PIN_SIZE
113 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
114 #else
115 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
116 #endif
117 #define VMALLOC_END ioremap_bot
118
119 /*
120 * Bits in a linux-style PTE. These match the bits in the
121 * (hardware-defined) PowerPC PTE as closely as possible.
122 */
123
124 #if defined(CONFIG_40x)
125 #include <asm/nohash/32/pte-40x.h>
126 #elif defined(CONFIG_44x)
127 #include <asm/nohash/32/pte-44x.h>
128 #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
129 #include <asm/nohash/pte-book3e.h>
130 #elif defined(CONFIG_FSL_BOOKE)
131 #include <asm/nohash/32/pte-fsl-booke.h>
132 #elif defined(CONFIG_PPC_8xx)
133 #include <asm/nohash/32/pte-8xx.h>
134 #endif
135
136 /*
137 * Location of the PFN in the PTE. Most 32-bit platforms use the same
138 * as _PAGE_SHIFT here (ie, naturally aligned).
139 * Platform who don't just pre-define the value so we don't override it here.
140 */
141 #ifndef PTE_RPN_SHIFT
142 #define PTE_RPN_SHIFT (PAGE_SHIFT)
143 #endif
144
145 /*
146 * The mask covered by the RPN must be a ULL on 32-bit platforms with
147 * 64-bit PTEs.
148 */
149 #if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
150 #define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1))
151 #define MAX_POSSIBLE_PHYSMEM_BITS 36
152 #else
153 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
154 #define MAX_POSSIBLE_PHYSMEM_BITS 32
155 #endif
156
157 /*
158 * _PAGE_CHG_MASK masks of bits that are to be preserved across
159 * pgprot changes.
160 */
161 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPECIAL)
162
163 #ifndef __ASSEMBLY__
164
165 #define pte_clear(mm, addr, ptep) \
166 do { pte_update(ptep, ~0, 0); } while (0)
167
168 #ifndef pte_mkwrite
pte_mkwrite(pte_t pte)169 static inline pte_t pte_mkwrite(pte_t pte)
170 {
171 return __pte(pte_val(pte) | _PAGE_RW);
172 }
173 #endif
174
pte_mkdirty(pte_t pte)175 static inline pte_t pte_mkdirty(pte_t pte)
176 {
177 return __pte(pte_val(pte) | _PAGE_DIRTY);
178 }
179
pte_mkyoung(pte_t pte)180 static inline pte_t pte_mkyoung(pte_t pte)
181 {
182 return __pte(pte_val(pte) | _PAGE_ACCESSED);
183 }
184
185 #ifndef pte_wrprotect
pte_wrprotect(pte_t pte)186 static inline pte_t pte_wrprotect(pte_t pte)
187 {
188 return __pte(pte_val(pte) & ~_PAGE_RW);
189 }
190 #endif
191
pte_mkexec(pte_t pte)192 static inline pte_t pte_mkexec(pte_t pte)
193 {
194 return __pte(pte_val(pte) | _PAGE_EXEC);
195 }
196
197 #define pmd_none(pmd) (!pmd_val(pmd))
198 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
199 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
pmd_clear(pmd_t * pmdp)200 static inline void pmd_clear(pmd_t *pmdp)
201 {
202 *pmdp = __pmd(0);
203 }
204
205
206
207 /*
208 * PTE updates. This function is called whenever an existing
209 * valid PTE is updated. This does -not- include set_pte_at()
210 * which nowadays only sets a new PTE.
211 *
212 * Depending on the type of MMU, we may need to use atomic updates
213 * and the PTE may be either 32 or 64 bit wide. In the later case,
214 * when using atomic updates, only the low part of the PTE is
215 * accessed atomically.
216 *
217 * In addition, on 44x, we also maintain a global flag indicating
218 * that an executable user mapping was modified, which is needed
219 * to properly flush the virtually tagged instruction cache of
220 * those implementations.
221 */
222 #ifndef CONFIG_PTE_64BIT
pte_update(pte_t * p,unsigned long clr,unsigned long set)223 static inline unsigned long pte_update(pte_t *p,
224 unsigned long clr,
225 unsigned long set)
226 {
227 #ifdef PTE_ATOMIC_UPDATES
228 unsigned long old, tmp;
229
230 __asm__ __volatile__("\
231 1: lwarx %0,0,%3\n\
232 andc %1,%0,%4\n\
233 or %1,%1,%5\n"
234 PPC405_ERR77(0,%3)
235 " stwcx. %1,0,%3\n\
236 bne- 1b"
237 : "=&r" (old), "=&r" (tmp), "=m" (*p)
238 : "r" (p), "r" (clr), "r" (set), "m" (*p)
239 : "cc" );
240 #else /* PTE_ATOMIC_UPDATES */
241 unsigned long old = pte_val(*p);
242 unsigned long new = (old & ~clr) | set;
243
244 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
245 p->pte = p->pte1 = p->pte2 = p->pte3 = new;
246 #else
247 *p = __pte(new);
248 #endif
249 #endif /* !PTE_ATOMIC_UPDATES */
250
251 #ifdef CONFIG_44x
252 if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
253 icache_44x_need_flush = 1;
254 #endif
255 return old;
256 }
257 #else /* CONFIG_PTE_64BIT */
pte_update(pte_t * p,unsigned long clr,unsigned long set)258 static inline unsigned long long pte_update(pte_t *p,
259 unsigned long clr,
260 unsigned long set)
261 {
262 #ifdef PTE_ATOMIC_UPDATES
263 unsigned long long old;
264 unsigned long tmp;
265
266 __asm__ __volatile__("\
267 1: lwarx %L0,0,%4\n\
268 lwzx %0,0,%3\n\
269 andc %1,%L0,%5\n\
270 or %1,%1,%6\n"
271 PPC405_ERR77(0,%3)
272 " stwcx. %1,0,%4\n\
273 bne- 1b"
274 : "=&r" (old), "=&r" (tmp), "=m" (*p)
275 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
276 : "cc" );
277 #else /* PTE_ATOMIC_UPDATES */
278 unsigned long long old = pte_val(*p);
279 *p = __pte((old & ~(unsigned long long)clr) | set);
280 #endif /* !PTE_ATOMIC_UPDATES */
281
282 #ifdef CONFIG_44x
283 if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
284 icache_44x_need_flush = 1;
285 #endif
286 return old;
287 }
288 #endif /* CONFIG_PTE_64BIT */
289
290 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(unsigned int context,unsigned long addr,pte_t * ptep)291 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
292 {
293 unsigned long old;
294 old = pte_update(ptep, _PAGE_ACCESSED, 0);
295 return (old & _PAGE_ACCESSED) != 0;
296 }
297 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
298 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
299
300 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)301 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
302 pte_t *ptep)
303 {
304 return __pte(pte_update(ptep, ~0, 0));
305 }
306
307 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long addr,pte_t * ptep)308 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
309 pte_t *ptep)
310 {
311 unsigned long clr = ~pte_val(pte_wrprotect(__pte(~0)));
312 unsigned long set = pte_val(pte_wrprotect(__pte(0)));
313
314 pte_update(ptep, clr, set);
315 }
316
__ptep_set_access_flags(struct vm_area_struct * vma,pte_t * ptep,pte_t entry,unsigned long address,int psize)317 static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
318 pte_t *ptep, pte_t entry,
319 unsigned long address,
320 int psize)
321 {
322 pte_t pte_set = pte_mkyoung(pte_mkdirty(pte_mkwrite(pte_mkexec(__pte(0)))));
323 pte_t pte_clr = pte_mkyoung(pte_mkdirty(pte_mkwrite(pte_mkexec(__pte(~0)))));
324 unsigned long set = pte_val(entry) & pte_val(pte_set);
325 unsigned long clr = ~pte_val(entry) & ~pte_val(pte_clr);
326
327 pte_update(ptep, clr, set);
328
329 flush_tlb_page(vma, address);
330 }
331
pte_young(pte_t pte)332 static inline int pte_young(pte_t pte)
333 {
334 return pte_val(pte) & _PAGE_ACCESSED;
335 }
336
337 #define __HAVE_ARCH_PTE_SAME
338 #define pte_same(A,B) ((pte_val(A) ^ pte_val(B)) == 0)
339
340 /*
341 * Note that on Book E processors, the pmd contains the kernel virtual
342 * (lowmem) address of the pte page. The physical address is less useful
343 * because everything runs with translation enabled (even the TLB miss
344 * handler). On everything else the pmd contains the physical address
345 * of the pte page. -- paulus
346 */
347 #ifndef CONFIG_BOOKE
348 #define pmd_page_vaddr(pmd) \
349 ((unsigned long)__va(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
350 #define pmd_page(pmd) \
351 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
352 #else
353 #define pmd_page_vaddr(pmd) \
354 ((unsigned long)(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
355 #define pmd_page(pmd) \
356 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
357 #endif
358
359 /* to find an entry in a kernel page-table-directory */
360 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
361
362 /* to find an entry in a page-table-directory */
363 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
364 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
365
366 /* Find an entry in the third-level page table.. */
367 #define pte_index(address) \
368 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
369 #define pte_offset_kernel(dir, addr) \
370 (pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \
371 pte_index(addr))
372 #define pte_offset_map(dir, addr) \
373 ((pte_t *)(kmap_atomic(pmd_page(*(dir))) + \
374 (pmd_page_vaddr(*(dir)) & ~PAGE_MASK)) + pte_index(addr))
375 #define pte_unmap(pte) kunmap_atomic(pte)
376
377 /*
378 * Encode and decode a swap entry.
379 * Note that the bits we use in a PTE for representing a swap entry
380 * must not include the _PAGE_PRESENT bit.
381 * -- paulus
382 */
383 #define __swp_type(entry) ((entry).val & 0x1f)
384 #define __swp_offset(entry) ((entry).val >> 5)
385 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
386 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
387 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
388
389 #endif /* !__ASSEMBLY__ */
390
391 #endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */
392