1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * FPU support code, moved here from head.S so that it can be used 4 * by chips which use other head-whatever.S files. 5 * 6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Copyright (C) 1996 Paul Mackerras. 9 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 10 */ 11 12#include <asm/reg.h> 13#include <asm/page.h> 14#include <asm/mmu.h> 15#include <asm/pgtable.h> 16#include <asm/cputable.h> 17#include <asm/cache.h> 18#include <asm/thread_info.h> 19#include <asm/ppc_asm.h> 20#include <asm/asm-offsets.h> 21#include <asm/ptrace.h> 22#include <asm/export.h> 23#include <asm/asm-compat.h> 24#include <asm/feature-fixups.h> 25 26#ifdef CONFIG_VSX 27#define __REST_1FPVSR(n,c,base) \ 28BEGIN_FTR_SECTION \ 29 b 2f; \ 30END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 31 REST_FPR(n,base); \ 32 b 3f; \ 332: REST_VSR(n,c,base); \ 343: 35 36#define __REST_32FPVSRS(n,c,base) \ 37BEGIN_FTR_SECTION \ 38 b 2f; \ 39END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 40 REST_32FPRS(n,base); \ 41 b 3f; \ 422: REST_32VSRS(n,c,base); \ 433: 44 45#define __SAVE_32FPVSRS(n,c,base) \ 46BEGIN_FTR_SECTION \ 47 b 2f; \ 48END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 49 SAVE_32FPRS(n,base); \ 50 b 3f; \ 512: SAVE_32VSRS(n,c,base); \ 523: 53#else 54#define __REST_1FPVSR(n,b,base) REST_FPR(n, base) 55#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) 56#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) 57#endif 58#define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base) 59#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) 60#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) 61 62/* 63 * Load state from memory into FP registers including FPSCR. 64 * Assumes the caller has enabled FP in the MSR. 65 */ 66_GLOBAL(load_fp_state) 67 lfd fr0,FPSTATE_FPSCR(r3) 68 MTFSF_L(fr0) 69 REST_32FPVSRS(0, R4, R3) 70 blr 71EXPORT_SYMBOL(load_fp_state) 72_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */ 73 74/* 75 * Store FP state into memory, including FPSCR 76 * Assumes the caller has enabled FP in the MSR. 77 */ 78_GLOBAL(store_fp_state) 79 SAVE_32FPVSRS(0, R4, R3) 80 mffs fr0 81 stfd fr0,FPSTATE_FPSCR(r3) 82 REST_1FPVSR(0, R4, R3) 83 blr 84EXPORT_SYMBOL(store_fp_state) 85 86/* 87 * This task wants to use the FPU now. 88 * On UP, disable FP for the task which had the FPU previously, 89 * and save its floating-point registers in its thread_struct. 90 * Load up this task's FP registers from its thread_struct, 91 * enable the FPU for the current task and return to the task. 92 * Note that on 32-bit this can only use registers that will be 93 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 94 */ 95_GLOBAL(load_up_fpu) 96 mfmsr r5 97 ori r5,r5,MSR_FP 98#ifdef CONFIG_VSX 99BEGIN_FTR_SECTION 100 oris r5,r5,MSR_VSX@h 101END_FTR_SECTION_IFSET(CPU_FTR_VSX) 102#endif 103 SYNC 104 MTMSRD(r5) /* enable use of fpu now */ 105 isync 106 /* enable use of FP after return */ 107#ifdef CONFIG_PPC32 108 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 109 lwz r4,THREAD_FPEXC_MODE(r5) 110 ori r9,r9,MSR_FP /* enable FP for current */ 111 or r9,r9,r4 112#else 113 ld r4,PACACURRENT(r13) 114 addi r5,r4,THREAD /* Get THREAD */ 115 lwz r4,THREAD_FPEXC_MODE(r5) 116 ori r12,r12,MSR_FP 117 or r12,r12,r4 118 std r12,_MSR(r1) 119#endif 120 /* Don't care if r4 overflows, this is desired behaviour */ 121 lbz r4,THREAD_LOAD_FP(r5) 122 addi r4,r4,1 123 stb r4,THREAD_LOAD_FP(r5) 124 addi r10,r5,THREAD_FPSTATE 125 lfd fr0,FPSTATE_FPSCR(r10) 126 MTFSF_L(fr0) 127 REST_32FPVSRS(0, R4, R10) 128 /* restore registers and return */ 129 /* we haven't used ctr or xer or lr */ 130 blr 131 132/* 133 * save_fpu(tsk) 134 * Save the floating-point registers in its thread_struct. 135 * Enables the FPU for use in the kernel on return. 136 */ 137_GLOBAL(save_fpu) 138 addi r3,r3,THREAD /* want THREAD of task */ 139 PPC_LL r6,THREAD_FPSAVEAREA(r3) 140 PPC_LL r5,PT_REGS(r3) 141 PPC_LCMPI 0,r6,0 142 bne 2f 143 addi r6,r3,THREAD_FPSTATE 1442: SAVE_32FPVSRS(0, R4, R6) 145 mffs fr0 146 stfd fr0,FPSTATE_FPSCR(r6) 147 REST_1FPVSR(0, R4, R6) 148 blr 149 150/* 151 * These are used in the alignment trap handler when emulating 152 * single-precision loads and stores. 153 */ 154 155_GLOBAL(cvt_fd) 156 lfs 0,0(r3) 157 stfd 0,0(r4) 158 blr 159 160_GLOBAL(cvt_df) 161 lfd 0,0(r3) 162 stfs 0,0(r4) 163 blr 164