1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/device.h>
3 #include <linux/cpu.h>
4 #include <linux/smp.h>
5 #include <linux/percpu.h>
6 #include <linux/init.h>
7 #include <linux/sched.h>
8 #include <linux/export.h>
9 #include <linux/nodemask.h>
10 #include <linux/cpumask.h>
11 #include <linux/notifier.h>
12
13 #include <asm/current.h>
14 #include <asm/processor.h>
15 #include <asm/cputable.h>
16 #include <asm/hvcall.h>
17 #include <asm/prom.h>
18 #include <asm/machdep.h>
19 #include <asm/smp.h>
20 #include <asm/pmc.h>
21 #include <asm/firmware.h>
22 #include <asm/svm.h>
23
24 #include "cacheinfo.h"
25 #include "setup.h"
26
27 #ifdef CONFIG_PPC64
28 #include <asm/paca.h>
29 #include <asm/lppaca.h>
30 #endif
31
32 static DEFINE_PER_CPU(struct cpu, cpu_devices);
33
34 #ifdef CONFIG_PPC64
35
36 /*
37 * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
38 * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
39 * 2014:
40 *
41 * "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
42 * up the kernel code."
43 *
44 * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
45 * code should be removed.
46 */
47
store_smt_snooze_delay(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)48 static ssize_t store_smt_snooze_delay(struct device *dev,
49 struct device_attribute *attr,
50 const char *buf,
51 size_t count)
52 {
53 pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
54 current->comm, current->pid);
55 return count;
56 }
57
show_smt_snooze_delay(struct device * dev,struct device_attribute * attr,char * buf)58 static ssize_t show_smt_snooze_delay(struct device *dev,
59 struct device_attribute *attr,
60 char *buf)
61 {
62 pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
63 current->comm, current->pid);
64 return sprintf(buf, "100\n");
65 }
66
67 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
68 store_smt_snooze_delay);
69
setup_smt_snooze_delay(char * str)70 static int __init setup_smt_snooze_delay(char *str)
71 {
72 if (!cpu_has_feature(CPU_FTR_SMT))
73 return 1;
74
75 pr_warn("smt-snooze-delay command line option has no effect\n");
76 return 1;
77 }
78 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
79
80 #endif /* CONFIG_PPC64 */
81
82 #ifdef CONFIG_PPC_FSL_BOOK3E
83 #define MAX_BIT 63
84
85 static u64 pw20_wt;
86 static u64 altivec_idle_wt;
87
get_idle_ticks_bit(u64 ns)88 static unsigned int get_idle_ticks_bit(u64 ns)
89 {
90 u64 cycle;
91
92 if (ns >= 10000)
93 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
94 else
95 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
96
97 if (!cycle)
98 return 0;
99
100 return ilog2(cycle);
101 }
102
do_show_pwrmgtcr0(void * val)103 static void do_show_pwrmgtcr0(void *val)
104 {
105 u32 *value = val;
106
107 *value = mfspr(SPRN_PWRMGTCR0);
108 }
109
show_pw20_state(struct device * dev,struct device_attribute * attr,char * buf)110 static ssize_t show_pw20_state(struct device *dev,
111 struct device_attribute *attr, char *buf)
112 {
113 u32 value;
114 unsigned int cpu = dev->id;
115
116 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
117
118 value &= PWRMGTCR0_PW20_WAIT;
119
120 return sprintf(buf, "%u\n", value ? 1 : 0);
121 }
122
do_store_pw20_state(void * val)123 static void do_store_pw20_state(void *val)
124 {
125 u32 *value = val;
126 u32 pw20_state;
127
128 pw20_state = mfspr(SPRN_PWRMGTCR0);
129
130 if (*value)
131 pw20_state |= PWRMGTCR0_PW20_WAIT;
132 else
133 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
134
135 mtspr(SPRN_PWRMGTCR0, pw20_state);
136 }
137
store_pw20_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)138 static ssize_t store_pw20_state(struct device *dev,
139 struct device_attribute *attr,
140 const char *buf, size_t count)
141 {
142 u32 value;
143 unsigned int cpu = dev->id;
144
145 if (kstrtou32(buf, 0, &value))
146 return -EINVAL;
147
148 if (value > 1)
149 return -EINVAL;
150
151 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
152
153 return count;
154 }
155
show_pw20_wait_time(struct device * dev,struct device_attribute * attr,char * buf)156 static ssize_t show_pw20_wait_time(struct device *dev,
157 struct device_attribute *attr, char *buf)
158 {
159 u32 value;
160 u64 tb_cycle = 1;
161 u64 time;
162
163 unsigned int cpu = dev->id;
164
165 if (!pw20_wt) {
166 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
167 value = (value & PWRMGTCR0_PW20_ENT) >>
168 PWRMGTCR0_PW20_ENT_SHIFT;
169
170 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
171 /* convert ms to ns */
172 if (tb_ticks_per_usec > 1000) {
173 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
174 } else {
175 u32 rem_us;
176
177 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
178 &rem_us);
179 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
180 }
181 } else {
182 time = pw20_wt;
183 }
184
185 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
186 }
187
set_pw20_wait_entry_bit(void * val)188 static void set_pw20_wait_entry_bit(void *val)
189 {
190 u32 *value = val;
191 u32 pw20_idle;
192
193 pw20_idle = mfspr(SPRN_PWRMGTCR0);
194
195 /* Set Automatic PW20 Core Idle Count */
196 /* clear count */
197 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
198
199 /* set count */
200 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
201
202 mtspr(SPRN_PWRMGTCR0, pw20_idle);
203 }
204
store_pw20_wait_time(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)205 static ssize_t store_pw20_wait_time(struct device *dev,
206 struct device_attribute *attr,
207 const char *buf, size_t count)
208 {
209 u32 entry_bit;
210 u64 value;
211
212 unsigned int cpu = dev->id;
213
214 if (kstrtou64(buf, 0, &value))
215 return -EINVAL;
216
217 if (!value)
218 return -EINVAL;
219
220 entry_bit = get_idle_ticks_bit(value);
221 if (entry_bit > MAX_BIT)
222 return -EINVAL;
223
224 pw20_wt = value;
225
226 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
227 &entry_bit, 1);
228
229 return count;
230 }
231
show_altivec_idle(struct device * dev,struct device_attribute * attr,char * buf)232 static ssize_t show_altivec_idle(struct device *dev,
233 struct device_attribute *attr, char *buf)
234 {
235 u32 value;
236 unsigned int cpu = dev->id;
237
238 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
239
240 value &= PWRMGTCR0_AV_IDLE_PD_EN;
241
242 return sprintf(buf, "%u\n", value ? 1 : 0);
243 }
244
do_store_altivec_idle(void * val)245 static void do_store_altivec_idle(void *val)
246 {
247 u32 *value = val;
248 u32 altivec_idle;
249
250 altivec_idle = mfspr(SPRN_PWRMGTCR0);
251
252 if (*value)
253 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
254 else
255 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
256
257 mtspr(SPRN_PWRMGTCR0, altivec_idle);
258 }
259
store_altivec_idle(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)260 static ssize_t store_altivec_idle(struct device *dev,
261 struct device_attribute *attr,
262 const char *buf, size_t count)
263 {
264 u32 value;
265 unsigned int cpu = dev->id;
266
267 if (kstrtou32(buf, 0, &value))
268 return -EINVAL;
269
270 if (value > 1)
271 return -EINVAL;
272
273 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
274
275 return count;
276 }
277
show_altivec_idle_wait_time(struct device * dev,struct device_attribute * attr,char * buf)278 static ssize_t show_altivec_idle_wait_time(struct device *dev,
279 struct device_attribute *attr, char *buf)
280 {
281 u32 value;
282 u64 tb_cycle = 1;
283 u64 time;
284
285 unsigned int cpu = dev->id;
286
287 if (!altivec_idle_wt) {
288 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
289 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
290 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
291
292 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
293 /* convert ms to ns */
294 if (tb_ticks_per_usec > 1000) {
295 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
296 } else {
297 u32 rem_us;
298
299 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
300 &rem_us);
301 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
302 }
303 } else {
304 time = altivec_idle_wt;
305 }
306
307 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
308 }
309
set_altivec_idle_wait_entry_bit(void * val)310 static void set_altivec_idle_wait_entry_bit(void *val)
311 {
312 u32 *value = val;
313 u32 altivec_idle;
314
315 altivec_idle = mfspr(SPRN_PWRMGTCR0);
316
317 /* Set Automatic AltiVec Idle Count */
318 /* clear count */
319 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
320
321 /* set count */
322 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
323
324 mtspr(SPRN_PWRMGTCR0, altivec_idle);
325 }
326
store_altivec_idle_wait_time(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)327 static ssize_t store_altivec_idle_wait_time(struct device *dev,
328 struct device_attribute *attr,
329 const char *buf, size_t count)
330 {
331 u32 entry_bit;
332 u64 value;
333
334 unsigned int cpu = dev->id;
335
336 if (kstrtou64(buf, 0, &value))
337 return -EINVAL;
338
339 if (!value)
340 return -EINVAL;
341
342 entry_bit = get_idle_ticks_bit(value);
343 if (entry_bit > MAX_BIT)
344 return -EINVAL;
345
346 altivec_idle_wt = value;
347
348 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
349 &entry_bit, 1);
350
351 return count;
352 }
353
354 /*
355 * Enable/Disable interface:
356 * 0, disable. 1, enable.
357 */
358 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
359 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
360
361 /*
362 * Set wait time interface:(Nanosecond)
363 * Example: Base on TBfreq is 41MHZ.
364 * 1~48(ns): TB[63]
365 * 49~97(ns): TB[62]
366 * 98~195(ns): TB[61]
367 * 196~390(ns): TB[60]
368 * 391~780(ns): TB[59]
369 * 781~1560(ns): TB[58]
370 * ...
371 */
372 static DEVICE_ATTR(pw20_wait_time, 0600,
373 show_pw20_wait_time,
374 store_pw20_wait_time);
375 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
376 show_altivec_idle_wait_time,
377 store_altivec_idle_wait_time);
378 #endif
379
380 /*
381 * Enabling PMCs will slow partition context switch times so we only do
382 * it the first time we write to the PMCs.
383 */
384
385 static DEFINE_PER_CPU(char, pmcs_enabled);
386
ppc_enable_pmcs(void)387 void ppc_enable_pmcs(void)
388 {
389 ppc_set_pmu_inuse(1);
390
391 /* Only need to enable them once */
392 if (__this_cpu_read(pmcs_enabled))
393 return;
394
395 __this_cpu_write(pmcs_enabled, 1);
396
397 if (ppc_md.enable_pmcs)
398 ppc_md.enable_pmcs();
399 }
400 EXPORT_SYMBOL(ppc_enable_pmcs);
401
402 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
403 static void read_##NAME(void *val) \
404 { \
405 *(unsigned long *)val = mfspr(ADDRESS); \
406 } \
407 static void write_##NAME(void *val) \
408 { \
409 EXTRA; \
410 mtspr(ADDRESS, *(unsigned long *)val); \
411 }
412
413 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
414 static ssize_t show_##NAME(struct device *dev, \
415 struct device_attribute *attr, \
416 char *buf) \
417 { \
418 struct cpu *cpu = container_of(dev, struct cpu, dev); \
419 unsigned long val; \
420 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
421 return sprintf(buf, "%lx\n", val); \
422 } \
423 static ssize_t __used \
424 store_##NAME(struct device *dev, struct device_attribute *attr, \
425 const char *buf, size_t count) \
426 { \
427 struct cpu *cpu = container_of(dev, struct cpu, dev); \
428 unsigned long val; \
429 int ret = sscanf(buf, "%lx", &val); \
430 if (ret != 1) \
431 return -EINVAL; \
432 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
433 return count; \
434 }
435
436 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
437 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
438 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
439 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
440 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
441 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
442
443 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
444 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
445
446 /* Let's define all possible registers, we'll only hook up the ones
447 * that are implemented on the current processor
448 */
449
450 #if defined(CONFIG_PPC64)
451 #define HAS_PPC_PMC_CLASSIC 1
452 #define HAS_PPC_PMC_IBM 1
453 #define HAS_PPC_PMC_PA6T 1
454 #elif defined(CONFIG_PPC_BOOK3S_32)
455 #define HAS_PPC_PMC_CLASSIC 1
456 #define HAS_PPC_PMC_IBM 1
457 #define HAS_PPC_PMC_G4 1
458 #endif
459
460
461 #ifdef HAS_PPC_PMC_CLASSIC
462 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
463 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
464 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
465 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
466 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
467 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
468 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
469 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
470
471 #ifdef HAS_PPC_PMC_G4
472 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
473 #endif
474
475 #ifdef CONFIG_PPC64
476 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
477 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
478
479 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
480 SYSFS_SPRSETUP(purr, SPRN_PURR);
481 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
482 SYSFS_SPRSETUP(pir, SPRN_PIR);
483 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
484
485 /*
486 Lets only enable read for phyp resources and
487 enable write when needed with a separate function.
488 Lets be conservative and default to pseries.
489 */
490 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
491 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
492 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
493 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
494 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
495
496 /*
497 * This is the system wide DSCR register default value. Any
498 * change to this default value through the sysfs interface
499 * will update all per cpu DSCR default values across the
500 * system stored in their respective PACA structures.
501 */
502 static unsigned long dscr_default;
503
504 /**
505 * read_dscr() - Fetch the cpu specific DSCR default
506 * @val: Returned cpu specific DSCR default value
507 *
508 * This function returns the per cpu DSCR default value
509 * for any cpu which is contained in it's PACA structure.
510 */
read_dscr(void * val)511 static void read_dscr(void *val)
512 {
513 *(unsigned long *)val = get_paca()->dscr_default;
514 }
515
516
517 /**
518 * write_dscr() - Update the cpu specific DSCR default
519 * @val: New cpu specific DSCR default value to update
520 *
521 * This function updates the per cpu DSCR default value
522 * for any cpu which is contained in it's PACA structure.
523 */
write_dscr(void * val)524 static void write_dscr(void *val)
525 {
526 get_paca()->dscr_default = *(unsigned long *)val;
527 if (!current->thread.dscr_inherit) {
528 current->thread.dscr = *(unsigned long *)val;
529 mtspr(SPRN_DSCR, *(unsigned long *)val);
530 }
531 }
532
533 SYSFS_SPRSETUP_SHOW_STORE(dscr);
534 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
535
add_write_permission_dev_attr(struct device_attribute * attr)536 static void add_write_permission_dev_attr(struct device_attribute *attr)
537 {
538 attr->attr.mode |= 0200;
539 }
540
541 /**
542 * show_dscr_default() - Fetch the system wide DSCR default
543 * @dev: Device structure
544 * @attr: Device attribute structure
545 * @buf: Interface buffer
546 *
547 * This function returns the system wide DSCR default value.
548 */
show_dscr_default(struct device * dev,struct device_attribute * attr,char * buf)549 static ssize_t show_dscr_default(struct device *dev,
550 struct device_attribute *attr, char *buf)
551 {
552 return sprintf(buf, "%lx\n", dscr_default);
553 }
554
555 /**
556 * store_dscr_default() - Update the system wide DSCR default
557 * @dev: Device structure
558 * @attr: Device attribute structure
559 * @buf: Interface buffer
560 * @count: Size of the update
561 *
562 * This function updates the system wide DSCR default value.
563 */
store_dscr_default(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)564 static ssize_t __used store_dscr_default(struct device *dev,
565 struct device_attribute *attr, const char *buf,
566 size_t count)
567 {
568 unsigned long val;
569 int ret = 0;
570
571 ret = sscanf(buf, "%lx", &val);
572 if (ret != 1)
573 return -EINVAL;
574 dscr_default = val;
575
576 on_each_cpu(write_dscr, &val, 1);
577
578 return count;
579 }
580
581 static DEVICE_ATTR(dscr_default, 0600,
582 show_dscr_default, store_dscr_default);
583
sysfs_create_dscr_default(void)584 static void sysfs_create_dscr_default(void)
585 {
586 if (cpu_has_feature(CPU_FTR_DSCR)) {
587 int err = 0;
588 int cpu;
589
590 dscr_default = spr_default_dscr;
591 for_each_possible_cpu(cpu)
592 paca_ptrs[cpu]->dscr_default = dscr_default;
593
594 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
595 }
596 }
597
598 #endif /* CONFIG_PPC64 */
599
600 #ifdef HAS_PPC_PMC_PA6T
601 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
602 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
603 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
604 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
605 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
606 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
607 #ifdef CONFIG_DEBUG_MISC
608 SYSFS_SPRSETUP(hid0, SPRN_HID0);
609 SYSFS_SPRSETUP(hid1, SPRN_HID1);
610 SYSFS_SPRSETUP(hid4, SPRN_HID4);
611 SYSFS_SPRSETUP(hid5, SPRN_HID5);
612 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
613 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
614 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
615 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
616 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
617 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
618 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
619 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
620 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
621 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
622 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
623 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
624 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
625 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
626 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
627 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
628 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
629 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
630 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
631 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
632 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
633 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
634 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
635 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
636 #endif /* CONFIG_DEBUG_MISC */
637 #endif /* HAS_PPC_PMC_PA6T */
638
639 #ifdef HAS_PPC_PMC_IBM
640 static struct device_attribute ibm_common_attrs[] = {
641 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
642 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
643 };
644 #endif /* HAS_PPC_PMC_G4 */
645
646 #ifdef HAS_PPC_PMC_G4
647 static struct device_attribute g4_common_attrs[] = {
648 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
649 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
650 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
651 };
652 #endif /* HAS_PPC_PMC_G4 */
653
654 static struct device_attribute classic_pmc_attrs[] = {
655 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
656 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
657 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
658 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
659 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
660 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
661 #ifdef CONFIG_PPC64
662 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
663 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
664 #endif
665 };
666
667 #ifdef HAS_PPC_PMC_PA6T
668 static struct device_attribute pa6t_attrs[] = {
669 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
670 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
671 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
672 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
673 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
674 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
675 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
676 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
677 #ifdef CONFIG_DEBUG_MISC
678 __ATTR(hid0, 0600, show_hid0, store_hid0),
679 __ATTR(hid1, 0600, show_hid1, store_hid1),
680 __ATTR(hid4, 0600, show_hid4, store_hid4),
681 __ATTR(hid5, 0600, show_hid5, store_hid5),
682 __ATTR(ima0, 0600, show_ima0, store_ima0),
683 __ATTR(ima1, 0600, show_ima1, store_ima1),
684 __ATTR(ima2, 0600, show_ima2, store_ima2),
685 __ATTR(ima3, 0600, show_ima3, store_ima3),
686 __ATTR(ima4, 0600, show_ima4, store_ima4),
687 __ATTR(ima5, 0600, show_ima5, store_ima5),
688 __ATTR(ima6, 0600, show_ima6, store_ima6),
689 __ATTR(ima7, 0600, show_ima7, store_ima7),
690 __ATTR(ima8, 0600, show_ima8, store_ima8),
691 __ATTR(ima9, 0600, show_ima9, store_ima9),
692 __ATTR(imaat, 0600, show_imaat, store_imaat),
693 __ATTR(btcr, 0600, show_btcr, store_btcr),
694 __ATTR(pccr, 0600, show_pccr, store_pccr),
695 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
696 __ATTR(der, 0600, show_der, store_der),
697 __ATTR(mer, 0600, show_mer, store_mer),
698 __ATTR(ber, 0600, show_ber, store_ber),
699 __ATTR(ier, 0600, show_ier, store_ier),
700 __ATTR(sier, 0600, show_sier, store_sier),
701 __ATTR(siar, 0600, show_siar, store_siar),
702 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
703 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
704 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
705 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
706 #endif /* CONFIG_DEBUG_MISC */
707 };
708 #endif /* HAS_PPC_PMC_PA6T */
709 #endif /* HAS_PPC_PMC_CLASSIC */
710
711 #ifdef CONFIG_PPC_SVM
show_svm(struct device * dev,struct device_attribute * attr,char * buf)712 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
713 {
714 return sprintf(buf, "%u\n", is_secure_guest());
715 }
716 static DEVICE_ATTR(svm, 0444, show_svm, NULL);
717
create_svm_file(void)718 static void create_svm_file(void)
719 {
720 device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
721 }
722 #else
create_svm_file(void)723 static void create_svm_file(void)
724 {
725 }
726 #endif /* CONFIG_PPC_SVM */
727
register_cpu_online(unsigned int cpu)728 static int register_cpu_online(unsigned int cpu)
729 {
730 struct cpu *c = &per_cpu(cpu_devices, cpu);
731 struct device *s = &c->dev;
732 struct device_attribute *attrs, *pmc_attrs;
733 int i, nattrs;
734
735 /* For cpus present at boot a reference was already grabbed in register_cpu() */
736 if (!s->of_node)
737 s->of_node = of_get_cpu_node(cpu, NULL);
738
739 #ifdef CONFIG_PPC64
740 if (cpu_has_feature(CPU_FTR_SMT))
741 device_create_file(s, &dev_attr_smt_snooze_delay);
742 #endif
743
744 /* PMC stuff */
745 switch (cur_cpu_spec->pmc_type) {
746 #ifdef HAS_PPC_PMC_IBM
747 case PPC_PMC_IBM:
748 attrs = ibm_common_attrs;
749 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
750 pmc_attrs = classic_pmc_attrs;
751 break;
752 #endif /* HAS_PPC_PMC_IBM */
753 #ifdef HAS_PPC_PMC_G4
754 case PPC_PMC_G4:
755 attrs = g4_common_attrs;
756 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
757 pmc_attrs = classic_pmc_attrs;
758 break;
759 #endif /* HAS_PPC_PMC_G4 */
760 #ifdef HAS_PPC_PMC_PA6T
761 case PPC_PMC_PA6T:
762 /* PA Semi starts counting at PMC0 */
763 attrs = pa6t_attrs;
764 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
765 pmc_attrs = NULL;
766 break;
767 #endif /* HAS_PPC_PMC_PA6T */
768 default:
769 attrs = NULL;
770 nattrs = 0;
771 pmc_attrs = NULL;
772 }
773
774 for (i = 0; i < nattrs; i++)
775 device_create_file(s, &attrs[i]);
776
777 if (pmc_attrs)
778 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
779 device_create_file(s, &pmc_attrs[i]);
780
781 #ifdef CONFIG_PPC64
782 if (cpu_has_feature(CPU_FTR_MMCRA))
783 device_create_file(s, &dev_attr_mmcra);
784
785 if (cpu_has_feature(CPU_FTR_PURR)) {
786 if (!firmware_has_feature(FW_FEATURE_LPAR))
787 add_write_permission_dev_attr(&dev_attr_purr);
788 device_create_file(s, &dev_attr_purr);
789 }
790
791 if (cpu_has_feature(CPU_FTR_SPURR))
792 device_create_file(s, &dev_attr_spurr);
793
794 if (cpu_has_feature(CPU_FTR_DSCR))
795 device_create_file(s, &dev_attr_dscr);
796
797 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
798 device_create_file(s, &dev_attr_pir);
799
800 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
801 !firmware_has_feature(FW_FEATURE_LPAR))
802 device_create_file(s, &dev_attr_tscr);
803 #endif /* CONFIG_PPC64 */
804
805 #ifdef CONFIG_PPC_FSL_BOOK3E
806 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
807 device_create_file(s, &dev_attr_pw20_state);
808 device_create_file(s, &dev_attr_pw20_wait_time);
809
810 device_create_file(s, &dev_attr_altivec_idle);
811 device_create_file(s, &dev_attr_altivec_idle_wait_time);
812 }
813 #endif
814 cacheinfo_cpu_online(cpu);
815 return 0;
816 }
817
818 #ifdef CONFIG_HOTPLUG_CPU
unregister_cpu_online(unsigned int cpu)819 static int unregister_cpu_online(unsigned int cpu)
820 {
821 struct cpu *c = &per_cpu(cpu_devices, cpu);
822 struct device *s = &c->dev;
823 struct device_attribute *attrs, *pmc_attrs;
824 int i, nattrs;
825
826 BUG_ON(!c->hotpluggable);
827
828 #ifdef CONFIG_PPC64
829 if (cpu_has_feature(CPU_FTR_SMT))
830 device_remove_file(s, &dev_attr_smt_snooze_delay);
831 #endif
832
833 /* PMC stuff */
834 switch (cur_cpu_spec->pmc_type) {
835 #ifdef HAS_PPC_PMC_IBM
836 case PPC_PMC_IBM:
837 attrs = ibm_common_attrs;
838 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
839 pmc_attrs = classic_pmc_attrs;
840 break;
841 #endif /* HAS_PPC_PMC_IBM */
842 #ifdef HAS_PPC_PMC_G4
843 case PPC_PMC_G4:
844 attrs = g4_common_attrs;
845 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
846 pmc_attrs = classic_pmc_attrs;
847 break;
848 #endif /* HAS_PPC_PMC_G4 */
849 #ifdef HAS_PPC_PMC_PA6T
850 case PPC_PMC_PA6T:
851 /* PA Semi starts counting at PMC0 */
852 attrs = pa6t_attrs;
853 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
854 pmc_attrs = NULL;
855 break;
856 #endif /* HAS_PPC_PMC_PA6T */
857 default:
858 attrs = NULL;
859 nattrs = 0;
860 pmc_attrs = NULL;
861 }
862
863 for (i = 0; i < nattrs; i++)
864 device_remove_file(s, &attrs[i]);
865
866 if (pmc_attrs)
867 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
868 device_remove_file(s, &pmc_attrs[i]);
869
870 #ifdef CONFIG_PPC64
871 if (cpu_has_feature(CPU_FTR_MMCRA))
872 device_remove_file(s, &dev_attr_mmcra);
873
874 if (cpu_has_feature(CPU_FTR_PURR))
875 device_remove_file(s, &dev_attr_purr);
876
877 if (cpu_has_feature(CPU_FTR_SPURR))
878 device_remove_file(s, &dev_attr_spurr);
879
880 if (cpu_has_feature(CPU_FTR_DSCR))
881 device_remove_file(s, &dev_attr_dscr);
882
883 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
884 device_remove_file(s, &dev_attr_pir);
885
886 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
887 !firmware_has_feature(FW_FEATURE_LPAR))
888 device_remove_file(s, &dev_attr_tscr);
889 #endif /* CONFIG_PPC64 */
890
891 #ifdef CONFIG_PPC_FSL_BOOK3E
892 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
893 device_remove_file(s, &dev_attr_pw20_state);
894 device_remove_file(s, &dev_attr_pw20_wait_time);
895
896 device_remove_file(s, &dev_attr_altivec_idle);
897 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
898 }
899 #endif
900 cacheinfo_cpu_offline(cpu);
901 of_node_put(s->of_node);
902 s->of_node = NULL;
903 return 0;
904 }
905 #else /* !CONFIG_HOTPLUG_CPU */
906 #define unregister_cpu_online NULL
907 #endif
908
909 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
arch_cpu_probe(const char * buf,size_t count)910 ssize_t arch_cpu_probe(const char *buf, size_t count)
911 {
912 if (ppc_md.cpu_probe)
913 return ppc_md.cpu_probe(buf, count);
914
915 return -EINVAL;
916 }
917
arch_cpu_release(const char * buf,size_t count)918 ssize_t arch_cpu_release(const char *buf, size_t count)
919 {
920 if (ppc_md.cpu_release)
921 return ppc_md.cpu_release(buf, count);
922
923 return -EINVAL;
924 }
925 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
926
927 static DEFINE_MUTEX(cpu_mutex);
928
cpu_add_dev_attr(struct device_attribute * attr)929 int cpu_add_dev_attr(struct device_attribute *attr)
930 {
931 int cpu;
932
933 mutex_lock(&cpu_mutex);
934
935 for_each_possible_cpu(cpu) {
936 device_create_file(get_cpu_device(cpu), attr);
937 }
938
939 mutex_unlock(&cpu_mutex);
940 return 0;
941 }
942 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
943
cpu_add_dev_attr_group(struct attribute_group * attrs)944 int cpu_add_dev_attr_group(struct attribute_group *attrs)
945 {
946 int cpu;
947 struct device *dev;
948 int ret;
949
950 mutex_lock(&cpu_mutex);
951
952 for_each_possible_cpu(cpu) {
953 dev = get_cpu_device(cpu);
954 ret = sysfs_create_group(&dev->kobj, attrs);
955 WARN_ON(ret != 0);
956 }
957
958 mutex_unlock(&cpu_mutex);
959 return 0;
960 }
961 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
962
963
cpu_remove_dev_attr(struct device_attribute * attr)964 void cpu_remove_dev_attr(struct device_attribute *attr)
965 {
966 int cpu;
967
968 mutex_lock(&cpu_mutex);
969
970 for_each_possible_cpu(cpu) {
971 device_remove_file(get_cpu_device(cpu), attr);
972 }
973
974 mutex_unlock(&cpu_mutex);
975 }
976 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
977
cpu_remove_dev_attr_group(struct attribute_group * attrs)978 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
979 {
980 int cpu;
981 struct device *dev;
982
983 mutex_lock(&cpu_mutex);
984
985 for_each_possible_cpu(cpu) {
986 dev = get_cpu_device(cpu);
987 sysfs_remove_group(&dev->kobj, attrs);
988 }
989
990 mutex_unlock(&cpu_mutex);
991 }
992 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
993
994
995 /* NUMA stuff */
996
997 #ifdef CONFIG_NUMA
register_nodes(void)998 static void register_nodes(void)
999 {
1000 int i;
1001
1002 for (i = 0; i < MAX_NUMNODES; i++)
1003 register_one_node(i);
1004 }
1005
sysfs_add_device_to_node(struct device * dev,int nid)1006 int sysfs_add_device_to_node(struct device *dev, int nid)
1007 {
1008 struct node *node = node_devices[nid];
1009 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1010 kobject_name(&dev->kobj));
1011 }
1012 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1013
sysfs_remove_device_from_node(struct device * dev,int nid)1014 void sysfs_remove_device_from_node(struct device *dev, int nid)
1015 {
1016 struct node *node = node_devices[nid];
1017 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1018 }
1019 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1020
1021 #else
register_nodes(void)1022 static void register_nodes(void)
1023 {
1024 return;
1025 }
1026
1027 #endif
1028
1029 /* Only valid if CPU is present. */
show_physical_id(struct device * dev,struct device_attribute * attr,char * buf)1030 static ssize_t show_physical_id(struct device *dev,
1031 struct device_attribute *attr, char *buf)
1032 {
1033 struct cpu *cpu = container_of(dev, struct cpu, dev);
1034
1035 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1036 }
1037 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1038
topology_init(void)1039 static int __init topology_init(void)
1040 {
1041 int cpu, r;
1042
1043 register_nodes();
1044
1045 for_each_possible_cpu(cpu) {
1046 struct cpu *c = &per_cpu(cpu_devices, cpu);
1047
1048 /*
1049 * For now, we just see if the system supports making
1050 * the RTAS calls for CPU hotplug. But, there may be a
1051 * more comprehensive way to do this for an individual
1052 * CPU. For instance, the boot cpu might never be valid
1053 * for hotplugging.
1054 */
1055 if (ppc_md.cpu_die)
1056 c->hotpluggable = 1;
1057
1058 if (cpu_online(cpu) || c->hotpluggable) {
1059 register_cpu(c, cpu);
1060
1061 device_create_file(&c->dev, &dev_attr_physical_id);
1062 }
1063 }
1064 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1065 register_cpu_online, unregister_cpu_online);
1066 WARN_ON(r < 0);
1067 #ifdef CONFIG_PPC64
1068 sysfs_create_dscr_default();
1069 #endif /* CONFIG_PPC64 */
1070
1071 create_svm_file();
1072
1073 return 0;
1074 }
1075 subsys_initcall(topology_init);
1076