1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
7 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
8 * Copyright (C) 1996 Paul Mackerras
9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
10 *
11 * Derived from "arch/i386/mm/init.c"
12 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
13 */
14
15 #include <linux/export.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/gfp.h>
21 #include <linux/types.h>
22 #include <linux/mm.h>
23 #include <linux/stddef.h>
24 #include <linux/init.h>
25 #include <linux/memblock.h>
26 #include <linux/highmem.h>
27 #include <linux/initrd.h>
28 #include <linux/pagemap.h>
29 #include <linux/suspend.h>
30 #include <linux/hugetlb.h>
31 #include <linux/slab.h>
32 #include <linux/vmalloc.h>
33 #include <linux/memremap.h>
34
35 #include <asm/pgalloc.h>
36 #include <asm/prom.h>
37 #include <asm/io.h>
38 #include <asm/mmu_context.h>
39 #include <asm/pgtable.h>
40 #include <asm/mmu.h>
41 #include <asm/smp.h>
42 #include <asm/machdep.h>
43 #include <asm/btext.h>
44 #include <asm/tlb.h>
45 #include <asm/sections.h>
46 #include <asm/sparsemem.h>
47 #include <asm/vdso.h>
48 #include <asm/fixmap.h>
49 #include <asm/swiotlb.h>
50 #include <asm/rtas.h>
51 #include <asm/ftrace.h>
52
53 #include <mm/mmu_decl.h>
54
55 #ifndef CPU_FTR_COHERENT_ICACHE
56 #define CPU_FTR_COHERENT_ICACHE 0 /* XXX for now */
57 #define CPU_FTR_NOEXECUTE 0
58 #endif
59
60 unsigned long long memory_limit;
61 bool init_mem_is_free;
62
63 #ifdef CONFIG_HIGHMEM
64 pte_t *kmap_pte;
65 EXPORT_SYMBOL(kmap_pte);
66 pgprot_t kmap_prot;
67 EXPORT_SYMBOL(kmap_prot);
68
virt_to_kpte(unsigned long vaddr)69 static inline pte_t *virt_to_kpte(unsigned long vaddr)
70 {
71 return pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr),
72 vaddr), vaddr), vaddr);
73 }
74 #endif
75
phys_mem_access_prot(struct file * file,unsigned long pfn,unsigned long size,pgprot_t vma_prot)76 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
77 unsigned long size, pgprot_t vma_prot)
78 {
79 if (ppc_md.phys_mem_access_prot)
80 return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
81
82 if (!page_is_ram(pfn))
83 vma_prot = pgprot_noncached(vma_prot);
84
85 return vma_prot;
86 }
87 EXPORT_SYMBOL(phys_mem_access_prot);
88
89 #ifdef CONFIG_MEMORY_HOTPLUG
90
91 #ifdef CONFIG_NUMA
memory_add_physaddr_to_nid(u64 start)92 int memory_add_physaddr_to_nid(u64 start)
93 {
94 return hot_add_scn_to_nid(start);
95 }
96 #endif
97
create_section_mapping(unsigned long start,unsigned long end,int nid)98 int __weak create_section_mapping(unsigned long start, unsigned long end, int nid)
99 {
100 return -ENODEV;
101 }
102
remove_section_mapping(unsigned long start,unsigned long end)103 int __weak remove_section_mapping(unsigned long start, unsigned long end)
104 {
105 return -ENODEV;
106 }
107
108 #define FLUSH_CHUNK_SIZE SZ_1G
109 /**
110 * flush_dcache_range_chunked(): Write any modified data cache blocks out to
111 * memory and invalidate them, in chunks of up to FLUSH_CHUNK_SIZE
112 * Does not invalidate the corresponding instruction cache blocks.
113 *
114 * @start: the start address
115 * @stop: the stop address (exclusive)
116 * @chunk: the max size of the chunks
117 */
flush_dcache_range_chunked(unsigned long start,unsigned long stop,unsigned long chunk)118 static void flush_dcache_range_chunked(unsigned long start, unsigned long stop,
119 unsigned long chunk)
120 {
121 unsigned long i;
122
123 for (i = start; i < stop; i += chunk) {
124 flush_dcache_range(i, min(stop, i + chunk));
125 cond_resched();
126 }
127 }
128
arch_add_memory(int nid,u64 start,u64 size,struct mhp_restrictions * restrictions)129 int __ref arch_add_memory(int nid, u64 start, u64 size,
130 struct mhp_restrictions *restrictions)
131 {
132 unsigned long start_pfn = start >> PAGE_SHIFT;
133 unsigned long nr_pages = size >> PAGE_SHIFT;
134 int rc;
135
136 resize_hpt_for_hotplug(memblock_phys_mem_size());
137
138 start = (unsigned long)__va(start);
139 rc = create_section_mapping(start, start + size, nid);
140 if (rc) {
141 pr_warn("Unable to create mapping for hot added memory 0x%llx..0x%llx: %d\n",
142 start, start + size, rc);
143 return -EFAULT;
144 }
145
146 flush_dcache_range_chunked(start, start + size, FLUSH_CHUNK_SIZE);
147
148 return __add_pages(nid, start_pfn, nr_pages, restrictions);
149 }
150
arch_remove_memory(int nid,u64 start,u64 size,struct vmem_altmap * altmap)151 void __ref arch_remove_memory(int nid, u64 start, u64 size,
152 struct vmem_altmap *altmap)
153 {
154 unsigned long start_pfn = start >> PAGE_SHIFT;
155 unsigned long nr_pages = size >> PAGE_SHIFT;
156 int ret;
157
158 __remove_pages(start_pfn, nr_pages, altmap);
159
160 /* Remove htab bolted mappings for this section of memory */
161 start = (unsigned long)__va(start);
162 flush_dcache_range_chunked(start, start + size, FLUSH_CHUNK_SIZE);
163
164 ret = remove_section_mapping(start, start + size);
165 WARN_ON_ONCE(ret);
166
167 /* Ensure all vmalloc mappings are flushed in case they also
168 * hit that section of memory
169 */
170 vm_unmap_aliases();
171
172 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC)
173 pr_warn("Hash collision while resizing HPT\n");
174 }
175 #endif
176
177 #ifndef CONFIG_NEED_MULTIPLE_NODES
mem_topology_setup(void)178 void __init mem_topology_setup(void)
179 {
180 max_low_pfn = max_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
181 min_low_pfn = MEMORY_START >> PAGE_SHIFT;
182 #ifdef CONFIG_HIGHMEM
183 max_low_pfn = lowmem_end_addr >> PAGE_SHIFT;
184 #endif
185
186 /* Place all memblock_regions in the same node and merge contiguous
187 * memblock_regions
188 */
189 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
190 }
191
initmem_init(void)192 void __init initmem_init(void)
193 {
194 /* XXX need to clip this if using highmem? */
195 sparse_memory_present_with_active_regions(0);
196 sparse_init();
197 }
198
199 /* mark pages that don't exist as nosave */
mark_nonram_nosave(void)200 static int __init mark_nonram_nosave(void)
201 {
202 struct memblock_region *reg, *prev = NULL;
203
204 for_each_memblock(memory, reg) {
205 if (prev &&
206 memblock_region_memory_end_pfn(prev) < memblock_region_memory_base_pfn(reg))
207 register_nosave_region(memblock_region_memory_end_pfn(prev),
208 memblock_region_memory_base_pfn(reg));
209 prev = reg;
210 }
211 return 0;
212 }
213 #else /* CONFIG_NEED_MULTIPLE_NODES */
mark_nonram_nosave(void)214 static int __init mark_nonram_nosave(void)
215 {
216 return 0;
217 }
218 #endif
219
220 /*
221 * Zones usage:
222 *
223 * We setup ZONE_DMA to be 31-bits on all platforms and ZONE_NORMAL to be
224 * everything else. GFP_DMA32 page allocations automatically fall back to
225 * ZONE_DMA.
226 *
227 * By using 31-bit unconditionally, we can exploit ARCH_ZONE_DMA_BITS to
228 * inform the generic DMA mapping code. 32-bit only devices (if not handled
229 * by an IOMMU anyway) will take a first dip into ZONE_NORMAL and get
230 * otherwise served by ZONE_DMA.
231 */
232 static unsigned long max_zone_pfns[MAX_NR_ZONES];
233
234 /*
235 * paging_init() sets up the page tables - in fact we've already done this.
236 */
paging_init(void)237 void __init paging_init(void)
238 {
239 unsigned long long total_ram = memblock_phys_mem_size();
240 phys_addr_t top_of_ram = memblock_end_of_DRAM();
241
242 #ifdef CONFIG_PPC32
243 unsigned long v = __fix_to_virt(__end_of_fixed_addresses - 1);
244 unsigned long end = __fix_to_virt(FIX_HOLE);
245
246 for (; v < end; v += PAGE_SIZE)
247 map_kernel_page(v, 0, __pgprot(0)); /* XXX gross */
248 #endif
249
250 #ifdef CONFIG_HIGHMEM
251 map_kernel_page(PKMAP_BASE, 0, __pgprot(0)); /* XXX gross */
252 pkmap_page_table = virt_to_kpte(PKMAP_BASE);
253
254 kmap_pte = virt_to_kpte(__fix_to_virt(FIX_KMAP_BEGIN));
255 kmap_prot = PAGE_KERNEL;
256 #endif /* CONFIG_HIGHMEM */
257
258 printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%llx\n",
259 (unsigned long long)top_of_ram, total_ram);
260 printk(KERN_DEBUG "Memory hole size: %ldMB\n",
261 (long int)((top_of_ram - total_ram) >> 20));
262
263 #ifdef CONFIG_ZONE_DMA
264 max_zone_pfns[ZONE_DMA] = min(max_low_pfn,
265 1UL << (ARCH_ZONE_DMA_BITS - PAGE_SHIFT));
266 #endif
267 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
268 #ifdef CONFIG_HIGHMEM
269 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
270 #endif
271
272 free_area_init_nodes(max_zone_pfns);
273
274 mark_nonram_nosave();
275 }
276
mem_init(void)277 void __init mem_init(void)
278 {
279 /*
280 * book3s is limited to 16 page sizes due to encoding this in
281 * a 4-bit field for slices.
282 */
283 BUILD_BUG_ON(MMU_PAGE_COUNT > 16);
284
285 #ifdef CONFIG_SWIOTLB
286 /*
287 * Some platforms (e.g. 85xx) limit DMA-able memory way below
288 * 4G. We force memblock to bottom-up mode to ensure that the
289 * memory allocated in swiotlb_init() is DMA-able.
290 * As it's the last memblock allocation, no need to reset it
291 * back to to-down.
292 */
293 memblock_set_bottom_up(true);
294 swiotlb_init(0);
295 #endif
296
297 high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
298 set_max_mapnr(max_pfn);
299 memblock_free_all();
300
301 #ifdef CONFIG_HIGHMEM
302 {
303 unsigned long pfn, highmem_mapnr;
304
305 highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
306 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
307 phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT;
308 struct page *page = pfn_to_page(pfn);
309 if (!memblock_is_reserved(paddr))
310 free_highmem_page(page);
311 }
312 }
313 #endif /* CONFIG_HIGHMEM */
314
315 #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP)
316 /*
317 * If smp is enabled, next_tlbcam_idx is initialized in the cpu up
318 * functions.... do it here for the non-smp case.
319 */
320 per_cpu(next_tlbcam_idx, smp_processor_id()) =
321 (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
322 #endif
323
324 mem_init_print_info(NULL);
325 #ifdef CONFIG_PPC32
326 pr_info("Kernel virtual memory layout:\n");
327 #ifdef CONFIG_KASAN
328 pr_info(" * 0x%08lx..0x%08lx : kasan shadow mem\n",
329 KASAN_SHADOW_START, KASAN_SHADOW_END);
330 #endif
331 pr_info(" * 0x%08lx..0x%08lx : fixmap\n", FIXADDR_START, FIXADDR_TOP);
332 #ifdef CONFIG_HIGHMEM
333 pr_info(" * 0x%08lx..0x%08lx : highmem PTEs\n",
334 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP));
335 #endif /* CONFIG_HIGHMEM */
336 if (ioremap_bot != IOREMAP_TOP)
337 pr_info(" * 0x%08lx..0x%08lx : early ioremap\n",
338 ioremap_bot, IOREMAP_TOP);
339 pr_info(" * 0x%08lx..0x%08lx : vmalloc & ioremap\n",
340 VMALLOC_START, VMALLOC_END);
341 #endif /* CONFIG_PPC32 */
342 }
343
free_initmem(void)344 void free_initmem(void)
345 {
346 ppc_md.progress = ppc_printk_progress;
347 mark_initmem_nx();
348 init_mem_is_free = true;
349 free_initmem_default(POISON_FREE_INITMEM);
350 ftrace_free_init_tramp();
351 }
352
353 /**
354 * flush_coherent_icache() - if a CPU has a coherent icache, flush it
355 * @addr: The base address to use (can be any valid address, the whole cache will be flushed)
356 * Return true if the cache was flushed, false otherwise
357 */
flush_coherent_icache(unsigned long addr)358 static inline bool flush_coherent_icache(unsigned long addr)
359 {
360 /*
361 * For a snooping icache, we still need a dummy icbi to purge all the
362 * prefetched instructions from the ifetch buffers. We also need a sync
363 * before the icbi to order the the actual stores to memory that might
364 * have modified instructions with the icbi.
365 */
366 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
367 mb(); /* sync */
368 allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
369 icbi((void *)addr);
370 prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
371 mb(); /* sync */
372 isync();
373 return true;
374 }
375
376 return false;
377 }
378
379 /**
380 * invalidate_icache_range() - Flush the icache by issuing icbi across an address range
381 * @start: the start address
382 * @stop: the stop address (exclusive)
383 */
invalidate_icache_range(unsigned long start,unsigned long stop)384 static void invalidate_icache_range(unsigned long start, unsigned long stop)
385 {
386 unsigned long shift = l1_icache_shift();
387 unsigned long bytes = l1_icache_bytes();
388 char *addr = (char *)(start & ~(bytes - 1));
389 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
390 unsigned long i;
391
392 for (i = 0; i < size >> shift; i++, addr += bytes)
393 icbi(addr);
394
395 mb(); /* sync */
396 isync();
397 }
398
399 /**
400 * flush_icache_range: Write any modified data cache blocks out to memory
401 * and invalidate the corresponding blocks in the instruction cache
402 *
403 * Generic code will call this after writing memory, before executing from it.
404 *
405 * @start: the start address
406 * @stop: the stop address (exclusive)
407 */
flush_icache_range(unsigned long start,unsigned long stop)408 void flush_icache_range(unsigned long start, unsigned long stop)
409 {
410 if (flush_coherent_icache(start))
411 return;
412
413 clean_dcache_range(start, stop);
414
415 if (IS_ENABLED(CONFIG_44x)) {
416 /*
417 * Flash invalidate on 44x because we are passed kmapped
418 * addresses and this doesn't work for userspace pages due to
419 * the virtually tagged icache.
420 */
421 iccci((void *)start);
422 mb(); /* sync */
423 isync();
424 } else
425 invalidate_icache_range(start, stop);
426 }
427 EXPORT_SYMBOL(flush_icache_range);
428
429 #if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
430 /**
431 * flush_dcache_icache_phys() - Flush a page by it's physical address
432 * @physaddr: the physical address of the page
433 */
flush_dcache_icache_phys(unsigned long physaddr)434 static void flush_dcache_icache_phys(unsigned long physaddr)
435 {
436 unsigned long bytes = l1_dcache_bytes();
437 unsigned long nb = PAGE_SIZE / bytes;
438 unsigned long addr = physaddr & PAGE_MASK;
439 unsigned long msr, msr0;
440 unsigned long loop1 = addr, loop2 = addr;
441
442 msr0 = mfmsr();
443 msr = msr0 & ~MSR_DR;
444 /*
445 * This must remain as ASM to prevent potential memory accesses
446 * while the data MMU is disabled
447 */
448 asm volatile(
449 " mtctr %2;\n"
450 " mtmsr %3;\n"
451 " isync;\n"
452 "0: dcbst 0, %0;\n"
453 " addi %0, %0, %4;\n"
454 " bdnz 0b;\n"
455 " sync;\n"
456 " mtctr %2;\n"
457 "1: icbi 0, %1;\n"
458 " addi %1, %1, %4;\n"
459 " bdnz 1b;\n"
460 " sync;\n"
461 " mtmsr %5;\n"
462 " isync;\n"
463 : "+&r" (loop1), "+&r" (loop2)
464 : "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
465 : "ctr", "memory");
466 }
467 #endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
468
469 /*
470 * This is called when a page has been modified by the kernel.
471 * It just marks the page as not i-cache clean. We do the i-cache
472 * flush later when the page is given to a user process, if necessary.
473 */
flush_dcache_page(struct page * page)474 void flush_dcache_page(struct page *page)
475 {
476 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
477 return;
478 /* avoid an atomic op if possible */
479 if (test_bit(PG_arch_1, &page->flags))
480 clear_bit(PG_arch_1, &page->flags);
481 }
482 EXPORT_SYMBOL(flush_dcache_page);
483
flush_dcache_icache_page(struct page * page)484 void flush_dcache_icache_page(struct page *page)
485 {
486 #ifdef CONFIG_HUGETLB_PAGE
487 if (PageCompound(page)) {
488 flush_dcache_icache_hugepage(page);
489 return;
490 }
491 #endif
492 #if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
493 /* On 8xx there is no need to kmap since highmem is not supported */
494 __flush_dcache_icache(page_address(page));
495 #else
496 if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
497 void *start = kmap_atomic(page);
498 __flush_dcache_icache(start);
499 kunmap_atomic(start);
500 } else {
501 unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
502
503 if (flush_coherent_icache(addr))
504 return;
505 flush_dcache_icache_phys(addr);
506 }
507 #endif
508 }
509 EXPORT_SYMBOL(flush_dcache_icache_page);
510
511 /**
512 * __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
513 * Note: this is necessary because the instruction cache does *not*
514 * snoop from the data cache.
515 *
516 * @page: the address of the page to flush
517 */
__flush_dcache_icache(void * p)518 void __flush_dcache_icache(void *p)
519 {
520 unsigned long addr = (unsigned long)p;
521
522 if (flush_coherent_icache(addr))
523 return;
524
525 clean_dcache_range(addr, addr + PAGE_SIZE);
526
527 /*
528 * We don't flush the icache on 44x. Those have a virtual icache and we
529 * don't have access to the virtual address here (it's not the page
530 * vaddr but where it's mapped in user space). The flushing of the
531 * icache on these is handled elsewhere, when a change in the address
532 * space occurs, before returning to user space.
533 */
534
535 if (mmu_has_feature(MMU_FTR_TYPE_44x))
536 return;
537
538 invalidate_icache_range(addr, addr + PAGE_SIZE);
539 }
540
clear_user_page(void * page,unsigned long vaddr,struct page * pg)541 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
542 {
543 clear_page(page);
544
545 /*
546 * We shouldn't have to do this, but some versions of glibc
547 * require it (ld.so assumes zero filled pages are icache clean)
548 * - Anton
549 */
550 flush_dcache_page(pg);
551 }
552 EXPORT_SYMBOL(clear_user_page);
553
copy_user_page(void * vto,void * vfrom,unsigned long vaddr,struct page * pg)554 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
555 struct page *pg)
556 {
557 copy_page(vto, vfrom);
558
559 /*
560 * We should be able to use the following optimisation, however
561 * there are two problems.
562 * Firstly a bug in some versions of binutils meant PLT sections
563 * were not marked executable.
564 * Secondly the first word in the GOT section is blrl, used
565 * to establish the GOT address. Until recently the GOT was
566 * not marked executable.
567 * - Anton
568 */
569 #if 0
570 if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
571 return;
572 #endif
573
574 flush_dcache_page(pg);
575 }
576
flush_icache_user_range(struct vm_area_struct * vma,struct page * page,unsigned long addr,int len)577 void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
578 unsigned long addr, int len)
579 {
580 unsigned long maddr;
581
582 maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK);
583 flush_icache_range(maddr, maddr + len);
584 kunmap(page);
585 }
586 EXPORT_SYMBOL(flush_icache_user_range);
587
588 /*
589 * System memory should not be in /proc/iomem but various tools expect it
590 * (eg kdump).
591 */
add_system_ram_resources(void)592 static int __init add_system_ram_resources(void)
593 {
594 struct memblock_region *reg;
595
596 for_each_memblock(memory, reg) {
597 struct resource *res;
598 unsigned long base = reg->base;
599 unsigned long size = reg->size;
600
601 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
602 WARN_ON(!res);
603
604 if (res) {
605 res->name = "System RAM";
606 res->start = base;
607 res->end = base + size - 1;
608 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
609 WARN_ON(request_resource(&iomem_resource, res) < 0);
610 }
611 }
612
613 return 0;
614 }
615 subsys_initcall(add_system_ram_resources);
616
617 #ifdef CONFIG_STRICT_DEVMEM
618 /*
619 * devmem_is_allowed(): check to see if /dev/mem access to a certain address
620 * is valid. The argument is a physical page number.
621 *
622 * Access has to be given to non-kernel-ram areas as well, these contain the
623 * PCI mmio resources as well as potential bios/acpi data regions.
624 */
devmem_is_allowed(unsigned long pfn)625 int devmem_is_allowed(unsigned long pfn)
626 {
627 if (page_is_rtas_user_buf(pfn))
628 return 1;
629 if (iomem_is_exclusive(PFN_PHYS(pfn)))
630 return 0;
631 if (!page_is_ram(pfn))
632 return 1;
633 return 0;
634 }
635 #endif /* CONFIG_STRICT_DEVMEM */
636
637 /*
638 * This is defined in kernel/resource.c but only powerpc needs to export it, for
639 * the EHEA driver. Drop this when drivers/net/ethernet/ibm/ehea is removed.
640 */
641 EXPORT_SYMBOL_GPL(walk_system_ram_range);
642