1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/arch/powerpc/platforms/cell/cell_setup.c
4 *
5 * Copyright (C) 1995 Linus Torvalds
6 * Adapted from 'alpha' version by Gary Thomas
7 * Modified by Cort Dougan (cort@cs.nmt.edu)
8 * Modified by PPC64 Team, IBM Corp
9 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH
10 */
11 #undef DEBUG
12
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/mm.h>
16 #include <linux/stddef.h>
17 #include <linux/export.h>
18 #include <linux/unistd.h>
19 #include <linux/user.h>
20 #include <linux/reboot.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/irq.h>
24 #include <linux/seq_file.h>
25 #include <linux/root_dev.h>
26 #include <linux/console.h>
27 #include <linux/mutex.h>
28 #include <linux/memory_hotplug.h>
29 #include <linux/of_platform.h>
30
31 #include <asm/mmu.h>
32 #include <asm/processor.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/prom.h>
36 #include <asm/rtas.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/iommu.h>
39 #include <asm/dma.h>
40 #include <asm/machdep.h>
41 #include <asm/time.h>
42 #include <asm/nvram.h>
43 #include <asm/cputable.h>
44 #include <asm/ppc-pci.h>
45 #include <asm/irq.h>
46 #include <asm/spu.h>
47 #include <asm/spu_priv1.h>
48 #include <asm/udbg.h>
49 #include <asm/mpic.h>
50 #include <asm/cell-regs.h>
51 #include <asm/io-workarounds.h>
52
53 #include "cell.h"
54 #include "interrupt.h"
55 #include "pervasive.h"
56 #include "ras.h"
57
58 #ifdef DEBUG
59 #define DBG(fmt...) udbg_printf(fmt)
60 #else
61 #define DBG(fmt...)
62 #endif
63
cell_show_cpuinfo(struct seq_file * m)64 static void cell_show_cpuinfo(struct seq_file *m)
65 {
66 struct device_node *root;
67 const char *model = "";
68
69 root = of_find_node_by_path("/");
70 if (root)
71 model = of_get_property(root, "model", NULL);
72 seq_printf(m, "machine\t\t: CHRP %s\n", model);
73 of_node_put(root);
74 }
75
cell_progress(char * s,unsigned short hex)76 static void cell_progress(char *s, unsigned short hex)
77 {
78 printk("*** %04x : %s\n", hex, s ? s : "");
79 }
80
cell_fixup_pcie_rootcomplex(struct pci_dev * dev)81 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
82 {
83 struct pci_controller *hose;
84 const char *s;
85 int i;
86
87 if (!machine_is(cell))
88 return;
89
90 /* We're searching for a direct child of the PHB */
91 if (dev->bus->self != NULL || dev->devfn != 0)
92 return;
93
94 hose = pci_bus_to_host(dev->bus);
95 if (hose == NULL)
96 return;
97
98 /* Only on PCIE */
99 if (!of_device_is_compatible(hose->dn, "pciex"))
100 return;
101
102 /* And only on axon */
103 s = of_get_property(hose->dn, "model", NULL);
104 if (!s || strcmp(s, "Axon") != 0)
105 return;
106
107 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
108 dev->resource[i].start = dev->resource[i].end = 0;
109 dev->resource[i].flags = 0;
110 }
111
112 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
113 pci_name(dev));
114 }
115 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
116
cell_setup_phb(struct pci_controller * phb)117 static int cell_setup_phb(struct pci_controller *phb)
118 {
119 const char *model;
120 struct device_node *np;
121
122 int rc = rtas_setup_phb(phb);
123 if (rc)
124 return rc;
125
126 phb->controller_ops = cell_pci_controller_ops;
127
128 np = phb->dn;
129 model = of_get_property(np, "model", NULL);
130 if (model == NULL || !of_node_name_eq(np, "pci"))
131 return 0;
132
133 /* Setup workarounds for spider */
134 if (strcmp(model, "Spider"))
135 return 0;
136
137 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
138 (void *)SPIDER_PCI_REG_BASE);
139 return 0;
140 }
141
142 static const struct of_device_id cell_bus_ids[] __initconst = {
143 { .type = "soc", },
144 { .compatible = "soc", },
145 { .type = "spider", },
146 { .type = "axon", },
147 { .type = "plb5", },
148 { .type = "plb4", },
149 { .type = "opb", },
150 { .type = "ebc", },
151 {},
152 };
153
cell_publish_devices(void)154 static int __init cell_publish_devices(void)
155 {
156 struct device_node *root = of_find_node_by_path("/");
157 struct device_node *np;
158 int node;
159
160 /* Publish OF platform devices for southbridge IOs */
161 of_platform_bus_probe(NULL, cell_bus_ids, NULL);
162
163 /* On spider based blades, we need to manually create the OF
164 * platform devices for the PCI host bridges
165 */
166 for_each_child_of_node(root, np) {
167 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
168 continue;
169 of_platform_device_create(np, NULL, NULL);
170 }
171
172 /* There is no device for the MIC memory controller, thus we create
173 * a platform device for it to attach the EDAC driver to.
174 */
175 for_each_online_node(node) {
176 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
177 continue;
178 platform_device_register_simple("cbe-mic", node, NULL, 0);
179 }
180
181 return 0;
182 }
183 machine_subsys_initcall(cell, cell_publish_devices);
184
mpic_init_IRQ(void)185 static void __init mpic_init_IRQ(void)
186 {
187 struct device_node *dn;
188 struct mpic *mpic;
189
190 for_each_node_by_name(dn, "interrupt-controller") {
191 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
192 continue;
193
194 /* The MPIC driver will get everything it needs from the
195 * device-tree, just pass 0 to all arguments
196 */
197 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
198 0, 0, " MPIC ");
199 if (mpic == NULL)
200 continue;
201 mpic_init(mpic);
202 }
203 }
204
205
cell_init_irq(void)206 static void __init cell_init_irq(void)
207 {
208 iic_init_IRQ();
209 spider_init_IRQ();
210 mpic_init_IRQ();
211 }
212
cell_set_dabrx(void)213 static void __init cell_set_dabrx(void)
214 {
215 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
216 }
217
cell_setup_arch(void)218 static void __init cell_setup_arch(void)
219 {
220 #ifdef CONFIG_SPU_BASE
221 spu_priv1_ops = &spu_priv1_mmio_ops;
222 spu_management_ops = &spu_management_of_ops;
223 #endif
224
225 cbe_regs_init();
226
227 cell_set_dabrx();
228
229 #ifdef CONFIG_CBE_RAS
230 cbe_ras_init();
231 #endif
232
233 #ifdef CONFIG_SMP
234 smp_init_cell();
235 #endif
236 /* init to some ~sane value until calibrate_delay() runs */
237 loops_per_jiffy = 50000000;
238
239 /* Find and initialize PCI host bridges */
240 init_pci_config_tokens();
241
242 cbe_pervasive_init();
243 #ifdef CONFIG_DUMMY_CONSOLE
244 conswitchp = &dummy_con;
245 #endif
246
247 mmio_nvram_init();
248 }
249
cell_probe(void)250 static int __init cell_probe(void)
251 {
252 if (!of_machine_is_compatible("IBM,CBEA") &&
253 !of_machine_is_compatible("IBM,CPBW-1.0"))
254 return 0;
255
256 pm_power_off = rtas_power_off;
257
258 return 1;
259 }
260
define_machine(cell)261 define_machine(cell) {
262 .name = "Cell",
263 .probe = cell_probe,
264 .setup_arch = cell_setup_arch,
265 .show_cpuinfo = cell_show_cpuinfo,
266 .restart = rtas_restart,
267 .halt = rtas_halt,
268 .get_boot_time = rtas_get_boot_time,
269 .get_rtc_time = rtas_get_rtc_time,
270 .set_rtc_time = rtas_set_rtc_time,
271 .calibrate_decr = generic_calibrate_decr,
272 .progress = cell_progress,
273 .init_IRQ = cell_init_irq,
274 .pci_setup_phb = cell_setup_phb,
275 };
276
277 struct pci_controller_ops cell_pci_controller_ops;
278