1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * The file intends to implement the platform dependent EEH operations on pseries.
4 * Actually, the pseries platform is built based on RTAS heavily. That means the
5 * pseries platform dependent EEH operations will be built on RTAS calls. The functions
6 * are derived from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
7 * been done.
8 *
9 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2011.
10 * Copyright IBM Corporation 2001, 2005, 2006
11 * Copyright Dave Engebretsen & Todd Inglett 2001
12 * Copyright Linas Vepstas 2005, 2006
13 */
14
15 #include <linux/atomic.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/of.h>
21 #include <linux/pci.h>
22 #include <linux/proc_fs.h>
23 #include <linux/rbtree.h>
24 #include <linux/sched.h>
25 #include <linux/seq_file.h>
26 #include <linux/spinlock.h>
27
28 #include <asm/eeh.h>
29 #include <asm/eeh_event.h>
30 #include <asm/io.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/rtas.h>
34
35 /* RTAS tokens */
36 static int ibm_set_eeh_option;
37 static int ibm_set_slot_reset;
38 static int ibm_read_slot_reset_state;
39 static int ibm_read_slot_reset_state2;
40 static int ibm_slot_error_detail;
41 static int ibm_get_config_addr_info;
42 static int ibm_get_config_addr_info2;
43 static int ibm_configure_pe;
44
pseries_pcibios_bus_add_device(struct pci_dev * pdev)45 void pseries_pcibios_bus_add_device(struct pci_dev *pdev)
46 {
47 struct pci_dn *pdn = pci_get_pdn(pdev);
48
49 if (eeh_has_flag(EEH_FORCE_DISABLED))
50 return;
51
52 dev_dbg(&pdev->dev, "EEH: Setting up device\n");
53 #ifdef CONFIG_PCI_IOV
54 if (pdev->is_virtfn) {
55 struct pci_dn *physfn_pdn;
56
57 pdn->device_id = pdev->device;
58 pdn->vendor_id = pdev->vendor;
59 pdn->class_code = pdev->class;
60 /*
61 * Last allow unfreeze return code used for retrieval
62 * by user space in eeh-sysfs to show the last command
63 * completion from platform.
64 */
65 pdn->last_allow_rc = 0;
66 physfn_pdn = pci_get_pdn(pdev->physfn);
67 pdn->pe_number = physfn_pdn->pe_num_map[pdn->vf_index];
68 }
69 #endif
70 eeh_add_device_early(pdn);
71 eeh_add_device_late(pdev);
72 #ifdef CONFIG_PCI_IOV
73 if (pdev->is_virtfn) {
74 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
75
76 edev->pe_config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
77 eeh_rmv_from_parent_pe(edev); /* Remove as it is adding to bus pe */
78 eeh_add_to_parent_pe(edev); /* Add as VF PE type */
79 }
80 #endif
81 eeh_sysfs_add_device(pdev);
82 }
83
84 /*
85 * Buffer for reporting slot-error-detail rtas calls. Its here
86 * in BSS, and not dynamically alloced, so that it ends up in
87 * RMO where RTAS can access it.
88 */
89 static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
90 static DEFINE_SPINLOCK(slot_errbuf_lock);
91 static int eeh_error_buf_size;
92
93 /**
94 * pseries_eeh_init - EEH platform dependent initialization
95 *
96 * EEH platform dependent initialization on pseries.
97 */
pseries_eeh_init(void)98 static int pseries_eeh_init(void)
99 {
100 /* figure out EEH RTAS function call tokens */
101 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
102 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
103 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
104 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
105 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
106 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
107 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
108 ibm_configure_pe = rtas_token("ibm,configure-pe");
109
110 /*
111 * ibm,configure-pe and ibm,configure-bridge have the same semantics,
112 * however ibm,configure-pe can be faster. If we can't find
113 * ibm,configure-pe then fall back to using ibm,configure-bridge.
114 */
115 if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE)
116 ibm_configure_pe = rtas_token("ibm,configure-bridge");
117
118 /*
119 * Necessary sanity check. We needn't check "get-config-addr-info"
120 * and its variant since the old firmware probably support address
121 * of domain/bus/slot/function for EEH RTAS operations.
122 */
123 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE ||
124 ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE ||
125 (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
126 ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) ||
127 ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE ||
128 ibm_configure_pe == RTAS_UNKNOWN_SERVICE) {
129 pr_info("EEH functionality not supported\n");
130 return -EINVAL;
131 }
132
133 /* Initialize error log lock and size */
134 spin_lock_init(&slot_errbuf_lock);
135 eeh_error_buf_size = rtas_token("rtas-error-log-max");
136 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
137 pr_info("%s: unknown EEH error log size\n",
138 __func__);
139 eeh_error_buf_size = 1024;
140 } else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
141 pr_info("%s: EEH error log size %d exceeds the maximal %d\n",
142 __func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
143 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
144 }
145
146 /* Set EEH probe mode */
147 eeh_add_flag(EEH_PROBE_MODE_DEVTREE | EEH_ENABLE_IO_FOR_LOG);
148
149 /* Set EEH machine dependent code */
150 ppc_md.pcibios_bus_add_device = pseries_pcibios_bus_add_device;
151
152 return 0;
153 }
154
pseries_eeh_cap_start(struct pci_dn * pdn)155 static int pseries_eeh_cap_start(struct pci_dn *pdn)
156 {
157 u32 status;
158
159 if (!pdn)
160 return 0;
161
162 rtas_read_config(pdn, PCI_STATUS, 2, &status);
163 if (!(status & PCI_STATUS_CAP_LIST))
164 return 0;
165
166 return PCI_CAPABILITY_LIST;
167 }
168
169
pseries_eeh_find_cap(struct pci_dn * pdn,int cap)170 static int pseries_eeh_find_cap(struct pci_dn *pdn, int cap)
171 {
172 int pos = pseries_eeh_cap_start(pdn);
173 int cnt = 48; /* Maximal number of capabilities */
174 u32 id;
175
176 if (!pos)
177 return 0;
178
179 while (cnt--) {
180 rtas_read_config(pdn, pos, 1, &pos);
181 if (pos < 0x40)
182 break;
183 pos &= ~3;
184 rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
185 if (id == 0xff)
186 break;
187 if (id == cap)
188 return pos;
189 pos += PCI_CAP_LIST_NEXT;
190 }
191
192 return 0;
193 }
194
pseries_eeh_find_ecap(struct pci_dn * pdn,int cap)195 static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
196 {
197 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
198 u32 header;
199 int pos = 256;
200 int ttl = (4096 - 256) / 8;
201
202 if (!edev || !edev->pcie_cap)
203 return 0;
204 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
205 return 0;
206 else if (!header)
207 return 0;
208
209 while (ttl-- > 0) {
210 if (PCI_EXT_CAP_ID(header) == cap && pos)
211 return pos;
212
213 pos = PCI_EXT_CAP_NEXT(header);
214 if (pos < 256)
215 break;
216
217 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
218 break;
219 }
220
221 return 0;
222 }
223
224 /**
225 * pseries_eeh_probe - EEH probe on the given device
226 * @pdn: PCI device node
227 * @data: Unused
228 *
229 * When EEH module is installed during system boot, all PCI devices
230 * are checked one by one to see if it supports EEH. The function
231 * is introduced for the purpose.
232 */
pseries_eeh_probe(struct pci_dn * pdn,void * data)233 static void *pseries_eeh_probe(struct pci_dn *pdn, void *data)
234 {
235 struct eeh_dev *edev;
236 struct eeh_pe pe;
237 u32 pcie_flags;
238 int enable = 0;
239 int ret;
240
241 /* Retrieve OF node and eeh device */
242 edev = pdn_to_eeh_dev(pdn);
243 if (!edev || edev->pe)
244 return NULL;
245
246 /* Check class/vendor/device IDs */
247 if (!pdn->vendor_id || !pdn->device_id || !pdn->class_code)
248 return NULL;
249
250 /* Skip for PCI-ISA bridge */
251 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
252 return NULL;
253
254 eeh_edev_dbg(edev, "Probing device\n");
255
256 /*
257 * Update class code and mode of eeh device. We need
258 * correctly reflects that current device is root port
259 * or PCIe switch downstream port.
260 */
261 edev->class_code = pdn->class_code;
262 edev->pcix_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
263 edev->pcie_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
264 edev->aer_cap = pseries_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
265 edev->mode &= 0xFFFFFF00;
266 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
267 edev->mode |= EEH_DEV_BRIDGE;
268 if (edev->pcie_cap) {
269 rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
270 2, &pcie_flags);
271 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
272 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
273 edev->mode |= EEH_DEV_ROOT_PORT;
274 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
275 edev->mode |= EEH_DEV_DS_PORT;
276 }
277 }
278
279 /* Initialize the fake PE */
280 memset(&pe, 0, sizeof(struct eeh_pe));
281 pe.phb = pdn->phb;
282 pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
283
284 /* Enable EEH on the device */
285 eeh_edev_dbg(edev, "Enabling EEH on device\n");
286 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
287 if (ret) {
288 eeh_edev_dbg(edev, "EEH failed to enable on device (code %d)\n", ret);
289 } else {
290 /* Retrieve PE address */
291 edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
292 pe.addr = edev->pe_config_addr;
293
294 /* Some older systems (Power4) allow the ibm,set-eeh-option
295 * call to succeed even on nodes where EEH is not supported.
296 * Verify support explicitly.
297 */
298 ret = eeh_ops->get_state(&pe, NULL);
299 if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
300 enable = 1;
301
302 if (enable) {
303 eeh_add_flag(EEH_ENABLED);
304 eeh_add_to_parent_pe(edev);
305 } else if (pdn->parent && pdn_to_eeh_dev(pdn->parent) &&
306 (pdn_to_eeh_dev(pdn->parent))->pe) {
307 /* This device doesn't support EEH, but it may have an
308 * EEH parent, in which case we mark it as supported.
309 */
310 edev->pe_config_addr = pdn_to_eeh_dev(pdn->parent)->pe_config_addr;
311 eeh_add_to_parent_pe(edev);
312 }
313 eeh_edev_dbg(edev, "EEH is %s on device (code %d)\n",
314 (enable ? "enabled" : "unsupported"), ret);
315 }
316
317 /* Save memory bars */
318 eeh_save_bars(edev);
319
320 return NULL;
321 }
322
323 /**
324 * pseries_eeh_set_option - Initialize EEH or MMIO/DMA reenable
325 * @pe: EEH PE
326 * @option: operation to be issued
327 *
328 * The function is used to control the EEH functionality globally.
329 * Currently, following options are support according to PAPR:
330 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
331 */
pseries_eeh_set_option(struct eeh_pe * pe,int option)332 static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
333 {
334 int ret = 0;
335 int config_addr;
336
337 /*
338 * When we're enabling or disabling EEH functioality on
339 * the particular PE, the PE config address is possibly
340 * unavailable. Therefore, we have to figure it out from
341 * the FDT node.
342 */
343 switch (option) {
344 case EEH_OPT_DISABLE:
345 case EEH_OPT_ENABLE:
346 case EEH_OPT_THAW_MMIO:
347 case EEH_OPT_THAW_DMA:
348 config_addr = pe->config_addr;
349 if (pe->addr)
350 config_addr = pe->addr;
351 break;
352 case EEH_OPT_FREEZE_PE:
353 /* Not support */
354 return 0;
355 default:
356 pr_err("%s: Invalid option %d\n",
357 __func__, option);
358 return -EINVAL;
359 }
360
361 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
362 config_addr, BUID_HI(pe->phb->buid),
363 BUID_LO(pe->phb->buid), option);
364
365 return ret;
366 }
367
368 /**
369 * pseries_eeh_get_pe_addr - Retrieve PE address
370 * @pe: EEH PE
371 *
372 * Retrieve the assocated PE address. Actually, there're 2 RTAS
373 * function calls dedicated for the purpose. We need implement
374 * it through the new function and then the old one. Besides,
375 * you should make sure the config address is figured out from
376 * FDT node before calling the function.
377 *
378 * It's notable that zero'ed return value means invalid PE config
379 * address.
380 */
pseries_eeh_get_pe_addr(struct eeh_pe * pe)381 static int pseries_eeh_get_pe_addr(struct eeh_pe *pe)
382 {
383 int ret = 0;
384 int rets[3];
385
386 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
387 /*
388 * First of all, we need to make sure there has one PE
389 * associated with the device. Otherwise, PE address is
390 * meaningless.
391 */
392 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
393 pe->config_addr, BUID_HI(pe->phb->buid),
394 BUID_LO(pe->phb->buid), 1);
395 if (ret || (rets[0] == 0))
396 return 0;
397
398 /* Retrieve the associated PE config address */
399 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
400 pe->config_addr, BUID_HI(pe->phb->buid),
401 BUID_LO(pe->phb->buid), 0);
402 if (ret) {
403 pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
404 __func__, pe->phb->global_number, pe->config_addr);
405 return 0;
406 }
407
408 return rets[0];
409 }
410
411 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
412 ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
413 pe->config_addr, BUID_HI(pe->phb->buid),
414 BUID_LO(pe->phb->buid), 0);
415 if (ret) {
416 pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
417 __func__, pe->phb->global_number, pe->config_addr);
418 return 0;
419 }
420
421 return rets[0];
422 }
423
424 return ret;
425 }
426
427 /**
428 * pseries_eeh_get_state - Retrieve PE state
429 * @pe: EEH PE
430 * @delay: suggested time to wait if state is unavailable
431 *
432 * Retrieve the state of the specified PE. On RTAS compliant
433 * pseries platform, there already has one dedicated RTAS function
434 * for the purpose. It's notable that the associated PE config address
435 * might be ready when calling the function. Therefore, endeavour to
436 * use the PE config address if possible. Further more, there're 2
437 * RTAS calls for the purpose, we need to try the new one and back
438 * to the old one if the new one couldn't work properly.
439 */
pseries_eeh_get_state(struct eeh_pe * pe,int * delay)440 static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)
441 {
442 int config_addr;
443 int ret;
444 int rets[4];
445 int result;
446
447 /* Figure out PE config address if possible */
448 config_addr = pe->config_addr;
449 if (pe->addr)
450 config_addr = pe->addr;
451
452 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
453 ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
454 config_addr, BUID_HI(pe->phb->buid),
455 BUID_LO(pe->phb->buid));
456 } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
457 /* Fake PE unavailable info */
458 rets[2] = 0;
459 ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
460 config_addr, BUID_HI(pe->phb->buid),
461 BUID_LO(pe->phb->buid));
462 } else {
463 return EEH_STATE_NOT_SUPPORT;
464 }
465
466 if (ret)
467 return ret;
468
469 /* Parse the result out */
470 if (!rets[1])
471 return EEH_STATE_NOT_SUPPORT;
472
473 switch(rets[0]) {
474 case 0:
475 result = EEH_STATE_MMIO_ACTIVE |
476 EEH_STATE_DMA_ACTIVE;
477 break;
478 case 1:
479 result = EEH_STATE_RESET_ACTIVE |
480 EEH_STATE_MMIO_ACTIVE |
481 EEH_STATE_DMA_ACTIVE;
482 break;
483 case 2:
484 result = 0;
485 break;
486 case 4:
487 result = EEH_STATE_MMIO_ENABLED;
488 break;
489 case 5:
490 if (rets[2]) {
491 if (delay)
492 *delay = rets[2];
493 result = EEH_STATE_UNAVAILABLE;
494 } else {
495 result = EEH_STATE_NOT_SUPPORT;
496 }
497 break;
498 default:
499 result = EEH_STATE_NOT_SUPPORT;
500 }
501
502 return result;
503 }
504
505 /**
506 * pseries_eeh_reset - Reset the specified PE
507 * @pe: EEH PE
508 * @option: reset option
509 *
510 * Reset the specified PE
511 */
pseries_eeh_reset(struct eeh_pe * pe,int option)512 static int pseries_eeh_reset(struct eeh_pe *pe, int option)
513 {
514 int config_addr;
515 int ret;
516
517 /* Figure out PE address */
518 config_addr = pe->config_addr;
519 if (pe->addr)
520 config_addr = pe->addr;
521
522 /* Reset PE through RTAS call */
523 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
524 config_addr, BUID_HI(pe->phb->buid),
525 BUID_LO(pe->phb->buid), option);
526
527 /* If fundamental-reset not supported, try hot-reset */
528 if (option == EEH_RESET_FUNDAMENTAL &&
529 ret == -8) {
530 option = EEH_RESET_HOT;
531 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
532 config_addr, BUID_HI(pe->phb->buid),
533 BUID_LO(pe->phb->buid), option);
534 }
535
536 /* We need reset hold or settlement delay */
537 if (option == EEH_RESET_FUNDAMENTAL ||
538 option == EEH_RESET_HOT)
539 msleep(EEH_PE_RST_HOLD_TIME);
540 else
541 msleep(EEH_PE_RST_SETTLE_TIME);
542
543 return ret;
544 }
545
546 /**
547 * pseries_eeh_get_log - Retrieve error log
548 * @pe: EEH PE
549 * @severity: temporary or permanent error log
550 * @drv_log: driver log to be combined with retrieved error log
551 * @len: length of driver log
552 *
553 * Retrieve the temporary or permanent error from the PE.
554 * Actually, the error will be retrieved through the dedicated
555 * RTAS call.
556 */
pseries_eeh_get_log(struct eeh_pe * pe,int severity,char * drv_log,unsigned long len)557 static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
558 {
559 int config_addr;
560 unsigned long flags;
561 int ret;
562
563 spin_lock_irqsave(&slot_errbuf_lock, flags);
564 memset(slot_errbuf, 0, eeh_error_buf_size);
565
566 /* Figure out the PE address */
567 config_addr = pe->config_addr;
568 if (pe->addr)
569 config_addr = pe->addr;
570
571 ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
572 BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
573 virt_to_phys(drv_log), len,
574 virt_to_phys(slot_errbuf), eeh_error_buf_size,
575 severity);
576 if (!ret)
577 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
578 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
579
580 return ret;
581 }
582
583 /**
584 * pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
585 * @pe: EEH PE
586 *
587 * The function will be called to reconfigure the bridges included
588 * in the specified PE so that the mulfunctional PE would be recovered
589 * again.
590 */
pseries_eeh_configure_bridge(struct eeh_pe * pe)591 static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
592 {
593 int config_addr;
594 int ret;
595 /* Waiting 0.2s maximum before skipping configuration */
596 int max_wait = 200;
597
598 /* Figure out the PE address */
599 config_addr = pe->config_addr;
600 if (pe->addr)
601 config_addr = pe->addr;
602
603 while (max_wait > 0) {
604 ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
605 config_addr, BUID_HI(pe->phb->buid),
606 BUID_LO(pe->phb->buid));
607
608 if (!ret)
609 return ret;
610
611 /*
612 * If RTAS returns a delay value that's above 100ms, cut it
613 * down to 100ms in case firmware made a mistake. For more
614 * on how these delay values work see rtas_busy_delay_time
615 */
616 if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
617 ret <= RTAS_EXTENDED_DELAY_MAX)
618 ret = RTAS_EXTENDED_DELAY_MIN+2;
619
620 max_wait -= rtas_busy_delay_time(ret);
621
622 if (max_wait < 0)
623 break;
624
625 rtas_busy_delay(ret);
626 }
627
628 pr_warn("%s: Unable to configure bridge PHB#%x-PE#%x (%d)\n",
629 __func__, pe->phb->global_number, pe->addr, ret);
630 return ret;
631 }
632
633 /**
634 * pseries_eeh_read_config - Read PCI config space
635 * @pdn: PCI device node
636 * @where: PCI address
637 * @size: size to read
638 * @val: return value
639 *
640 * Read config space from the speicifed device
641 */
pseries_eeh_read_config(struct pci_dn * pdn,int where,int size,u32 * val)642 static int pseries_eeh_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
643 {
644 return rtas_read_config(pdn, where, size, val);
645 }
646
647 /**
648 * pseries_eeh_write_config - Write PCI config space
649 * @pdn: PCI device node
650 * @where: PCI address
651 * @size: size to write
652 * @val: value to be written
653 *
654 * Write config space to the specified device
655 */
pseries_eeh_write_config(struct pci_dn * pdn,int where,int size,u32 val)656 static int pseries_eeh_write_config(struct pci_dn *pdn, int where, int size, u32 val)
657 {
658 return rtas_write_config(pdn, where, size, val);
659 }
660
pseries_eeh_restore_config(struct pci_dn * pdn)661 static int pseries_eeh_restore_config(struct pci_dn *pdn)
662 {
663 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
664 s64 ret = 0;
665
666 if (!edev)
667 return -EEXIST;
668
669 /*
670 * FIXME: The MPS, error routing rules, timeout setting are worthy
671 * to be exported by firmware in extendible way.
672 */
673 if (edev->physfn)
674 ret = eeh_restore_vf_config(pdn);
675
676 if (ret) {
677 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
678 __func__, edev->pe_config_addr, ret);
679 return -EIO;
680 }
681
682 return ret;
683 }
684
685 #ifdef CONFIG_PCI_IOV
pseries_send_allow_unfreeze(struct pci_dn * pdn,u16 * vf_pe_array,int cur_vfs)686 int pseries_send_allow_unfreeze(struct pci_dn *pdn,
687 u16 *vf_pe_array, int cur_vfs)
688 {
689 int rc;
690 int ibm_allow_unfreeze = rtas_token("ibm,open-sriov-allow-unfreeze");
691 unsigned long buid, addr;
692
693 addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
694 buid = pdn->phb->buid;
695 spin_lock(&rtas_data_buf_lock);
696 memcpy(rtas_data_buf, vf_pe_array, RTAS_DATA_BUF_SIZE);
697 rc = rtas_call(ibm_allow_unfreeze, 5, 1, NULL,
698 addr,
699 BUID_HI(buid),
700 BUID_LO(buid),
701 rtas_data_buf, cur_vfs * sizeof(u16));
702 spin_unlock(&rtas_data_buf_lock);
703 if (rc)
704 pr_warn("%s: Failed to allow unfreeze for PHB#%x-PE#%lx, rc=%x\n",
705 __func__,
706 pdn->phb->global_number, addr, rc);
707 return rc;
708 }
709
pseries_call_allow_unfreeze(struct eeh_dev * edev)710 static int pseries_call_allow_unfreeze(struct eeh_dev *edev)
711 {
712 struct pci_dn *pdn, *tmp, *parent, *physfn_pdn;
713 int cur_vfs = 0, rc = 0, vf_index, bus, devfn;
714 u16 *vf_pe_array;
715
716 vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
717 if (!vf_pe_array)
718 return -ENOMEM;
719 if (pci_num_vf(edev->physfn ? edev->physfn : edev->pdev)) {
720 if (edev->pdev->is_physfn) {
721 cur_vfs = pci_num_vf(edev->pdev);
722 pdn = eeh_dev_to_pdn(edev);
723 parent = pdn->parent;
724 for (vf_index = 0; vf_index < cur_vfs; vf_index++)
725 vf_pe_array[vf_index] =
726 cpu_to_be16(pdn->pe_num_map[vf_index]);
727 rc = pseries_send_allow_unfreeze(pdn, vf_pe_array,
728 cur_vfs);
729 pdn->last_allow_rc = rc;
730 for (vf_index = 0; vf_index < cur_vfs; vf_index++) {
731 list_for_each_entry_safe(pdn, tmp,
732 &parent->child_list,
733 list) {
734 bus = pci_iov_virtfn_bus(edev->pdev,
735 vf_index);
736 devfn = pci_iov_virtfn_devfn(edev->pdev,
737 vf_index);
738 if (pdn->busno != bus ||
739 pdn->devfn != devfn)
740 continue;
741 pdn->last_allow_rc = rc;
742 }
743 }
744 } else {
745 pdn = pci_get_pdn(edev->pdev);
746 vf_pe_array[0] = cpu_to_be16(pdn->pe_number);
747 physfn_pdn = pci_get_pdn(edev->physfn);
748 rc = pseries_send_allow_unfreeze(physfn_pdn,
749 vf_pe_array, 1);
750 pdn->last_allow_rc = rc;
751 }
752 }
753
754 kfree(vf_pe_array);
755 return rc;
756 }
757
pseries_notify_resume(struct pci_dn * pdn)758 static int pseries_notify_resume(struct pci_dn *pdn)
759 {
760 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
761
762 if (!edev)
763 return -EEXIST;
764
765 if (rtas_token("ibm,open-sriov-allow-unfreeze")
766 == RTAS_UNKNOWN_SERVICE)
767 return -EINVAL;
768
769 if (edev->pdev->is_physfn || edev->pdev->is_virtfn)
770 return pseries_call_allow_unfreeze(edev);
771
772 return 0;
773 }
774 #endif
775
776 static struct eeh_ops pseries_eeh_ops = {
777 .name = "pseries",
778 .init = pseries_eeh_init,
779 .probe = pseries_eeh_probe,
780 .set_option = pseries_eeh_set_option,
781 .get_pe_addr = pseries_eeh_get_pe_addr,
782 .get_state = pseries_eeh_get_state,
783 .reset = pseries_eeh_reset,
784 .get_log = pseries_eeh_get_log,
785 .configure_bridge = pseries_eeh_configure_bridge,
786 .err_inject = NULL,
787 .read_config = pseries_eeh_read_config,
788 .write_config = pseries_eeh_write_config,
789 .next_error = NULL,
790 .restore_config = pseries_eeh_restore_config,
791 #ifdef CONFIG_PCI_IOV
792 .notify_resume = pseries_notify_resume
793 #endif
794 };
795
796 /**
797 * eeh_pseries_init - Register platform dependent EEH operations
798 *
799 * EEH initialization on pseries platform. This function should be
800 * called before any EEH related functions.
801 */
eeh_pseries_init(void)802 static int __init eeh_pseries_init(void)
803 {
804 int ret;
805
806 ret = eeh_ops_register(&pseries_eeh_ops);
807 if (!ret)
808 pr_info("EEH: pSeries platform initialized\n");
809 else
810 pr_info("EEH: pSeries platform initialization failure (%d)\n",
811 ret);
812
813 return ret;
814 }
815 machine_early_initcall(pseries, eeh_pseries_init);
816