1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale MPC85xx/MPC86xx RapidIO support
4 *
5 * Copyright 2009 Sysgo AG
6 * Thomas Moll <thomas.moll@sysgo.com>
7 * - fixed maintenance access routines, check for aligned access
8 *
9 * Copyright 2009 Integrated Device Technology, Inc.
10 * Alex Bounine <alexandre.bounine@idt.com>
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
13 *
14 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
15 * Zhang Wei <wei.zhang@freescale.com>
16 *
17 * Copyright 2005 MontaVista Software, Inc.
18 * Matt Porter <mporter@kernel.crashing.org>
19 */
20
21 #include <linux/init.h>
22 #include <linux/extable.h>
23 #include <linux/types.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/interrupt.h>
26 #include <linux/device.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32
33 #include <linux/io.h>
34 #include <linux/uaccess.h>
35 #include <asm/machdep.h>
36
37 #include "fsl_rio.h"
38
39 #undef DEBUG_PW /* Port-Write debugging */
40
41 #define RIO_PORT1_EDCSR 0x0640
42 #define RIO_PORT2_EDCSR 0x0680
43 #define RIO_PORT1_IECSR 0x10130
44 #define RIO_PORT2_IECSR 0x101B0
45
46 #define RIO_GCCSR 0x13c
47 #define RIO_ESCSR 0x158
48 #define ESCSR_CLEAR 0x07120204
49 #define RIO_PORT2_ESCSR 0x178
50 #define RIO_CCSR 0x15c
51 #define RIO_LTLEDCSR_IER 0x80000000
52 #define RIO_LTLEDCSR_PRT 0x01000000
53 #define IECSR_CLEAR 0x80000000
54 #define RIO_ISR_AACR 0x10120
55 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
56
57 #define RIWTAR_TRAD_VAL_SHIFT 12
58 #define RIWTAR_TRAD_MASK 0x00FFFFFF
59 #define RIWBAR_BADD_VAL_SHIFT 12
60 #define RIWBAR_BADD_MASK 0x003FFFFF
61 #define RIWAR_ENABLE 0x80000000
62 #define RIWAR_TGINT_LOCAL 0x00F00000
63 #define RIWAR_RDTYP_NO_SNOOP 0x00040000
64 #define RIWAR_RDTYP_SNOOP 0x00050000
65 #define RIWAR_WRTYP_NO_SNOOP 0x00004000
66 #define RIWAR_WRTYP_SNOOP 0x00005000
67 #define RIWAR_WRTYP_ALLOC 0x00006000
68 #define RIWAR_SIZE_MASK 0x0000003F
69
70 static DEFINE_SPINLOCK(fsl_rio_config_lock);
71
72 #define __fsl_read_rio_config(x, addr, err, op) \
73 __asm__ __volatile__( \
74 "1: "op" %1,0(%2)\n" \
75 " eieio\n" \
76 "2:\n" \
77 ".section .fixup,\"ax\"\n" \
78 "3: li %1,-1\n" \
79 " li %0,%3\n" \
80 " b 2b\n" \
81 ".previous\n" \
82 EX_TABLE(1b, 3b) \
83 : "=r" (err), "=r" (x) \
84 : "b" (addr), "i" (-EFAULT), "0" (err))
85
86 void __iomem *rio_regs_win;
87 void __iomem *rmu_regs_win;
88 resource_size_t rio_law_start;
89
90 struct fsl_rio_dbell *dbell;
91 struct fsl_rio_pw *pw;
92
93 #ifdef CONFIG_E500
fsl_rio_mcheck_exception(struct pt_regs * regs)94 int fsl_rio_mcheck_exception(struct pt_regs *regs)
95 {
96 const struct exception_table_entry *entry;
97 unsigned long reason;
98
99 if (!rio_regs_win)
100 return 0;
101
102 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
103 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
104 /* Check if we are prepared to handle this fault */
105 entry = search_exception_tables(regs->nip);
106 if (entry) {
107 pr_debug("RIO: %s - MC Exception handled\n",
108 __func__);
109 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
110 0);
111 regs->msr |= MSR_RI;
112 regs->nip = extable_fixup(entry);
113 return 1;
114 }
115 }
116
117 return 0;
118 }
119 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
120 #endif
121
122 /**
123 * fsl_local_config_read - Generate a MPC85xx local config space read
124 * @mport: RapidIO master port info
125 * @index: ID of RapdiIO interface
126 * @offset: Offset into configuration space
127 * @len: Length (in bytes) of the maintenance transaction
128 * @data: Value to be read into
129 *
130 * Generates a MPC85xx local configuration space read. Returns %0 on
131 * success or %-EINVAL on failure.
132 */
fsl_local_config_read(struct rio_mport * mport,int index,u32 offset,int len,u32 * data)133 static int fsl_local_config_read(struct rio_mport *mport,
134 int index, u32 offset, int len, u32 *data)
135 {
136 struct rio_priv *priv = mport->priv;
137 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
138 offset);
139 *data = in_be32(priv->regs_win + offset);
140
141 return 0;
142 }
143
144 /**
145 * fsl_local_config_write - Generate a MPC85xx local config space write
146 * @mport: RapidIO master port info
147 * @index: ID of RapdiIO interface
148 * @offset: Offset into configuration space
149 * @len: Length (in bytes) of the maintenance transaction
150 * @data: Value to be written
151 *
152 * Generates a MPC85xx local configuration space write. Returns %0 on
153 * success or %-EINVAL on failure.
154 */
fsl_local_config_write(struct rio_mport * mport,int index,u32 offset,int len,u32 data)155 static int fsl_local_config_write(struct rio_mport *mport,
156 int index, u32 offset, int len, u32 data)
157 {
158 struct rio_priv *priv = mport->priv;
159 pr_debug
160 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
161 index, offset, data);
162 out_be32(priv->regs_win + offset, data);
163
164 return 0;
165 }
166
167 /**
168 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
169 * @mport: RapidIO master port info
170 * @index: ID of RapdiIO interface
171 * @destid: Destination ID of transaction
172 * @hopcount: Number of hops to target device
173 * @offset: Offset into configuration space
174 * @len: Length (in bytes) of the maintenance transaction
175 * @val: Location to be read into
176 *
177 * Generates a MPC85xx read maintenance transaction. Returns %0 on
178 * success or %-EINVAL on failure.
179 */
180 static int
fsl_rio_config_read(struct rio_mport * mport,int index,u16 destid,u8 hopcount,u32 offset,int len,u32 * val)181 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
182 u8 hopcount, u32 offset, int len, u32 *val)
183 {
184 struct rio_priv *priv = mport->priv;
185 unsigned long flags;
186 u8 *data;
187 u32 rval, err = 0;
188
189 pr_debug
190 ("fsl_rio_config_read:"
191 " index %d destid %d hopcount %d offset %8.8x len %d\n",
192 index, destid, hopcount, offset, len);
193
194 /* 16MB maintenance window possible */
195 /* allow only aligned access to maintenance registers */
196 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
197 return -EINVAL;
198
199 spin_lock_irqsave(&fsl_rio_config_lock, flags);
200
201 out_be32(&priv->maint_atmu_regs->rowtar,
202 (destid << 22) | (hopcount << 12) | (offset >> 12));
203 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
204
205 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
206 switch (len) {
207 case 1:
208 __fsl_read_rio_config(rval, data, err, "lbz");
209 break;
210 case 2:
211 __fsl_read_rio_config(rval, data, err, "lhz");
212 break;
213 case 4:
214 __fsl_read_rio_config(rval, data, err, "lwz");
215 break;
216 default:
217 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
218 return -EINVAL;
219 }
220
221 if (err) {
222 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
223 err, destid, hopcount, offset);
224 }
225
226 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
227 *val = rval;
228
229 return err;
230 }
231
232 /**
233 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
234 * @mport: RapidIO master port info
235 * @index: ID of RapdiIO interface
236 * @destid: Destination ID of transaction
237 * @hopcount: Number of hops to target device
238 * @offset: Offset into configuration space
239 * @len: Length (in bytes) of the maintenance transaction
240 * @val: Value to be written
241 *
242 * Generates an MPC85xx write maintenance transaction. Returns %0 on
243 * success or %-EINVAL on failure.
244 */
245 static int
fsl_rio_config_write(struct rio_mport * mport,int index,u16 destid,u8 hopcount,u32 offset,int len,u32 val)246 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
247 u8 hopcount, u32 offset, int len, u32 val)
248 {
249 struct rio_priv *priv = mport->priv;
250 unsigned long flags;
251 u8 *data;
252 int ret = 0;
253
254 pr_debug
255 ("fsl_rio_config_write:"
256 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
257 index, destid, hopcount, offset, len, val);
258
259 /* 16MB maintenance windows possible */
260 /* allow only aligned access to maintenance registers */
261 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
262 return -EINVAL;
263
264 spin_lock_irqsave(&fsl_rio_config_lock, flags);
265
266 out_be32(&priv->maint_atmu_regs->rowtar,
267 (destid << 22) | (hopcount << 12) | (offset >> 12));
268 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
269
270 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
271 switch (len) {
272 case 1:
273 out_8((u8 *) data, val);
274 break;
275 case 2:
276 out_be16((u16 *) data, val);
277 break;
278 case 4:
279 out_be32((u32 *) data, val);
280 break;
281 default:
282 ret = -EINVAL;
283 }
284 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
285
286 return ret;
287 }
288
fsl_rio_inbound_mem_init(struct rio_priv * priv)289 static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
290 {
291 int i;
292
293 /* close inbound windows */
294 for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
295 out_be32(&priv->inb_atmu_regs[i].riwar, 0);
296 }
297
fsl_map_inb_mem(struct rio_mport * mport,dma_addr_t lstart,u64 rstart,u64 size,u32 flags)298 int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
299 u64 rstart, u64 size, u32 flags)
300 {
301 struct rio_priv *priv = mport->priv;
302 u32 base_size;
303 unsigned int base_size_log;
304 u64 win_start, win_end;
305 u32 riwar;
306 int i;
307
308 if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
309 return -EINVAL;
310
311 base_size_log = ilog2(size);
312 base_size = 1 << base_size_log;
313
314 /* check if addresses are aligned with the window size */
315 if (lstart & (base_size - 1))
316 return -EINVAL;
317 if (rstart & (base_size - 1))
318 return -EINVAL;
319
320 /* check for conflicting ranges */
321 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
322 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
323 if ((riwar & RIWAR_ENABLE) == 0)
324 continue;
325 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
326 << RIWBAR_BADD_VAL_SHIFT;
327 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
328 if (rstart < win_end && (rstart + size) > win_start)
329 return -EINVAL;
330 }
331
332 /* find unused atmu */
333 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
334 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
335 if ((riwar & RIWAR_ENABLE) == 0)
336 break;
337 }
338 if (i >= RIO_INB_ATMU_COUNT)
339 return -ENOMEM;
340
341 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
342 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
343 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
344 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
345
346 return 0;
347 }
348
fsl_unmap_inb_mem(struct rio_mport * mport,dma_addr_t lstart)349 void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
350 {
351 u32 win_start_shift, base_start_shift;
352 struct rio_priv *priv = mport->priv;
353 u32 riwar, riwtar;
354 int i;
355
356 /* skip default window */
357 base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
358 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
359 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
360 if ((riwar & RIWAR_ENABLE) == 0)
361 continue;
362
363 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
364 win_start_shift = riwtar & RIWTAR_TRAD_MASK;
365 if (win_start_shift == base_start_shift) {
366 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
367 return;
368 }
369 }
370 }
371
fsl_rio_port_error_handler(int offset)372 void fsl_rio_port_error_handler(int offset)
373 {
374 /*XXX: Error recovery is not implemented, we just clear errors */
375 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
376
377 if (offset == 0) {
378 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
379 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
380 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
381 } else {
382 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
383 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
384 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
385 }
386 }
fsl_rio_info(struct device * dev,u32 ccsr)387 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
388 {
389 const char *str;
390 if (ccsr & 1) {
391 /* Serial phy */
392 switch (ccsr >> 30) {
393 case 0:
394 str = "1";
395 break;
396 case 1:
397 str = "4";
398 break;
399 default:
400 str = "Unknown";
401 break;
402 }
403 dev_info(dev, "Hardware port width: %s\n", str);
404
405 switch ((ccsr >> 27) & 7) {
406 case 0:
407 str = "Single-lane 0";
408 break;
409 case 1:
410 str = "Single-lane 2";
411 break;
412 case 2:
413 str = "Four-lane";
414 break;
415 default:
416 str = "Unknown";
417 break;
418 }
419 dev_info(dev, "Training connection status: %s\n", str);
420 } else {
421 /* Parallel phy */
422 if (!(ccsr & 0x80000000))
423 dev_info(dev, "Output port operating in 8-bit mode\n");
424 if (!(ccsr & 0x08000000))
425 dev_info(dev, "Input port operating in 8-bit mode\n");
426 }
427 }
428
429 /**
430 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
431 * @dev: platform_device pointer
432 *
433 * Initializes MPC85xx RapidIO hardware interface, configures
434 * master port with system-specific info, and registers the
435 * master port with the RapidIO subsystem.
436 */
fsl_rio_setup(struct platform_device * dev)437 int fsl_rio_setup(struct platform_device *dev)
438 {
439 struct rio_ops *ops;
440 struct rio_mport *port;
441 struct rio_priv *priv;
442 int rc = 0;
443 const u32 *dt_range, *cell, *port_index;
444 u32 active_ports = 0;
445 struct resource regs, rmu_regs;
446 struct device_node *np, *rmu_node;
447 int rlen;
448 u32 ccsr;
449 u64 range_start, range_size;
450 int paw, aw, sw;
451 u32 i;
452 static int tmp;
453 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
454
455 if (!dev->dev.of_node) {
456 dev_err(&dev->dev, "Device OF-Node is NULL");
457 return -ENODEV;
458 }
459
460 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
461 if (rc) {
462 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
463 dev->dev.of_node);
464 return -EFAULT;
465 }
466 dev_info(&dev->dev, "Of-device full name %pOF\n",
467 dev->dev.of_node);
468 dev_info(&dev->dev, "Regs: %pR\n", ®s);
469
470 rio_regs_win = ioremap(regs.start, resource_size(®s));
471 if (!rio_regs_win) {
472 dev_err(&dev->dev, "Unable to map rio register window\n");
473 rc = -ENOMEM;
474 goto err_rio_regs;
475 }
476
477 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
478 if (!ops) {
479 rc = -ENOMEM;
480 goto err_ops;
481 }
482 ops->lcread = fsl_local_config_read;
483 ops->lcwrite = fsl_local_config_write;
484 ops->cread = fsl_rio_config_read;
485 ops->cwrite = fsl_rio_config_write;
486 ops->dsend = fsl_rio_doorbell_send;
487 ops->pwenable = fsl_rio_pw_enable;
488 ops->open_outb_mbox = fsl_open_outb_mbox;
489 ops->open_inb_mbox = fsl_open_inb_mbox;
490 ops->close_outb_mbox = fsl_close_outb_mbox;
491 ops->close_inb_mbox = fsl_close_inb_mbox;
492 ops->add_outb_message = fsl_add_outb_message;
493 ops->add_inb_buffer = fsl_add_inb_buffer;
494 ops->get_inb_message = fsl_get_inb_message;
495 ops->map_inb = fsl_map_inb_mem;
496 ops->unmap_inb = fsl_unmap_inb_mem;
497
498 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
499 if (!rmu_node) {
500 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
501 rc = -ENOENT;
502 goto err_rmu;
503 }
504 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
505 if (rc) {
506 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
507 rmu_node);
508 of_node_put(rmu_node);
509 goto err_rmu;
510 }
511 of_node_put(rmu_node);
512 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
513 if (!rmu_regs_win) {
514 dev_err(&dev->dev, "Unable to map rmu register window\n");
515 rc = -ENOMEM;
516 goto err_rmu;
517 }
518 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
519 rmu_np[tmp] = np;
520 tmp++;
521 }
522
523 /*set up doobell node*/
524 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
525 if (!np) {
526 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
527 rc = -ENODEV;
528 goto err_dbell;
529 }
530 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
531 if (!(dbell)) {
532 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
533 rc = -ENOMEM;
534 goto err_dbell;
535 }
536 dbell->dev = &dev->dev;
537 dbell->bellirq = irq_of_parse_and_map(np, 1);
538 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
539
540 aw = of_n_addr_cells(np);
541 dt_range = of_get_property(np, "reg", &rlen);
542 if (!dt_range) {
543 pr_err("%pOF: unable to find 'reg' property\n",
544 np);
545 rc = -ENOMEM;
546 goto err_pw;
547 }
548 range_start = of_read_number(dt_range, aw);
549 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
550 (u32)range_start);
551
552 /*set up port write node*/
553 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
554 if (!np) {
555 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
556 rc = -ENODEV;
557 goto err_pw;
558 }
559 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
560 if (!(pw)) {
561 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
562 rc = -ENOMEM;
563 goto err_pw;
564 }
565 pw->dev = &dev->dev;
566 pw->pwirq = irq_of_parse_and_map(np, 0);
567 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
568 aw = of_n_addr_cells(np);
569 dt_range = of_get_property(np, "reg", &rlen);
570 if (!dt_range) {
571 pr_err("%pOF: unable to find 'reg' property\n",
572 np);
573 rc = -ENOMEM;
574 goto err;
575 }
576 range_start = of_read_number(dt_range, aw);
577 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
578
579 /*set up ports node*/
580 for_each_child_of_node(dev->dev.of_node, np) {
581 port_index = of_get_property(np, "cell-index", NULL);
582 if (!port_index) {
583 dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
584 np);
585 continue;
586 }
587
588 dt_range = of_get_property(np, "ranges", &rlen);
589 if (!dt_range) {
590 dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
591 np);
592 continue;
593 }
594
595 /* Get node address wide */
596 cell = of_get_property(np, "#address-cells", NULL);
597 if (cell)
598 aw = *cell;
599 else
600 aw = of_n_addr_cells(np);
601 /* Get node size wide */
602 cell = of_get_property(np, "#size-cells", NULL);
603 if (cell)
604 sw = *cell;
605 else
606 sw = of_n_size_cells(np);
607 /* Get parent address wide wide */
608 paw = of_n_addr_cells(np);
609 range_start = of_read_number(dt_range + aw, paw);
610 range_size = of_read_number(dt_range + aw + paw, sw);
611
612 dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
613 np, range_start, range_size);
614
615 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
616 if (!port)
617 continue;
618
619 rc = rio_mport_initialize(port);
620 if (rc) {
621 kfree(port);
622 continue;
623 }
624
625 i = *port_index - 1;
626 port->index = (unsigned char)i;
627
628 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
629 if (!priv) {
630 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
631 kfree(port);
632 continue;
633 }
634
635 INIT_LIST_HEAD(&port->dbells);
636 port->iores.start = range_start;
637 port->iores.end = port->iores.start + range_size - 1;
638 port->iores.flags = IORESOURCE_MEM;
639 port->iores.name = "rio_io_win";
640
641 if (request_resource(&iomem_resource, &port->iores) < 0) {
642 dev_err(&dev->dev, "RIO: Error requesting master port region"
643 " 0x%016llx-0x%016llx\n",
644 (u64)port->iores.start, (u64)port->iores.end);
645 kfree(priv);
646 kfree(port);
647 continue;
648 }
649 sprintf(port->name, "RIO mport %d", i);
650
651 priv->dev = &dev->dev;
652 port->dev.parent = &dev->dev;
653 port->ops = ops;
654 port->priv = priv;
655 port->phys_efptr = 0x100;
656 port->phys_rmap = 1;
657 priv->regs_win = rio_regs_win;
658
659 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
660
661 /* Checking the port training status */
662 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
663 dev_err(&dev->dev, "Port %d is not ready. "
664 "Try to restart connection...\n", i);
665 /* Disable ports */
666 out_be32(priv->regs_win
667 + RIO_CCSR + i*0x20, 0);
668 /* Set 1x lane */
669 setbits32(priv->regs_win
670 + RIO_CCSR + i*0x20, 0x02000000);
671 /* Enable ports */
672 setbits32(priv->regs_win
673 + RIO_CCSR + i*0x20, 0x00600000);
674 msleep(100);
675 if (in_be32((priv->regs_win
676 + RIO_ESCSR + i*0x20)) & 1) {
677 dev_err(&dev->dev,
678 "Port %d restart failed.\n", i);
679 release_resource(&port->iores);
680 kfree(priv);
681 kfree(port);
682 continue;
683 }
684 dev_info(&dev->dev, "Port %d restart success!\n", i);
685 }
686 fsl_rio_info(&dev->dev, ccsr);
687
688 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
689 & RIO_PEF_CTLS) >> 4;
690 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
691 port->sys_size ? 65536 : 256);
692
693 if (port->host_deviceid >= 0)
694 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
695 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
696 else
697 out_be32(priv->regs_win + RIO_GCCSR,
698 RIO_PORT_GEN_MASTER);
699
700 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
701 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
702 RIO_ATMU_REGS_PORT2_OFFSET));
703
704 priv->maint_atmu_regs = priv->atmu_regs + 1;
705 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
706 (priv->regs_win +
707 ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
708 RIO_INB_ATMU_REGS_PORT2_OFFSET));
709
710 /* Set to receive packets with any dest ID */
711 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
712 RIO_ISR_AACR_AA);
713
714 /* Configure maintenance transaction window */
715 out_be32(&priv->maint_atmu_regs->rowbar,
716 port->iores.start >> 12);
717 out_be32(&priv->maint_atmu_regs->rowar,
718 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
719
720 priv->maint_win = ioremap(port->iores.start,
721 RIO_MAINT_WIN_SIZE);
722
723 rio_law_start = range_start;
724
725 fsl_rio_setup_rmu(port, rmu_np[i]);
726 fsl_rio_inbound_mem_init(priv);
727
728 dbell->mport[i] = port;
729 pw->mport[i] = port;
730
731 if (rio_register_mport(port)) {
732 release_resource(&port->iores);
733 kfree(priv);
734 kfree(port);
735 continue;
736 }
737 active_ports++;
738 }
739
740 if (!active_ports) {
741 rc = -ENOLINK;
742 goto err;
743 }
744
745 fsl_rio_doorbell_init(dbell);
746 fsl_rio_port_write_init(pw);
747
748 return 0;
749 err:
750 kfree(pw);
751 pw = NULL;
752 err_pw:
753 kfree(dbell);
754 dbell = NULL;
755 err_dbell:
756 iounmap(rmu_regs_win);
757 rmu_regs_win = NULL;
758 err_rmu:
759 kfree(ops);
760 err_ops:
761 iounmap(rio_regs_win);
762 rio_regs_win = NULL;
763 err_rio_regs:
764 return rc;
765 }
766
767 /* The probe function for RapidIO peer-to-peer network.
768 */
fsl_of_rio_rpn_probe(struct platform_device * dev)769 static int fsl_of_rio_rpn_probe(struct platform_device *dev)
770 {
771 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
772 dev->dev.of_node);
773
774 return fsl_rio_setup(dev);
775 };
776
777 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
778 {
779 .compatible = "fsl,srio",
780 },
781 {},
782 };
783
784 static struct platform_driver fsl_of_rio_rpn_driver = {
785 .driver = {
786 .name = "fsl-of-rio",
787 .of_match_table = fsl_of_rio_rpn_ids,
788 },
789 .probe = fsl_of_rio_rpn_probe,
790 };
791
fsl_of_rio_rpn_init(void)792 static __init int fsl_of_rio_rpn_init(void)
793 {
794 return platform_driver_register(&fsl_of_rio_rpn_driver);
795 }
796
797 subsys_initcall(fsl_of_rio_rpn_init);
798