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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2017 SiFive
4  */
5 
6 #include <asm/pgtable.h>
7 #include <asm/cacheflush.h>
8 
9 #ifdef CONFIG_SMP
10 
11 #include <asm/sbi.h>
12 
flush_icache_all(void)13 void flush_icache_all(void)
14 {
15 	sbi_remote_fence_i(NULL);
16 }
17 EXPORT_SYMBOL(flush_icache_all);
18 
19 /*
20  * Performs an icache flush for the given MM context.  RISC-V has no direct
21  * mechanism for instruction cache shoot downs, so instead we send an IPI that
22  * informs the remote harts they need to flush their local instruction caches.
23  * To avoid pathologically slow behavior in a common case (a bunch of
24  * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
25  * IPIs for harts that are not currently executing a MM context and instead
26  * schedule a deferred local instruction cache flush to be performed before
27  * execution resumes on each hart.
28  */
flush_icache_mm(struct mm_struct * mm,bool local)29 void flush_icache_mm(struct mm_struct *mm, bool local)
30 {
31 	unsigned int cpu;
32 	cpumask_t others, hmask, *mask;
33 
34 	preempt_disable();
35 
36 	/* Mark every hart's icache as needing a flush for this MM. */
37 	mask = &mm->context.icache_stale_mask;
38 	cpumask_setall(mask);
39 	/* Flush this hart's I$ now, and mark it as flushed. */
40 	cpu = smp_processor_id();
41 	cpumask_clear_cpu(cpu, mask);
42 	local_flush_icache_all();
43 
44 	/*
45 	 * Flush the I$ of other harts concurrently executing, and mark them as
46 	 * flushed.
47 	 */
48 	cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
49 	local |= cpumask_empty(&others);
50 	if (mm != current->active_mm || !local) {
51 		riscv_cpuid_to_hartid_mask(&others, &hmask);
52 		sbi_remote_fence_i(hmask.bits);
53 	} else {
54 		/*
55 		 * It's assumed that at least one strongly ordered operation is
56 		 * performed on this hart between setting a hart's cpumask bit
57 		 * and scheduling this MM context on that hart.  Sending an SBI
58 		 * remote message will do this, but in the case where no
59 		 * messages are sent we still need to order this hart's writes
60 		 * with flush_icache_deferred().
61 		 */
62 		smp_mb();
63 	}
64 
65 	preempt_enable();
66 }
67 
68 #endif /* CONFIG_SMP */
69 
flush_icache_pte(pte_t pte)70 void flush_icache_pte(pte_t pte)
71 {
72 	struct page *page = pte_page(pte);
73 
74 	if (!test_bit(PG_dcache_clean, &page->flags)) {
75 		flush_icache_all();
76 		set_bit(PG_dcache_clean, &page->flags);
77 	}
78 }
79