1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BPF Jit compiler for s390.
4 *
5 * Minimum build requirements:
6 *
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
10 * - PACK_STACK
11 * - 64BIT
12 *
13 * Copyright IBM Corp. 2012,2015
14 *
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
17 */
18
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <linux/mm.h>
27 #include <asm/cacheflush.h>
28 #include <asm/dis.h>
29 #include <asm/facility.h>
30 #include <asm/nospec-branch.h>
31 #include <asm/set_memory.h>
32 #include "bpf_jit.h"
33
34 struct bpf_jit {
35 u32 seen; /* Flags to remember seen eBPF instructions */
36 u32 seen_reg[16]; /* Array to remember which registers are used */
37 u32 *addrs; /* Array with relative instruction addresses */
38 u8 *prg_buf; /* Start of program */
39 int size; /* Size of program and literal pool */
40 int size_prg; /* Size of program */
41 int prg; /* Current position in program */
42 int lit_start; /* Start of literal pool */
43 int lit; /* Current position in literal pool */
44 int base_ip; /* Base address for literal pool */
45 int ret0_ip; /* Address of return 0 */
46 int exit_ip; /* Address of exit */
47 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
48 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
49 int tail_call_start; /* Tail call start offset */
50 int labels[1]; /* Labels for local jumps */
51 };
52
53 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
54
55 #define SEEN_MEM (1 << 0) /* use mem[] for temporary storage */
56 #define SEEN_RET0 (1 << 1) /* ret0_ip points to a valid return 0 */
57 #define SEEN_LITERAL (1 << 2) /* code uses literals */
58 #define SEEN_FUNC (1 << 3) /* calls C functions */
59 #define SEEN_TAIL_CALL (1 << 4) /* code uses tail calls */
60 #define SEEN_REG_AX (1 << 5) /* code uses constant blinding */
61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
62
63 /*
64 * s390 registers
65 */
66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
67 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
68 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
69 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
70 #define REG_0 REG_W0 /* Register 0 */
71 #define REG_1 REG_W1 /* Register 1 */
72 #define REG_2 BPF_REG_1 /* Register 2 */
73 #define REG_14 BPF_REG_0 /* Register 14 */
74
75 /*
76 * Mapping of BPF registers to s390 registers
77 */
78 static const int reg2hex[] = {
79 /* Return code */
80 [BPF_REG_0] = 14,
81 /* Function parameters */
82 [BPF_REG_1] = 2,
83 [BPF_REG_2] = 3,
84 [BPF_REG_3] = 4,
85 [BPF_REG_4] = 5,
86 [BPF_REG_5] = 6,
87 /* Call saved registers */
88 [BPF_REG_6] = 7,
89 [BPF_REG_7] = 8,
90 [BPF_REG_8] = 9,
91 [BPF_REG_9] = 10,
92 /* BPF stack pointer */
93 [BPF_REG_FP] = 13,
94 /* Register for blinding */
95 [BPF_REG_AX] = 12,
96 /* Work registers for s390x backend */
97 [REG_W0] = 0,
98 [REG_W1] = 1,
99 [REG_L] = 11,
100 [REG_15] = 15,
101 };
102
reg(u32 dst_reg,u32 src_reg)103 static inline u32 reg(u32 dst_reg, u32 src_reg)
104 {
105 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
106 }
107
reg_high(u32 reg)108 static inline u32 reg_high(u32 reg)
109 {
110 return reg2hex[reg] << 4;
111 }
112
reg_set_seen(struct bpf_jit * jit,u32 b1)113 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
114 {
115 u32 r1 = reg2hex[b1];
116
117 if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1])
118 jit->seen_reg[r1] = 1;
119 }
120
121 #define REG_SET_SEEN(b1) \
122 ({ \
123 reg_set_seen(jit, b1); \
124 })
125
126 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
127
128 /*
129 * EMIT macros for code generation
130 */
131
132 #define _EMIT2(op) \
133 ({ \
134 if (jit->prg_buf) \
135 *(u16 *) (jit->prg_buf + jit->prg) = op; \
136 jit->prg += 2; \
137 })
138
139 #define EMIT2(op, b1, b2) \
140 ({ \
141 _EMIT2(op | reg(b1, b2)); \
142 REG_SET_SEEN(b1); \
143 REG_SET_SEEN(b2); \
144 })
145
146 #define _EMIT4(op) \
147 ({ \
148 if (jit->prg_buf) \
149 *(u32 *) (jit->prg_buf + jit->prg) = op; \
150 jit->prg += 4; \
151 })
152
153 #define EMIT4(op, b1, b2) \
154 ({ \
155 _EMIT4(op | reg(b1, b2)); \
156 REG_SET_SEEN(b1); \
157 REG_SET_SEEN(b2); \
158 })
159
160 #define EMIT4_RRF(op, b1, b2, b3) \
161 ({ \
162 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
163 REG_SET_SEEN(b1); \
164 REG_SET_SEEN(b2); \
165 REG_SET_SEEN(b3); \
166 })
167
168 #define _EMIT4_DISP(op, disp) \
169 ({ \
170 unsigned int __disp = (disp) & 0xfff; \
171 _EMIT4(op | __disp); \
172 })
173
174 #define EMIT4_DISP(op, b1, b2, disp) \
175 ({ \
176 _EMIT4_DISP(op | reg_high(b1) << 16 | \
177 reg_high(b2) << 8, disp); \
178 REG_SET_SEEN(b1); \
179 REG_SET_SEEN(b2); \
180 })
181
182 #define EMIT4_IMM(op, b1, imm) \
183 ({ \
184 unsigned int __imm = (imm) & 0xffff; \
185 _EMIT4(op | reg_high(b1) << 16 | __imm); \
186 REG_SET_SEEN(b1); \
187 })
188
189 #define EMIT4_PCREL(op, pcrel) \
190 ({ \
191 long __pcrel = ((pcrel) >> 1) & 0xffff; \
192 _EMIT4(op | __pcrel); \
193 })
194
195 #define _EMIT6(op1, op2) \
196 ({ \
197 if (jit->prg_buf) { \
198 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
199 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
200 } \
201 jit->prg += 6; \
202 })
203
204 #define _EMIT6_DISP(op1, op2, disp) \
205 ({ \
206 unsigned int __disp = (disp) & 0xfff; \
207 _EMIT6(op1 | __disp, op2); \
208 })
209
210 #define _EMIT6_DISP_LH(op1, op2, disp) \
211 ({ \
212 u32 _disp = (u32) disp; \
213 unsigned int __disp_h = _disp & 0xff000; \
214 unsigned int __disp_l = _disp & 0x00fff; \
215 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
216 })
217
218 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
219 ({ \
220 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
221 reg_high(b3) << 8, op2, disp); \
222 REG_SET_SEEN(b1); \
223 REG_SET_SEEN(b2); \
224 REG_SET_SEEN(b3); \
225 })
226
227 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
228 ({ \
229 int rel = (jit->labels[label] - jit->prg) >> 1; \
230 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
231 op2 | mask << 12); \
232 REG_SET_SEEN(b1); \
233 REG_SET_SEEN(b2); \
234 })
235
236 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
237 ({ \
238 int rel = (jit->labels[label] - jit->prg) >> 1; \
239 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
240 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
241 REG_SET_SEEN(b1); \
242 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
243 })
244
245 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
246 ({ \
247 /* Branch instruction needs 6 bytes */ \
248 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
249 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
250 REG_SET_SEEN(b1); \
251 REG_SET_SEEN(b2); \
252 })
253
254 #define EMIT6_PCREL_RILB(op, b, target) \
255 ({ \
256 int rel = (target - jit->prg) / 2; \
257 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
258 REG_SET_SEEN(b); \
259 })
260
261 #define EMIT6_PCREL_RIL(op, target) \
262 ({ \
263 int rel = (target - jit->prg) / 2; \
264 _EMIT6(op | rel >> 16, rel & 0xffff); \
265 })
266
267 #define _EMIT6_IMM(op, imm) \
268 ({ \
269 unsigned int __imm = (imm); \
270 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
271 })
272
273 #define EMIT6_IMM(op, b1, imm) \
274 ({ \
275 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
276 REG_SET_SEEN(b1); \
277 })
278
279 #define EMIT_CONST_U32(val) \
280 ({ \
281 unsigned int ret; \
282 ret = jit->lit - jit->base_ip; \
283 jit->seen |= SEEN_LITERAL; \
284 if (jit->prg_buf) \
285 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
286 jit->lit += 4; \
287 ret; \
288 })
289
290 #define EMIT_CONST_U64(val) \
291 ({ \
292 unsigned int ret; \
293 ret = jit->lit - jit->base_ip; \
294 jit->seen |= SEEN_LITERAL; \
295 if (jit->prg_buf) \
296 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
297 jit->lit += 8; \
298 ret; \
299 })
300
301 #define EMIT_ZERO(b1) \
302 ({ \
303 if (!fp->aux->verifier_zext) { \
304 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
305 EMIT4(0xb9160000, b1, b1); \
306 REG_SET_SEEN(b1); \
307 } \
308 })
309
310 /*
311 * Fill whole space with illegal instructions
312 */
jit_fill_hole(void * area,unsigned int size)313 static void jit_fill_hole(void *area, unsigned int size)
314 {
315 memset(area, 0, size);
316 }
317
318 /*
319 * Save registers from "rs" (register start) to "re" (register end) on stack
320 */
save_regs(struct bpf_jit * jit,u32 rs,u32 re)321 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
322 {
323 u32 off = STK_OFF_R6 + (rs - 6) * 8;
324
325 if (rs == re)
326 /* stg %rs,off(%r15) */
327 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
328 else
329 /* stmg %rs,%re,off(%r15) */
330 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
331 }
332
333 /*
334 * Restore registers from "rs" (register start) to "re" (register end) on stack
335 */
restore_regs(struct bpf_jit * jit,u32 rs,u32 re,u32 stack_depth)336 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
337 {
338 u32 off = STK_OFF_R6 + (rs - 6) * 8;
339
340 if (jit->seen & SEEN_STACK)
341 off += STK_OFF + stack_depth;
342
343 if (rs == re)
344 /* lg %rs,off(%r15) */
345 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
346 else
347 /* lmg %rs,%re,off(%r15) */
348 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
349 }
350
351 /*
352 * Return first seen register (from start)
353 */
get_start(struct bpf_jit * jit,int start)354 static int get_start(struct bpf_jit *jit, int start)
355 {
356 int i;
357
358 for (i = start; i <= 15; i++) {
359 if (jit->seen_reg[i])
360 return i;
361 }
362 return 0;
363 }
364
365 /*
366 * Return last seen register (from start) (gap >= 2)
367 */
get_end(struct bpf_jit * jit,int start)368 static int get_end(struct bpf_jit *jit, int start)
369 {
370 int i;
371
372 for (i = start; i < 15; i++) {
373 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
374 return i - 1;
375 }
376 return jit->seen_reg[15] ? 15 : 14;
377 }
378
379 #define REGS_SAVE 1
380 #define REGS_RESTORE 0
381 /*
382 * Save and restore clobbered registers (6-15) on stack.
383 * We save/restore registers in chunks with gap >= 2 registers.
384 */
save_restore_regs(struct bpf_jit * jit,int op,u32 stack_depth)385 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
386 {
387
388 int re = 6, rs;
389
390 do {
391 rs = get_start(jit, re);
392 if (!rs)
393 break;
394 re = get_end(jit, rs + 1);
395 if (op == REGS_SAVE)
396 save_regs(jit, rs, re);
397 else
398 restore_regs(jit, rs, re, stack_depth);
399 re++;
400 } while (re <= 15);
401 }
402
403 /*
404 * Emit function prologue
405 *
406 * Save registers and create stack frame if necessary.
407 * See stack frame layout desription in "bpf_jit.h"!
408 */
bpf_jit_prologue(struct bpf_jit * jit,u32 stack_depth)409 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
410 {
411 if (jit->seen & SEEN_TAIL_CALL) {
412 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
413 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
414 } else {
415 /* j tail_call_start: NOP if no tail calls are used */
416 EMIT4_PCREL(0xa7f40000, 6);
417 _EMIT2(0);
418 }
419 /* Tail calls have to skip above initialization */
420 jit->tail_call_start = jit->prg;
421 /* Save registers */
422 save_restore_regs(jit, REGS_SAVE, stack_depth);
423 /* Setup literal pool */
424 if (jit->seen & SEEN_LITERAL) {
425 /* basr %r13,0 */
426 EMIT2(0x0d00, REG_L, REG_0);
427 jit->base_ip = jit->prg;
428 }
429 /* Setup stack and backchain */
430 if (jit->seen & SEEN_STACK) {
431 if (jit->seen & SEEN_FUNC)
432 /* lgr %w1,%r15 (backchain) */
433 EMIT4(0xb9040000, REG_W1, REG_15);
434 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
435 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
436 /* aghi %r15,-STK_OFF */
437 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
438 if (jit->seen & SEEN_FUNC)
439 /* stg %w1,152(%r15) (backchain) */
440 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
441 REG_15, 152);
442 }
443 }
444
445 /*
446 * Function epilogue
447 */
bpf_jit_epilogue(struct bpf_jit * jit,u32 stack_depth)448 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
449 {
450 /* Return 0 */
451 if (jit->seen & SEEN_RET0) {
452 jit->ret0_ip = jit->prg;
453 /* lghi %b0,0 */
454 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
455 }
456 jit->exit_ip = jit->prg;
457 /* Load exit code: lgr %r2,%b0 */
458 EMIT4(0xb9040000, REG_2, BPF_REG_0);
459 /* Restore registers */
460 save_restore_regs(jit, REGS_RESTORE, stack_depth);
461 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
462 jit->r14_thunk_ip = jit->prg;
463 /* Generate __s390_indirect_jump_r14 thunk */
464 if (test_facility(35)) {
465 /* exrl %r0,.+10 */
466 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
467 } else {
468 /* larl %r1,.+14 */
469 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
470 /* ex 0,0(%r1) */
471 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
472 }
473 /* j . */
474 EMIT4_PCREL(0xa7f40000, 0);
475 }
476 /* br %r14 */
477 _EMIT2(0x07fe);
478
479 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
480 (jit->seen & SEEN_FUNC)) {
481 jit->r1_thunk_ip = jit->prg;
482 /* Generate __s390_indirect_jump_r1 thunk */
483 if (test_facility(35)) {
484 /* exrl %r0,.+10 */
485 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
486 /* j . */
487 EMIT4_PCREL(0xa7f40000, 0);
488 /* br %r1 */
489 _EMIT2(0x07f1);
490 } else {
491 /* ex 0,S390_lowcore.br_r1_tampoline */
492 EMIT4_DISP(0x44000000, REG_0, REG_0,
493 offsetof(struct lowcore, br_r1_trampoline));
494 /* j . */
495 EMIT4_PCREL(0xa7f40000, 0);
496 }
497 }
498 }
499
500 /*
501 * Compile one eBPF instruction into s390x code
502 *
503 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
504 * stack space for the large switch statement.
505 */
bpf_jit_insn(struct bpf_jit * jit,struct bpf_prog * fp,int i,bool extra_pass)506 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
507 int i, bool extra_pass)
508 {
509 struct bpf_insn *insn = &fp->insnsi[i];
510 int jmp_off, last, insn_count = 1;
511 u32 dst_reg = insn->dst_reg;
512 u32 src_reg = insn->src_reg;
513 u32 *addrs = jit->addrs;
514 s32 imm = insn->imm;
515 s16 off = insn->off;
516 unsigned int mask;
517
518 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
519 jit->seen |= SEEN_REG_AX;
520 switch (insn->code) {
521 /*
522 * BPF_MOV
523 */
524 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
525 /* llgfr %dst,%src */
526 EMIT4(0xb9160000, dst_reg, src_reg);
527 if (insn_is_zext(&insn[1]))
528 insn_count = 2;
529 break;
530 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
531 /* lgr %dst,%src */
532 EMIT4(0xb9040000, dst_reg, src_reg);
533 break;
534 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
535 /* llilf %dst,imm */
536 EMIT6_IMM(0xc00f0000, dst_reg, imm);
537 if (insn_is_zext(&insn[1]))
538 insn_count = 2;
539 break;
540 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
541 /* lgfi %dst,imm */
542 EMIT6_IMM(0xc0010000, dst_reg, imm);
543 break;
544 /*
545 * BPF_LD 64
546 */
547 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
548 {
549 /* 16 byte instruction that uses two 'struct bpf_insn' */
550 u64 imm64;
551
552 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
553 /* lg %dst,<d(imm)>(%l) */
554 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
555 EMIT_CONST_U64(imm64));
556 insn_count = 2;
557 break;
558 }
559 /*
560 * BPF_ADD
561 */
562 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
563 /* ar %dst,%src */
564 EMIT2(0x1a00, dst_reg, src_reg);
565 EMIT_ZERO(dst_reg);
566 break;
567 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
568 /* agr %dst,%src */
569 EMIT4(0xb9080000, dst_reg, src_reg);
570 break;
571 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
572 if (imm != 0) {
573 /* alfi %dst,imm */
574 EMIT6_IMM(0xc20b0000, dst_reg, imm);
575 }
576 EMIT_ZERO(dst_reg);
577 break;
578 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
579 if (!imm)
580 break;
581 /* agfi %dst,imm */
582 EMIT6_IMM(0xc2080000, dst_reg, imm);
583 break;
584 /*
585 * BPF_SUB
586 */
587 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
588 /* sr %dst,%src */
589 EMIT2(0x1b00, dst_reg, src_reg);
590 EMIT_ZERO(dst_reg);
591 break;
592 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
593 /* sgr %dst,%src */
594 EMIT4(0xb9090000, dst_reg, src_reg);
595 break;
596 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
597 if (imm != 0) {
598 /* alfi %dst,-imm */
599 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
600 }
601 EMIT_ZERO(dst_reg);
602 break;
603 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
604 if (!imm)
605 break;
606 if (imm == -0x80000000) {
607 /* algfi %dst,0x80000000 */
608 EMIT6_IMM(0xc20a0000, dst_reg, 0x80000000);
609 } else {
610 /* agfi %dst,-imm */
611 EMIT6_IMM(0xc2080000, dst_reg, -imm);
612 }
613 break;
614 /*
615 * BPF_MUL
616 */
617 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
618 /* msr %dst,%src */
619 EMIT4(0xb2520000, dst_reg, src_reg);
620 EMIT_ZERO(dst_reg);
621 break;
622 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
623 /* msgr %dst,%src */
624 EMIT4(0xb90c0000, dst_reg, src_reg);
625 break;
626 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
627 if (imm != 1) {
628 /* msfi %r5,imm */
629 EMIT6_IMM(0xc2010000, dst_reg, imm);
630 }
631 EMIT_ZERO(dst_reg);
632 break;
633 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
634 if (imm == 1)
635 break;
636 /* msgfi %dst,imm */
637 EMIT6_IMM(0xc2000000, dst_reg, imm);
638 break;
639 /*
640 * BPF_DIV / BPF_MOD
641 */
642 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
643 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
644 {
645 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
646
647 /* lhi %w0,0 */
648 EMIT4_IMM(0xa7080000, REG_W0, 0);
649 /* lr %w1,%dst */
650 EMIT2(0x1800, REG_W1, dst_reg);
651 /* dlr %w0,%src */
652 EMIT4(0xb9970000, REG_W0, src_reg);
653 /* llgfr %dst,%rc */
654 EMIT4(0xb9160000, dst_reg, rc_reg);
655 if (insn_is_zext(&insn[1]))
656 insn_count = 2;
657 break;
658 }
659 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
660 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
661 {
662 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
663
664 /* lghi %w0,0 */
665 EMIT4_IMM(0xa7090000, REG_W0, 0);
666 /* lgr %w1,%dst */
667 EMIT4(0xb9040000, REG_W1, dst_reg);
668 /* dlgr %w0,%dst */
669 EMIT4(0xb9870000, REG_W0, src_reg);
670 /* lgr %dst,%rc */
671 EMIT4(0xb9040000, dst_reg, rc_reg);
672 break;
673 }
674 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
675 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
676 {
677 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
678
679 if (imm == 1) {
680 if (BPF_OP(insn->code) == BPF_MOD)
681 /* lhgi %dst,0 */
682 EMIT4_IMM(0xa7090000, dst_reg, 0);
683 else
684 EMIT_ZERO(dst_reg);
685 break;
686 }
687 /* lhi %w0,0 */
688 EMIT4_IMM(0xa7080000, REG_W0, 0);
689 /* lr %w1,%dst */
690 EMIT2(0x1800, REG_W1, dst_reg);
691 /* dl %w0,<d(imm)>(%l) */
692 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
693 EMIT_CONST_U32(imm));
694 /* llgfr %dst,%rc */
695 EMIT4(0xb9160000, dst_reg, rc_reg);
696 if (insn_is_zext(&insn[1]))
697 insn_count = 2;
698 break;
699 }
700 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
701 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
702 {
703 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
704
705 if (imm == 1) {
706 if (BPF_OP(insn->code) == BPF_MOD)
707 /* lhgi %dst,0 */
708 EMIT4_IMM(0xa7090000, dst_reg, 0);
709 break;
710 }
711 /* lghi %w0,0 */
712 EMIT4_IMM(0xa7090000, REG_W0, 0);
713 /* lgr %w1,%dst */
714 EMIT4(0xb9040000, REG_W1, dst_reg);
715 /* dlg %w0,<d(imm)>(%l) */
716 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
717 EMIT_CONST_U64(imm));
718 /* lgr %dst,%rc */
719 EMIT4(0xb9040000, dst_reg, rc_reg);
720 break;
721 }
722 /*
723 * BPF_AND
724 */
725 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
726 /* nr %dst,%src */
727 EMIT2(0x1400, dst_reg, src_reg);
728 EMIT_ZERO(dst_reg);
729 break;
730 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
731 /* ngr %dst,%src */
732 EMIT4(0xb9800000, dst_reg, src_reg);
733 break;
734 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
735 /* nilf %dst,imm */
736 EMIT6_IMM(0xc00b0000, dst_reg, imm);
737 EMIT_ZERO(dst_reg);
738 break;
739 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
740 /* ng %dst,<d(imm)>(%l) */
741 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
742 EMIT_CONST_U64(imm));
743 break;
744 /*
745 * BPF_OR
746 */
747 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
748 /* or %dst,%src */
749 EMIT2(0x1600, dst_reg, src_reg);
750 EMIT_ZERO(dst_reg);
751 break;
752 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
753 /* ogr %dst,%src */
754 EMIT4(0xb9810000, dst_reg, src_reg);
755 break;
756 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
757 /* oilf %dst,imm */
758 EMIT6_IMM(0xc00d0000, dst_reg, imm);
759 EMIT_ZERO(dst_reg);
760 break;
761 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
762 /* og %dst,<d(imm)>(%l) */
763 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
764 EMIT_CONST_U64(imm));
765 break;
766 /*
767 * BPF_XOR
768 */
769 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
770 /* xr %dst,%src */
771 EMIT2(0x1700, dst_reg, src_reg);
772 EMIT_ZERO(dst_reg);
773 break;
774 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
775 /* xgr %dst,%src */
776 EMIT4(0xb9820000, dst_reg, src_reg);
777 break;
778 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
779 if (imm != 0) {
780 /* xilf %dst,imm */
781 EMIT6_IMM(0xc0070000, dst_reg, imm);
782 }
783 EMIT_ZERO(dst_reg);
784 break;
785 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
786 /* xg %dst,<d(imm)>(%l) */
787 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
788 EMIT_CONST_U64(imm));
789 break;
790 /*
791 * BPF_LSH
792 */
793 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
794 /* sll %dst,0(%src) */
795 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
796 EMIT_ZERO(dst_reg);
797 break;
798 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
799 /* sllg %dst,%dst,0(%src) */
800 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
801 break;
802 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
803 if (imm != 0) {
804 /* sll %dst,imm(%r0) */
805 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
806 }
807 EMIT_ZERO(dst_reg);
808 break;
809 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
810 if (imm == 0)
811 break;
812 /* sllg %dst,%dst,imm(%r0) */
813 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
814 break;
815 /*
816 * BPF_RSH
817 */
818 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
819 /* srl %dst,0(%src) */
820 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
821 EMIT_ZERO(dst_reg);
822 break;
823 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
824 /* srlg %dst,%dst,0(%src) */
825 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
826 break;
827 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
828 if (imm != 0) {
829 /* srl %dst,imm(%r0) */
830 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
831 }
832 EMIT_ZERO(dst_reg);
833 break;
834 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
835 if (imm == 0)
836 break;
837 /* srlg %dst,%dst,imm(%r0) */
838 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
839 break;
840 /*
841 * BPF_ARSH
842 */
843 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
844 /* sra %dst,%dst,0(%src) */
845 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
846 EMIT_ZERO(dst_reg);
847 break;
848 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
849 /* srag %dst,%dst,0(%src) */
850 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
851 break;
852 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
853 if (imm != 0) {
854 /* sra %dst,imm(%r0) */
855 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
856 }
857 EMIT_ZERO(dst_reg);
858 break;
859 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
860 if (imm == 0)
861 break;
862 /* srag %dst,%dst,imm(%r0) */
863 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
864 break;
865 /*
866 * BPF_NEG
867 */
868 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
869 /* lcr %dst,%dst */
870 EMIT2(0x1300, dst_reg, dst_reg);
871 EMIT_ZERO(dst_reg);
872 break;
873 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
874 /* lcgr %dst,%dst */
875 EMIT4(0xb9030000, dst_reg, dst_reg);
876 break;
877 /*
878 * BPF_FROM_BE/LE
879 */
880 case BPF_ALU | BPF_END | BPF_FROM_BE:
881 /* s390 is big endian, therefore only clear high order bytes */
882 switch (imm) {
883 case 16: /* dst = (u16) cpu_to_be16(dst) */
884 /* llghr %dst,%dst */
885 EMIT4(0xb9850000, dst_reg, dst_reg);
886 if (insn_is_zext(&insn[1]))
887 insn_count = 2;
888 break;
889 case 32: /* dst = (u32) cpu_to_be32(dst) */
890 if (!fp->aux->verifier_zext)
891 /* llgfr %dst,%dst */
892 EMIT4(0xb9160000, dst_reg, dst_reg);
893 break;
894 case 64: /* dst = (u64) cpu_to_be64(dst) */
895 break;
896 }
897 break;
898 case BPF_ALU | BPF_END | BPF_FROM_LE:
899 switch (imm) {
900 case 16: /* dst = (u16) cpu_to_le16(dst) */
901 /* lrvr %dst,%dst */
902 EMIT4(0xb91f0000, dst_reg, dst_reg);
903 /* srl %dst,16(%r0) */
904 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
905 /* llghr %dst,%dst */
906 EMIT4(0xb9850000, dst_reg, dst_reg);
907 if (insn_is_zext(&insn[1]))
908 insn_count = 2;
909 break;
910 case 32: /* dst = (u32) cpu_to_le32(dst) */
911 /* lrvr %dst,%dst */
912 EMIT4(0xb91f0000, dst_reg, dst_reg);
913 if (!fp->aux->verifier_zext)
914 /* llgfr %dst,%dst */
915 EMIT4(0xb9160000, dst_reg, dst_reg);
916 break;
917 case 64: /* dst = (u64) cpu_to_le64(dst) */
918 /* lrvgr %dst,%dst */
919 EMIT4(0xb90f0000, dst_reg, dst_reg);
920 break;
921 }
922 break;
923 /*
924 * BPF_NOSPEC (speculation barrier)
925 */
926 case BPF_ST | BPF_NOSPEC:
927 break;
928 /*
929 * BPF_ST(X)
930 */
931 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
932 /* stcy %src,off(%dst) */
933 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
934 jit->seen |= SEEN_MEM;
935 break;
936 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
937 /* sthy %src,off(%dst) */
938 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
939 jit->seen |= SEEN_MEM;
940 break;
941 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
942 /* sty %src,off(%dst) */
943 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
944 jit->seen |= SEEN_MEM;
945 break;
946 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
947 /* stg %src,off(%dst) */
948 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
949 jit->seen |= SEEN_MEM;
950 break;
951 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
952 /* lhi %w0,imm */
953 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
954 /* stcy %w0,off(dst) */
955 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
956 jit->seen |= SEEN_MEM;
957 break;
958 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
959 /* lhi %w0,imm */
960 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
961 /* sthy %w0,off(dst) */
962 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
963 jit->seen |= SEEN_MEM;
964 break;
965 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
966 /* llilf %w0,imm */
967 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
968 /* sty %w0,off(%dst) */
969 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
970 jit->seen |= SEEN_MEM;
971 break;
972 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
973 /* lgfi %w0,imm */
974 EMIT6_IMM(0xc0010000, REG_W0, imm);
975 /* stg %w0,off(%dst) */
976 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
977 jit->seen |= SEEN_MEM;
978 break;
979 /*
980 * BPF_STX XADD (atomic_add)
981 */
982 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
983 /* laal %w0,%src,off(%dst) */
984 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
985 dst_reg, off);
986 jit->seen |= SEEN_MEM;
987 break;
988 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
989 /* laalg %w0,%src,off(%dst) */
990 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
991 dst_reg, off);
992 jit->seen |= SEEN_MEM;
993 break;
994 /*
995 * BPF_LDX
996 */
997 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
998 /* llgc %dst,0(off,%src) */
999 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1000 jit->seen |= SEEN_MEM;
1001 if (insn_is_zext(&insn[1]))
1002 insn_count = 2;
1003 break;
1004 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1005 /* llgh %dst,0(off,%src) */
1006 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1007 jit->seen |= SEEN_MEM;
1008 if (insn_is_zext(&insn[1]))
1009 insn_count = 2;
1010 break;
1011 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1012 /* llgf %dst,off(%src) */
1013 jit->seen |= SEEN_MEM;
1014 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1015 if (insn_is_zext(&insn[1]))
1016 insn_count = 2;
1017 break;
1018 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1019 /* lg %dst,0(off,%src) */
1020 jit->seen |= SEEN_MEM;
1021 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1022 break;
1023 /*
1024 * BPF_JMP / CALL
1025 */
1026 case BPF_JMP | BPF_CALL:
1027 {
1028 u64 func;
1029 bool func_addr_fixed;
1030 int ret;
1031
1032 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1033 &func, &func_addr_fixed);
1034 if (ret < 0)
1035 return -1;
1036
1037 REG_SET_SEEN(BPF_REG_5);
1038 jit->seen |= SEEN_FUNC;
1039 /* lg %w1,<d(imm)>(%l) */
1040 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1041 EMIT_CONST_U64(func));
1042 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1043 /* brasl %r14,__s390_indirect_jump_r1 */
1044 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1045 } else {
1046 /* basr %r14,%w1 */
1047 EMIT2(0x0d00, REG_14, REG_W1);
1048 }
1049 /* lgr %b0,%r2: load return value into %b0 */
1050 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1051 break;
1052 }
1053 case BPF_JMP | BPF_TAIL_CALL:
1054 /*
1055 * Implicit input:
1056 * B1: pointer to ctx
1057 * B2: pointer to bpf_array
1058 * B3: index in bpf_array
1059 */
1060 jit->seen |= SEEN_TAIL_CALL;
1061
1062 /*
1063 * if (index >= array->map.max_entries)
1064 * goto out;
1065 */
1066
1067 /* llgf %w1,map.max_entries(%b2) */
1068 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1069 offsetof(struct bpf_array, map.max_entries));
1070 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1071 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1072 REG_W1, 0, 0xa);
1073
1074 /*
1075 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1076 * goto out;
1077 */
1078
1079 if (jit->seen & SEEN_STACK)
1080 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth;
1081 else
1082 off = STK_OFF_TCCNT;
1083 /* lhi %w0,1 */
1084 EMIT4_IMM(0xa7080000, REG_W0, 1);
1085 /* laal %w1,%w0,off(%r15) */
1086 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1087 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1088 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1089 MAX_TAIL_CALL_CNT, 0, 0x2);
1090
1091 /*
1092 * prog = array->ptrs[index];
1093 * if (prog == NULL)
1094 * goto out;
1095 */
1096
1097 /* llgfr %r1,%b3: %r1 = (u32) index */
1098 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1099 /* sllg %r1,%r1,3: %r1 *= 8 */
1100 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1101 /* lg %r1,prog(%b2,%r1) */
1102 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1103 REG_1, offsetof(struct bpf_array, ptrs));
1104 /* clgij %r1,0,0x8,label0 */
1105 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1106
1107 /*
1108 * Restore registers before calling function
1109 */
1110 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth);
1111
1112 /*
1113 * goto *(prog->bpf_func + tail_call_start);
1114 */
1115
1116 /* lg %r1,bpf_func(%r1) */
1117 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1118 offsetof(struct bpf_prog, bpf_func));
1119 /* bc 0xf,tail_call_start(%r1) */
1120 _EMIT4(0x47f01000 + jit->tail_call_start);
1121 /* out: */
1122 jit->labels[0] = jit->prg;
1123 break;
1124 case BPF_JMP | BPF_EXIT: /* return b0 */
1125 last = (i == fp->len - 1) ? 1 : 0;
1126 if (last && !(jit->seen & SEEN_RET0))
1127 break;
1128 /* j <exit> */
1129 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1130 break;
1131 /*
1132 * Branch relative (number of skipped instructions) to offset on
1133 * condition.
1134 *
1135 * Condition code to mask mapping:
1136 *
1137 * CC | Description | Mask
1138 * ------------------------------
1139 * 0 | Operands equal | 8
1140 * 1 | First operand low | 4
1141 * 2 | First operand high | 2
1142 * 3 | Unused | 1
1143 *
1144 * For s390x relative branches: ip = ip + off_bytes
1145 * For BPF relative branches: insn = insn + off_insns + 1
1146 *
1147 * For example for s390x with offset 0 we jump to the branch
1148 * instruction itself (loop) and for BPF with offset 0 we
1149 * branch to the instruction behind the branch.
1150 */
1151 case BPF_JMP | BPF_JA: /* if (true) */
1152 mask = 0xf000; /* j */
1153 goto branch_oc;
1154 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1155 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1156 mask = 0x2000; /* jh */
1157 goto branch_ks;
1158 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1159 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1160 mask = 0x4000; /* jl */
1161 goto branch_ks;
1162 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1163 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1164 mask = 0xa000; /* jhe */
1165 goto branch_ks;
1166 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1167 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1168 mask = 0xc000; /* jle */
1169 goto branch_ks;
1170 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1171 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1172 mask = 0x2000; /* jh */
1173 goto branch_ku;
1174 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1175 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1176 mask = 0x4000; /* jl */
1177 goto branch_ku;
1178 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1179 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1180 mask = 0xa000; /* jhe */
1181 goto branch_ku;
1182 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1183 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1184 mask = 0xc000; /* jle */
1185 goto branch_ku;
1186 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1187 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1188 mask = 0x7000; /* jne */
1189 goto branch_ku;
1190 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1191 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1192 mask = 0x8000; /* je */
1193 goto branch_ku;
1194 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1195 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1196 mask = 0x7000; /* jnz */
1197 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1198 /* llilf %w1,imm (load zero extend imm) */
1199 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1200 /* nr %w1,%dst */
1201 EMIT2(0x1400, REG_W1, dst_reg);
1202 } else {
1203 /* lgfi %w1,imm (load sign extend imm) */
1204 EMIT6_IMM(0xc0010000, REG_W1, imm);
1205 /* ngr %w1,%dst */
1206 EMIT4(0xb9800000, REG_W1, dst_reg);
1207 }
1208 goto branch_oc;
1209
1210 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1211 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1212 mask = 0x2000; /* jh */
1213 goto branch_xs;
1214 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1215 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1216 mask = 0x4000; /* jl */
1217 goto branch_xs;
1218 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1219 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1220 mask = 0xa000; /* jhe */
1221 goto branch_xs;
1222 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1223 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1224 mask = 0xc000; /* jle */
1225 goto branch_xs;
1226 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1227 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1228 mask = 0x2000; /* jh */
1229 goto branch_xu;
1230 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1231 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1232 mask = 0x4000; /* jl */
1233 goto branch_xu;
1234 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1235 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1236 mask = 0xa000; /* jhe */
1237 goto branch_xu;
1238 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1239 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1240 mask = 0xc000; /* jle */
1241 goto branch_xu;
1242 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1243 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1244 mask = 0x7000; /* jne */
1245 goto branch_xu;
1246 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1247 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1248 mask = 0x8000; /* je */
1249 goto branch_xu;
1250 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1251 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1252 {
1253 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1254
1255 mask = 0x7000; /* jnz */
1256 /* nrk or ngrk %w1,%dst,%src */
1257 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1258 REG_W1, dst_reg, src_reg);
1259 goto branch_oc;
1260 branch_ks:
1261 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1262 /* lgfi %w1,imm (load sign extend imm) */
1263 EMIT6_IMM(0xc0010000, REG_W1, imm);
1264 /* crj or cgrj %dst,%w1,mask,off */
1265 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1266 dst_reg, REG_W1, i, off, mask);
1267 break;
1268 branch_ku:
1269 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1270 /* lgfi %w1,imm (load sign extend imm) */
1271 EMIT6_IMM(0xc0010000, REG_W1, imm);
1272 /* clrj or clgrj %dst,%w1,mask,off */
1273 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1274 dst_reg, REG_W1, i, off, mask);
1275 break;
1276 branch_xs:
1277 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1278 /* crj or cgrj %dst,%src,mask,off */
1279 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1280 dst_reg, src_reg, i, off, mask);
1281 break;
1282 branch_xu:
1283 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1284 /* clrj or clgrj %dst,%src,mask,off */
1285 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1286 dst_reg, src_reg, i, off, mask);
1287 break;
1288 branch_oc:
1289 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1290 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1291 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1292 break;
1293 }
1294 default: /* too complex, give up */
1295 pr_err("Unknown opcode %02x\n", insn->code);
1296 return -1;
1297 }
1298 return insn_count;
1299 }
1300
1301 /*
1302 * Compile eBPF program into s390x code
1303 */
bpf_jit_prog(struct bpf_jit * jit,struct bpf_prog * fp,bool extra_pass)1304 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1305 bool extra_pass)
1306 {
1307 int i, insn_count;
1308
1309 jit->lit = jit->lit_start;
1310 jit->prg = 0;
1311
1312 bpf_jit_prologue(jit, fp->aux->stack_depth);
1313 for (i = 0; i < fp->len; i += insn_count) {
1314 insn_count = bpf_jit_insn(jit, fp, i, extra_pass);
1315 if (insn_count < 0)
1316 return -1;
1317 /* Next instruction address */
1318 jit->addrs[i + insn_count] = jit->prg;
1319 }
1320 bpf_jit_epilogue(jit, fp->aux->stack_depth);
1321
1322 jit->lit_start = jit->prg;
1323 jit->size = jit->lit;
1324 jit->size_prg = jit->prg;
1325 return 0;
1326 }
1327
bpf_jit_needs_zext(void)1328 bool bpf_jit_needs_zext(void)
1329 {
1330 return true;
1331 }
1332
1333 struct s390_jit_data {
1334 struct bpf_binary_header *header;
1335 struct bpf_jit ctx;
1336 int pass;
1337 };
1338
1339 /*
1340 * Compile eBPF program "fp"
1341 */
bpf_int_jit_compile(struct bpf_prog * fp)1342 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1343 {
1344 struct bpf_prog *tmp, *orig_fp = fp;
1345 struct bpf_binary_header *header;
1346 struct s390_jit_data *jit_data;
1347 bool tmp_blinded = false;
1348 bool extra_pass = false;
1349 struct bpf_jit jit;
1350 int pass;
1351
1352 if (!fp->jit_requested)
1353 return orig_fp;
1354
1355 tmp = bpf_jit_blind_constants(fp);
1356 /*
1357 * If blinding was requested and we failed during blinding,
1358 * we must fall back to the interpreter.
1359 */
1360 if (IS_ERR(tmp))
1361 return orig_fp;
1362 if (tmp != fp) {
1363 tmp_blinded = true;
1364 fp = tmp;
1365 }
1366
1367 jit_data = fp->aux->jit_data;
1368 if (!jit_data) {
1369 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1370 if (!jit_data) {
1371 fp = orig_fp;
1372 goto out;
1373 }
1374 fp->aux->jit_data = jit_data;
1375 }
1376 if (jit_data->ctx.addrs) {
1377 jit = jit_data->ctx;
1378 header = jit_data->header;
1379 extra_pass = true;
1380 pass = jit_data->pass + 1;
1381 goto skip_init_ctx;
1382 }
1383
1384 memset(&jit, 0, sizeof(jit));
1385 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1386 if (jit.addrs == NULL) {
1387 fp = orig_fp;
1388 goto free_addrs;
1389 }
1390 /*
1391 * Three initial passes:
1392 * - 1/2: Determine clobbered registers
1393 * - 3: Calculate program size and addrs arrray
1394 */
1395 for (pass = 1; pass <= 3; pass++) {
1396 if (bpf_jit_prog(&jit, fp, extra_pass)) {
1397 fp = orig_fp;
1398 goto free_addrs;
1399 }
1400 }
1401 /*
1402 * Final pass: Allocate and generate program
1403 */
1404 if (jit.size >= BPF_SIZE_MAX) {
1405 fp = orig_fp;
1406 goto free_addrs;
1407 }
1408
1409 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1410 if (!header) {
1411 fp = orig_fp;
1412 goto free_addrs;
1413 }
1414 skip_init_ctx:
1415 if (bpf_jit_prog(&jit, fp, extra_pass)) {
1416 bpf_jit_binary_free(header);
1417 fp = orig_fp;
1418 goto free_addrs;
1419 }
1420 if (bpf_jit_enable > 1) {
1421 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1422 print_fn_code(jit.prg_buf, jit.size_prg);
1423 }
1424 if (!fp->is_func || extra_pass) {
1425 bpf_jit_binary_lock_ro(header);
1426 } else {
1427 jit_data->header = header;
1428 jit_data->ctx = jit;
1429 jit_data->pass = pass;
1430 }
1431 fp->bpf_func = (void *) jit.prg_buf;
1432 fp->jited = 1;
1433 fp->jited_len = jit.size;
1434
1435 if (!fp->is_func || extra_pass) {
1436 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1437 free_addrs:
1438 kvfree(jit.addrs);
1439 kfree(jit_data);
1440 fp->aux->jit_data = NULL;
1441 }
1442 out:
1443 if (tmp_blinded)
1444 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1445 tmp : orig_fp);
1446 return fp;
1447 }
1448