1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/perf_event.h>
3 #include <linux/types.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/msr.h>
7 #include <asm/insn.h>
8
9 #include "../perf_event.h"
10
11 enum {
12 LBR_FORMAT_32 = 0x00,
13 LBR_FORMAT_LIP = 0x01,
14 LBR_FORMAT_EIP = 0x02,
15 LBR_FORMAT_EIP_FLAGS = 0x03,
16 LBR_FORMAT_EIP_FLAGS2 = 0x04,
17 LBR_FORMAT_INFO = 0x05,
18 LBR_FORMAT_TIME = 0x06,
19 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
20 };
21
22 static const enum {
23 LBR_EIP_FLAGS = 1,
24 LBR_TSX = 2,
25 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
26 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
27 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
28 };
29
30 /*
31 * Intel LBR_SELECT bits
32 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
33 *
34 * Hardware branch filter (not available on all CPUs)
35 */
36 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
37 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
38 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
39 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
40 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
41 #define LBR_RETURN_BIT 5 /* do not capture near returns */
42 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
43 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
44 #define LBR_FAR_BIT 8 /* do not capture far branches */
45 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
46
47 /*
48 * Following bit only exists in Linux; we mask it out before writing it to
49 * the actual MSR. But it helps the constraint perf code to understand
50 * that this is a separate configuration.
51 */
52 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */
53
54 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
55 #define LBR_USER (1 << LBR_USER_BIT)
56 #define LBR_JCC (1 << LBR_JCC_BIT)
57 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
58 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
59 #define LBR_RETURN (1 << LBR_RETURN_BIT)
60 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
61 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
62 #define LBR_FAR (1 << LBR_FAR_BIT)
63 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
64 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT)
65
66 #define LBR_PLM (LBR_KERNEL | LBR_USER)
67
68 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
69 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
70 #define LBR_IGN 0 /* ignored */
71
72 #define LBR_ANY \
73 (LBR_JCC |\
74 LBR_REL_CALL |\
75 LBR_IND_CALL |\
76 LBR_RETURN |\
77 LBR_REL_JMP |\
78 LBR_IND_JMP |\
79 LBR_FAR)
80
81 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
82 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
83 #define LBR_FROM_FLAG_ABORT BIT_ULL(61)
84
85 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
86
87 /*
88 * x86control flow change classification
89 * x86control flow changes include branches, interrupts, traps, faults
90 */
91 enum {
92 X86_BR_NONE = 0, /* unknown */
93
94 X86_BR_USER = 1 << 0, /* branch target is user */
95 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
96
97 X86_BR_CALL = 1 << 2, /* call */
98 X86_BR_RET = 1 << 3, /* return */
99 X86_BR_SYSCALL = 1 << 4, /* syscall */
100 X86_BR_SYSRET = 1 << 5, /* syscall return */
101 X86_BR_INT = 1 << 6, /* sw interrupt */
102 X86_BR_IRET = 1 << 7, /* return from interrupt */
103 X86_BR_JCC = 1 << 8, /* conditional */
104 X86_BR_JMP = 1 << 9, /* jump */
105 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
106 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
107 X86_BR_ABORT = 1 << 12,/* transaction abort */
108 X86_BR_IN_TX = 1 << 13,/* in transaction */
109 X86_BR_NO_TX = 1 << 14,/* not in transaction */
110 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
111 X86_BR_CALL_STACK = 1 << 16,/* call stack */
112 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
113
114 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
115
116 };
117
118 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
119 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
120
121 #define X86_BR_ANY \
122 (X86_BR_CALL |\
123 X86_BR_RET |\
124 X86_BR_SYSCALL |\
125 X86_BR_SYSRET |\
126 X86_BR_INT |\
127 X86_BR_IRET |\
128 X86_BR_JCC |\
129 X86_BR_JMP |\
130 X86_BR_IRQ |\
131 X86_BR_ABORT |\
132 X86_BR_IND_CALL |\
133 X86_BR_IND_JMP |\
134 X86_BR_ZERO_CALL)
135
136 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
137
138 #define X86_BR_ANY_CALL \
139 (X86_BR_CALL |\
140 X86_BR_IND_CALL |\
141 X86_BR_ZERO_CALL |\
142 X86_BR_SYSCALL |\
143 X86_BR_IRQ |\
144 X86_BR_INT)
145
146 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
147
148 /*
149 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
150 * otherwise it becomes near impossible to get a reliable stack.
151 */
152
__intel_pmu_lbr_enable(bool pmi)153 static void __intel_pmu_lbr_enable(bool pmi)
154 {
155 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
156 u64 debugctl, lbr_select = 0, orig_debugctl;
157
158 /*
159 * No need to unfreeze manually, as v4 can do that as part
160 * of the GLOBAL_STATUS ack.
161 */
162 if (pmi && x86_pmu.version >= 4)
163 return;
164
165 /*
166 * No need to reprogram LBR_SELECT in a PMI, as it
167 * did not change.
168 */
169 if (cpuc->lbr_sel)
170 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
171 if (!pmi && cpuc->lbr_sel)
172 wrmsrl(MSR_LBR_SELECT, lbr_select);
173
174 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
175 orig_debugctl = debugctl;
176 debugctl |= DEBUGCTLMSR_LBR;
177 /*
178 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
179 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
180 * may cause superfluous increase/decrease of LBR_TOS.
181 */
182 if (!(lbr_select & LBR_CALL_STACK))
183 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
184 if (orig_debugctl != debugctl)
185 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
186 }
187
__intel_pmu_lbr_disable(void)188 static void __intel_pmu_lbr_disable(void)
189 {
190 u64 debugctl;
191
192 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
193 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
194 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
195 }
196
intel_pmu_lbr_reset_32(void)197 static void intel_pmu_lbr_reset_32(void)
198 {
199 int i;
200
201 for (i = 0; i < x86_pmu.lbr_nr; i++)
202 wrmsrl(x86_pmu.lbr_from + i, 0);
203 }
204
intel_pmu_lbr_reset_64(void)205 static void intel_pmu_lbr_reset_64(void)
206 {
207 int i;
208
209 for (i = 0; i < x86_pmu.lbr_nr; i++) {
210 wrmsrl(x86_pmu.lbr_from + i, 0);
211 wrmsrl(x86_pmu.lbr_to + i, 0);
212 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
213 wrmsrl(MSR_LBR_INFO_0 + i, 0);
214 }
215 }
216
intel_pmu_lbr_reset(void)217 void intel_pmu_lbr_reset(void)
218 {
219 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
220
221 if (!x86_pmu.lbr_nr)
222 return;
223
224 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
225 intel_pmu_lbr_reset_32();
226 else
227 intel_pmu_lbr_reset_64();
228
229 cpuc->last_task_ctx = NULL;
230 cpuc->last_log_id = 0;
231 }
232
233 /*
234 * TOS = most recently recorded branch
235 */
intel_pmu_lbr_tos(void)236 static inline u64 intel_pmu_lbr_tos(void)
237 {
238 u64 tos;
239
240 rdmsrl(x86_pmu.lbr_tos, tos);
241 return tos;
242 }
243
244 enum {
245 LBR_NONE,
246 LBR_VALID,
247 };
248
249 /*
250 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
251 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
252 * TSX is not supported they have no consistent behavior:
253 *
254 * - For wrmsr(), bits 61:62 are considered part of the sign extension.
255 * - For HW updates (branch captures) bits 61:62 are always OFF and are not
256 * part of the sign extension.
257 *
258 * Therefore, if:
259 *
260 * 1) LBR has TSX format
261 * 2) CPU has no TSX support enabled
262 *
263 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any
264 * value from rdmsr() must be converted to have a 61 bits sign extension,
265 * ignoring the TSX flags.
266 */
lbr_from_signext_quirk_needed(void)267 static inline bool lbr_from_signext_quirk_needed(void)
268 {
269 int lbr_format = x86_pmu.intel_cap.lbr_format;
270 bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
271 boot_cpu_has(X86_FEATURE_RTM);
272
273 return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX);
274 }
275
276 static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
277
278 /* If quirk is enabled, ensure sign extension is 63 bits: */
lbr_from_signext_quirk_wr(u64 val)279 inline u64 lbr_from_signext_quirk_wr(u64 val)
280 {
281 if (static_branch_unlikely(&lbr_from_quirk_key)) {
282 /*
283 * Sign extend into bits 61:62 while preserving bit 63.
284 *
285 * Quirk is enabled when TSX is disabled. Therefore TSX bits
286 * in val are always OFF and must be changed to be sign
287 * extension bits. Since bits 59:60 are guaranteed to be
288 * part of the sign extension bits, we can just copy them
289 * to 61:62.
290 */
291 val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2;
292 }
293 return val;
294 }
295
296 /*
297 * If quirk is needed, ensure sign extension is 61 bits:
298 */
lbr_from_signext_quirk_rd(u64 val)299 static u64 lbr_from_signext_quirk_rd(u64 val)
300 {
301 if (static_branch_unlikely(&lbr_from_quirk_key)) {
302 /*
303 * Quirk is on when TSX is not enabled. Therefore TSX
304 * flags must be read as OFF.
305 */
306 val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT);
307 }
308 return val;
309 }
310
wrlbr_from(unsigned int idx,u64 val)311 static inline void wrlbr_from(unsigned int idx, u64 val)
312 {
313 val = lbr_from_signext_quirk_wr(val);
314 wrmsrl(x86_pmu.lbr_from + idx, val);
315 }
316
wrlbr_to(unsigned int idx,u64 val)317 static inline void wrlbr_to(unsigned int idx, u64 val)
318 {
319 wrmsrl(x86_pmu.lbr_to + idx, val);
320 }
321
rdlbr_from(unsigned int idx)322 static inline u64 rdlbr_from(unsigned int idx)
323 {
324 u64 val;
325
326 rdmsrl(x86_pmu.lbr_from + idx, val);
327
328 return lbr_from_signext_quirk_rd(val);
329 }
330
rdlbr_to(unsigned int idx)331 static inline u64 rdlbr_to(unsigned int idx)
332 {
333 u64 val;
334
335 rdmsrl(x86_pmu.lbr_to + idx, val);
336
337 return val;
338 }
339
__intel_pmu_lbr_restore(struct x86_perf_task_context * task_ctx)340 static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
341 {
342 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
343 int i;
344 unsigned lbr_idx, mask;
345 u64 tos;
346
347 if (task_ctx->lbr_callstack_users == 0 ||
348 task_ctx->lbr_stack_state == LBR_NONE) {
349 intel_pmu_lbr_reset();
350 return;
351 }
352
353 tos = task_ctx->tos;
354 /*
355 * Does not restore the LBR registers, if
356 * - No one else touched them, and
357 * - Did not enter C6
358 */
359 if ((task_ctx == cpuc->last_task_ctx) &&
360 (task_ctx->log_id == cpuc->last_log_id) &&
361 rdlbr_from(tos)) {
362 task_ctx->lbr_stack_state = LBR_NONE;
363 return;
364 }
365
366 mask = x86_pmu.lbr_nr - 1;
367 for (i = 0; i < task_ctx->valid_lbrs; i++) {
368 lbr_idx = (tos - i) & mask;
369 wrlbr_from(lbr_idx, task_ctx->lbr_from[i]);
370 wrlbr_to (lbr_idx, task_ctx->lbr_to[i]);
371
372 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
373 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
374 }
375
376 for (; i < x86_pmu.lbr_nr; i++) {
377 lbr_idx = (tos - i) & mask;
378 wrlbr_from(lbr_idx, 0);
379 wrlbr_to(lbr_idx, 0);
380 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
381 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, 0);
382 }
383
384 wrmsrl(x86_pmu.lbr_tos, tos);
385 task_ctx->lbr_stack_state = LBR_NONE;
386 }
387
__intel_pmu_lbr_save(struct x86_perf_task_context * task_ctx)388 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
389 {
390 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
391 unsigned lbr_idx, mask;
392 u64 tos, from;
393 int i;
394
395 if (task_ctx->lbr_callstack_users == 0) {
396 task_ctx->lbr_stack_state = LBR_NONE;
397 return;
398 }
399
400 mask = x86_pmu.lbr_nr - 1;
401 tos = intel_pmu_lbr_tos();
402 for (i = 0; i < x86_pmu.lbr_nr; i++) {
403 lbr_idx = (tos - i) & mask;
404 from = rdlbr_from(lbr_idx);
405 if (!from)
406 break;
407 task_ctx->lbr_from[i] = from;
408 task_ctx->lbr_to[i] = rdlbr_to(lbr_idx);
409 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
410 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
411 }
412 task_ctx->valid_lbrs = i;
413 task_ctx->tos = tos;
414 task_ctx->lbr_stack_state = LBR_VALID;
415
416 cpuc->last_task_ctx = task_ctx;
417 cpuc->last_log_id = ++task_ctx->log_id;
418 }
419
intel_pmu_lbr_sched_task(struct perf_event_context * ctx,bool sched_in)420 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
421 {
422 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
423 struct x86_perf_task_context *task_ctx;
424
425 if (!cpuc->lbr_users)
426 return;
427
428 /*
429 * If LBR callstack feature is enabled and the stack was saved when
430 * the task was scheduled out, restore the stack. Otherwise flush
431 * the LBR stack.
432 */
433 task_ctx = ctx ? ctx->task_ctx_data : NULL;
434 if (task_ctx) {
435 if (sched_in)
436 __intel_pmu_lbr_restore(task_ctx);
437 else
438 __intel_pmu_lbr_save(task_ctx);
439 return;
440 }
441
442 /*
443 * Since a context switch can flip the address space and LBR entries
444 * are not tagged with an identifier, we need to wipe the LBR, even for
445 * per-cpu events. You simply cannot resolve the branches from the old
446 * address space.
447 */
448 if (sched_in)
449 intel_pmu_lbr_reset();
450 }
451
branch_user_callstack(unsigned br_sel)452 static inline bool branch_user_callstack(unsigned br_sel)
453 {
454 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK);
455 }
456
intel_pmu_lbr_add(struct perf_event * event)457 void intel_pmu_lbr_add(struct perf_event *event)
458 {
459 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
460 struct x86_perf_task_context *task_ctx;
461
462 if (!x86_pmu.lbr_nr)
463 return;
464
465 cpuc->br_sel = event->hw.branch_reg.reg;
466
467 if (branch_user_callstack(cpuc->br_sel) && event->ctx->task_ctx_data) {
468 task_ctx = event->ctx->task_ctx_data;
469 task_ctx->lbr_callstack_users++;
470 }
471
472 /*
473 * Request pmu::sched_task() callback, which will fire inside the
474 * regular perf event scheduling, so that call will:
475 *
476 * - restore or wipe; when LBR-callstack,
477 * - wipe; otherwise,
478 *
479 * when this is from __perf_event_task_sched_in().
480 *
481 * However, if this is from perf_install_in_context(), no such callback
482 * will follow and we'll need to reset the LBR here if this is the
483 * first LBR event.
484 *
485 * The problem is, we cannot tell these cases apart... but we can
486 * exclude the biggest chunk of cases by looking at
487 * event->total_time_running. An event that has accrued runtime cannot
488 * be 'new'. Conversely, a new event can get installed through the
489 * context switch path for the first time.
490 */
491 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
492 cpuc->lbr_pebs_users++;
493 perf_sched_cb_inc(event->ctx->pmu);
494 if (!cpuc->lbr_users++ && !event->total_time_running)
495 intel_pmu_lbr_reset();
496 }
497
intel_pmu_lbr_del(struct perf_event * event)498 void intel_pmu_lbr_del(struct perf_event *event)
499 {
500 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
501 struct x86_perf_task_context *task_ctx;
502
503 if (!x86_pmu.lbr_nr)
504 return;
505
506 if (branch_user_callstack(cpuc->br_sel) &&
507 event->ctx->task_ctx_data) {
508 task_ctx = event->ctx->task_ctx_data;
509 task_ctx->lbr_callstack_users--;
510 }
511
512 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
513 cpuc->lbr_pebs_users--;
514 cpuc->lbr_users--;
515 WARN_ON_ONCE(cpuc->lbr_users < 0);
516 WARN_ON_ONCE(cpuc->lbr_pebs_users < 0);
517 perf_sched_cb_dec(event->ctx->pmu);
518 }
519
intel_pmu_lbr_enable_all(bool pmi)520 void intel_pmu_lbr_enable_all(bool pmi)
521 {
522 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
523
524 if (cpuc->lbr_users)
525 __intel_pmu_lbr_enable(pmi);
526 }
527
intel_pmu_lbr_disable_all(void)528 void intel_pmu_lbr_disable_all(void)
529 {
530 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
531
532 if (cpuc->lbr_users)
533 __intel_pmu_lbr_disable();
534 }
535
intel_pmu_lbr_read_32(struct cpu_hw_events * cpuc)536 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
537 {
538 unsigned long mask = x86_pmu.lbr_nr - 1;
539 u64 tos = intel_pmu_lbr_tos();
540 int i;
541
542 for (i = 0; i < x86_pmu.lbr_nr; i++) {
543 unsigned long lbr_idx = (tos - i) & mask;
544 union {
545 struct {
546 u32 from;
547 u32 to;
548 };
549 u64 lbr;
550 } msr_lastbranch;
551
552 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
553
554 cpuc->lbr_entries[i].from = msr_lastbranch.from;
555 cpuc->lbr_entries[i].to = msr_lastbranch.to;
556 cpuc->lbr_entries[i].mispred = 0;
557 cpuc->lbr_entries[i].predicted = 0;
558 cpuc->lbr_entries[i].in_tx = 0;
559 cpuc->lbr_entries[i].abort = 0;
560 cpuc->lbr_entries[i].cycles = 0;
561 cpuc->lbr_entries[i].type = 0;
562 cpuc->lbr_entries[i].reserved = 0;
563 }
564 cpuc->lbr_stack.nr = i;
565 }
566
567 /*
568 * Due to lack of segmentation in Linux the effective address (offset)
569 * is the same as the linear address, allowing us to merge the LIP and EIP
570 * LBR formats.
571 */
intel_pmu_lbr_read_64(struct cpu_hw_events * cpuc)572 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
573 {
574 bool need_info = false, call_stack = false;
575 unsigned long mask = x86_pmu.lbr_nr - 1;
576 int lbr_format = x86_pmu.intel_cap.lbr_format;
577 u64 tos = intel_pmu_lbr_tos();
578 int i;
579 int out = 0;
580 int num = x86_pmu.lbr_nr;
581
582 if (cpuc->lbr_sel) {
583 need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
584 if (cpuc->lbr_sel->config & LBR_CALL_STACK)
585 call_stack = true;
586 }
587
588 for (i = 0; i < num; i++) {
589 unsigned long lbr_idx = (tos - i) & mask;
590 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
591 int skip = 0;
592 u16 cycles = 0;
593 int lbr_flags = lbr_desc[lbr_format];
594
595 from = rdlbr_from(lbr_idx);
596 to = rdlbr_to(lbr_idx);
597
598 /*
599 * Read LBR call stack entries
600 * until invalid entry (0s) is detected.
601 */
602 if (call_stack && !from)
603 break;
604
605 if (lbr_format == LBR_FORMAT_INFO && need_info) {
606 u64 info;
607
608 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info);
609 mis = !!(info & LBR_INFO_MISPRED);
610 pred = !mis;
611 in_tx = !!(info & LBR_INFO_IN_TX);
612 abort = !!(info & LBR_INFO_ABORT);
613 cycles = (info & LBR_INFO_CYCLES);
614 }
615
616 if (lbr_format == LBR_FORMAT_TIME) {
617 mis = !!(from & LBR_FROM_FLAG_MISPRED);
618 pred = !mis;
619 skip = 1;
620 cycles = ((to >> 48) & LBR_INFO_CYCLES);
621
622 to = (u64)((((s64)to) << 16) >> 16);
623 }
624
625 if (lbr_flags & LBR_EIP_FLAGS) {
626 mis = !!(from & LBR_FROM_FLAG_MISPRED);
627 pred = !mis;
628 skip = 1;
629 }
630 if (lbr_flags & LBR_TSX) {
631 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
632 abort = !!(from & LBR_FROM_FLAG_ABORT);
633 skip = 3;
634 }
635 from = (u64)((((s64)from) << skip) >> skip);
636
637 /*
638 * Some CPUs report duplicated abort records,
639 * with the second entry not having an abort bit set.
640 * Skip them here. This loop runs backwards,
641 * so we need to undo the previous record.
642 * If the abort just happened outside the window
643 * the extra entry cannot be removed.
644 */
645 if (abort && x86_pmu.lbr_double_abort && out > 0)
646 out--;
647
648 cpuc->lbr_entries[out].from = from;
649 cpuc->lbr_entries[out].to = to;
650 cpuc->lbr_entries[out].mispred = mis;
651 cpuc->lbr_entries[out].predicted = pred;
652 cpuc->lbr_entries[out].in_tx = in_tx;
653 cpuc->lbr_entries[out].abort = abort;
654 cpuc->lbr_entries[out].cycles = cycles;
655 cpuc->lbr_entries[out].type = 0;
656 cpuc->lbr_entries[out].reserved = 0;
657 out++;
658 }
659 cpuc->lbr_stack.nr = out;
660 }
661
intel_pmu_lbr_read(void)662 void intel_pmu_lbr_read(void)
663 {
664 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
665
666 /*
667 * Don't read when all LBRs users are using adaptive PEBS.
668 *
669 * This could be smarter and actually check the event,
670 * but this simple approach seems to work for now.
671 */
672 if (!cpuc->lbr_users || cpuc->lbr_users == cpuc->lbr_pebs_users)
673 return;
674
675 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
676 intel_pmu_lbr_read_32(cpuc);
677 else
678 intel_pmu_lbr_read_64(cpuc);
679
680 intel_pmu_lbr_filter(cpuc);
681 }
682
683 /*
684 * SW filter is used:
685 * - in case there is no HW filter
686 * - in case the HW filter has errata or limitations
687 */
intel_pmu_setup_sw_lbr_filter(struct perf_event * event)688 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
689 {
690 u64 br_type = event->attr.branch_sample_type;
691 int mask = 0;
692
693 if (br_type & PERF_SAMPLE_BRANCH_USER)
694 mask |= X86_BR_USER;
695
696 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
697 mask |= X86_BR_KERNEL;
698
699 /* we ignore BRANCH_HV here */
700
701 if (br_type & PERF_SAMPLE_BRANCH_ANY)
702 mask |= X86_BR_ANY;
703
704 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
705 mask |= X86_BR_ANY_CALL;
706
707 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
708 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
709
710 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
711 mask |= X86_BR_IND_CALL;
712
713 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
714 mask |= X86_BR_ABORT;
715
716 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
717 mask |= X86_BR_IN_TX;
718
719 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
720 mask |= X86_BR_NO_TX;
721
722 if (br_type & PERF_SAMPLE_BRANCH_COND)
723 mask |= X86_BR_JCC;
724
725 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) {
726 if (!x86_pmu_has_lbr_callstack())
727 return -EOPNOTSUPP;
728 if (mask & ~(X86_BR_USER | X86_BR_KERNEL))
729 return -EINVAL;
730 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET |
731 X86_BR_CALL_STACK;
732 }
733
734 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP)
735 mask |= X86_BR_IND_JMP;
736
737 if (br_type & PERF_SAMPLE_BRANCH_CALL)
738 mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
739
740 if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE)
741 mask |= X86_BR_TYPE_SAVE;
742
743 /*
744 * stash actual user request into reg, it may
745 * be used by fixup code for some CPU
746 */
747 event->hw.branch_reg.reg = mask;
748 return 0;
749 }
750
751 /*
752 * setup the HW LBR filter
753 * Used only when available, may not be enough to disambiguate
754 * all branches, may need the help of the SW filter
755 */
intel_pmu_setup_hw_lbr_filter(struct perf_event * event)756 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
757 {
758 struct hw_perf_event_extra *reg;
759 u64 br_type = event->attr.branch_sample_type;
760 u64 mask = 0, v;
761 int i;
762
763 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
764 if (!(br_type & (1ULL << i)))
765 continue;
766
767 v = x86_pmu.lbr_sel_map[i];
768 if (v == LBR_NOT_SUPP)
769 return -EOPNOTSUPP;
770
771 if (v != LBR_IGN)
772 mask |= v;
773 }
774
775 reg = &event->hw.branch_reg;
776 reg->idx = EXTRA_REG_LBR;
777
778 /*
779 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
780 * in suppress mode. So LBR_SELECT should be set to
781 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
782 * But the 10th bit LBR_CALL_STACK does not operate
783 * in suppress mode.
784 */
785 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
786
787 if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
788 (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
789 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO))
790 reg->config |= LBR_NO_INFO;
791
792 return 0;
793 }
794
intel_pmu_setup_lbr_filter(struct perf_event * event)795 int intel_pmu_setup_lbr_filter(struct perf_event *event)
796 {
797 int ret = 0;
798
799 /*
800 * no LBR on this PMU
801 */
802 if (!x86_pmu.lbr_nr)
803 return -EOPNOTSUPP;
804
805 /*
806 * setup SW LBR filter
807 */
808 ret = intel_pmu_setup_sw_lbr_filter(event);
809 if (ret)
810 return ret;
811
812 /*
813 * setup HW LBR filter, if any
814 */
815 if (x86_pmu.lbr_sel_map)
816 ret = intel_pmu_setup_hw_lbr_filter(event);
817
818 return ret;
819 }
820
821 /*
822 * return the type of control flow change at address "from"
823 * instruction is not necessarily a branch (in case of interrupt).
824 *
825 * The branch type returned also includes the priv level of the
826 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
827 *
828 * If a branch type is unknown OR the instruction cannot be
829 * decoded (e.g., text page not present), then X86_BR_NONE is
830 * returned.
831 */
branch_type(unsigned long from,unsigned long to,int abort)832 static int branch_type(unsigned long from, unsigned long to, int abort)
833 {
834 struct insn insn;
835 void *addr;
836 int bytes_read, bytes_left;
837 int ret = X86_BR_NONE;
838 int ext, to_plm, from_plm;
839 u8 buf[MAX_INSN_SIZE];
840 int is64 = 0;
841
842 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
843 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
844
845 /*
846 * maybe zero if lbr did not fill up after a reset by the time
847 * we get a PMU interrupt
848 */
849 if (from == 0 || to == 0)
850 return X86_BR_NONE;
851
852 if (abort)
853 return X86_BR_ABORT | to_plm;
854
855 if (from_plm == X86_BR_USER) {
856 /*
857 * can happen if measuring at the user level only
858 * and we interrupt in a kernel thread, e.g., idle.
859 */
860 if (!current->mm)
861 return X86_BR_NONE;
862
863 /* may fail if text not present */
864 bytes_left = copy_from_user_nmi(buf, (void __user *)from,
865 MAX_INSN_SIZE);
866 bytes_read = MAX_INSN_SIZE - bytes_left;
867 if (!bytes_read)
868 return X86_BR_NONE;
869
870 addr = buf;
871 } else {
872 /*
873 * The LBR logs any address in the IP, even if the IP just
874 * faulted. This means userspace can control the from address.
875 * Ensure we don't blindy read any address by validating it is
876 * a known text address.
877 */
878 if (kernel_text_address(from)) {
879 addr = (void *)from;
880 /*
881 * Assume we can get the maximum possible size
882 * when grabbing kernel data. This is not
883 * _strictly_ true since we could possibly be
884 * executing up next to a memory hole, but
885 * it is very unlikely to be a problem.
886 */
887 bytes_read = MAX_INSN_SIZE;
888 } else {
889 return X86_BR_NONE;
890 }
891 }
892
893 /*
894 * decoder needs to know the ABI especially
895 * on 64-bit systems running 32-bit apps
896 */
897 #ifdef CONFIG_X86_64
898 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
899 #endif
900 insn_init(&insn, addr, bytes_read, is64);
901 insn_get_opcode(&insn);
902 if (!insn.opcode.got)
903 return X86_BR_ABORT;
904
905 switch (insn.opcode.bytes[0]) {
906 case 0xf:
907 switch (insn.opcode.bytes[1]) {
908 case 0x05: /* syscall */
909 case 0x34: /* sysenter */
910 ret = X86_BR_SYSCALL;
911 break;
912 case 0x07: /* sysret */
913 case 0x35: /* sysexit */
914 ret = X86_BR_SYSRET;
915 break;
916 case 0x80 ... 0x8f: /* conditional */
917 ret = X86_BR_JCC;
918 break;
919 default:
920 ret = X86_BR_NONE;
921 }
922 break;
923 case 0x70 ... 0x7f: /* conditional */
924 ret = X86_BR_JCC;
925 break;
926 case 0xc2: /* near ret */
927 case 0xc3: /* near ret */
928 case 0xca: /* far ret */
929 case 0xcb: /* far ret */
930 ret = X86_BR_RET;
931 break;
932 case 0xcf: /* iret */
933 ret = X86_BR_IRET;
934 break;
935 case 0xcc ... 0xce: /* int */
936 ret = X86_BR_INT;
937 break;
938 case 0xe8: /* call near rel */
939 insn_get_immediate(&insn);
940 if (insn.immediate1.value == 0) {
941 /* zero length call */
942 ret = X86_BR_ZERO_CALL;
943 break;
944 }
945 /* fall through */
946 case 0x9a: /* call far absolute */
947 ret = X86_BR_CALL;
948 break;
949 case 0xe0 ... 0xe3: /* loop jmp */
950 ret = X86_BR_JCC;
951 break;
952 case 0xe9 ... 0xeb: /* jmp */
953 ret = X86_BR_JMP;
954 break;
955 case 0xff: /* call near absolute, call far absolute ind */
956 insn_get_modrm(&insn);
957 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
958 switch (ext) {
959 case 2: /* near ind call */
960 case 3: /* far ind call */
961 ret = X86_BR_IND_CALL;
962 break;
963 case 4:
964 case 5:
965 ret = X86_BR_IND_JMP;
966 break;
967 }
968 break;
969 default:
970 ret = X86_BR_NONE;
971 }
972 /*
973 * interrupts, traps, faults (and thus ring transition) may
974 * occur on any instructions. Thus, to classify them correctly,
975 * we need to first look at the from and to priv levels. If they
976 * are different and to is in the kernel, then it indicates
977 * a ring transition. If the from instruction is not a ring
978 * transition instr (syscall, systenter, int), then it means
979 * it was a irq, trap or fault.
980 *
981 * we have no way of detecting kernel to kernel faults.
982 */
983 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
984 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
985 ret = X86_BR_IRQ;
986
987 /*
988 * branch priv level determined by target as
989 * is done by HW when LBR_SELECT is implemented
990 */
991 if (ret != X86_BR_NONE)
992 ret |= to_plm;
993
994 return ret;
995 }
996
997 #define X86_BR_TYPE_MAP_MAX 16
998
999 static int branch_map[X86_BR_TYPE_MAP_MAX] = {
1000 PERF_BR_CALL, /* X86_BR_CALL */
1001 PERF_BR_RET, /* X86_BR_RET */
1002 PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
1003 PERF_BR_SYSRET, /* X86_BR_SYSRET */
1004 PERF_BR_UNKNOWN, /* X86_BR_INT */
1005 PERF_BR_UNKNOWN, /* X86_BR_IRET */
1006 PERF_BR_COND, /* X86_BR_JCC */
1007 PERF_BR_UNCOND, /* X86_BR_JMP */
1008 PERF_BR_UNKNOWN, /* X86_BR_IRQ */
1009 PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
1010 PERF_BR_UNKNOWN, /* X86_BR_ABORT */
1011 PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
1012 PERF_BR_UNKNOWN, /* X86_BR_NO_TX */
1013 PERF_BR_CALL, /* X86_BR_ZERO_CALL */
1014 PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */
1015 PERF_BR_IND, /* X86_BR_IND_JMP */
1016 };
1017
1018 static int
common_branch_type(int type)1019 common_branch_type(int type)
1020 {
1021 int i;
1022
1023 type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */
1024
1025 if (type) {
1026 i = __ffs(type);
1027 if (i < X86_BR_TYPE_MAP_MAX)
1028 return branch_map[i];
1029 }
1030
1031 return PERF_BR_UNKNOWN;
1032 }
1033
1034 /*
1035 * implement actual branch filter based on user demand.
1036 * Hardware may not exactly satisfy that request, thus
1037 * we need to inspect opcodes. Mismatched branches are
1038 * discarded. Therefore, the number of branches returned
1039 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
1040 */
1041 static void
intel_pmu_lbr_filter(struct cpu_hw_events * cpuc)1042 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
1043 {
1044 u64 from, to;
1045 int br_sel = cpuc->br_sel;
1046 int i, j, type;
1047 bool compress = false;
1048
1049 /* if sampling all branches, then nothing to filter */
1050 if (((br_sel & X86_BR_ALL) == X86_BR_ALL) &&
1051 ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE))
1052 return;
1053
1054 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
1055
1056 from = cpuc->lbr_entries[i].from;
1057 to = cpuc->lbr_entries[i].to;
1058
1059 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
1060 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
1061 if (cpuc->lbr_entries[i].in_tx)
1062 type |= X86_BR_IN_TX;
1063 else
1064 type |= X86_BR_NO_TX;
1065 }
1066
1067 /* if type does not correspond, then discard */
1068 if (type == X86_BR_NONE || (br_sel & type) != type) {
1069 cpuc->lbr_entries[i].from = 0;
1070 compress = true;
1071 }
1072
1073 if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE)
1074 cpuc->lbr_entries[i].type = common_branch_type(type);
1075 }
1076
1077 if (!compress)
1078 return;
1079
1080 /* remove all entries with from=0 */
1081 for (i = 0; i < cpuc->lbr_stack.nr; ) {
1082 if (!cpuc->lbr_entries[i].from) {
1083 j = i;
1084 while (++j < cpuc->lbr_stack.nr)
1085 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
1086 cpuc->lbr_stack.nr--;
1087 if (!cpuc->lbr_entries[i].from)
1088 continue;
1089 }
1090 i++;
1091 }
1092 }
1093
intel_pmu_store_pebs_lbrs(struct pebs_lbr * lbr)1094 void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr)
1095 {
1096 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1097 int i;
1098
1099 cpuc->lbr_stack.nr = x86_pmu.lbr_nr;
1100 for (i = 0; i < x86_pmu.lbr_nr; i++) {
1101 u64 info = lbr->lbr[i].info;
1102 struct perf_branch_entry *e = &cpuc->lbr_entries[i];
1103
1104 e->from = lbr->lbr[i].from;
1105 e->to = lbr->lbr[i].to;
1106 e->mispred = !!(info & LBR_INFO_MISPRED);
1107 e->predicted = !(info & LBR_INFO_MISPRED);
1108 e->in_tx = !!(info & LBR_INFO_IN_TX);
1109 e->abort = !!(info & LBR_INFO_ABORT);
1110 e->cycles = info & LBR_INFO_CYCLES;
1111 e->reserved = 0;
1112 }
1113 intel_pmu_lbr_filter(cpuc);
1114 }
1115
1116 /*
1117 * Map interface branch filters onto LBR filters
1118 */
1119 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1120 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1121 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1122 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1123 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1124 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP
1125 | LBR_IND_JMP | LBR_FAR,
1126 /*
1127 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
1128 */
1129 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] =
1130 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
1131 /*
1132 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
1133 */
1134 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP,
1135 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1136 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1137 };
1138
1139 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1140 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1141 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1142 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1143 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1144 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1145 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1146 | LBR_FAR,
1147 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1148 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1149 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1150 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1151 };
1152
1153 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1154 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1155 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1156 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1157 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1158 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1159 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1160 | LBR_FAR,
1161 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1162 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1163 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1164 | LBR_RETURN | LBR_CALL_STACK,
1165 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1166 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1167 };
1168
1169 /* core */
intel_pmu_lbr_init_core(void)1170 void __init intel_pmu_lbr_init_core(void)
1171 {
1172 x86_pmu.lbr_nr = 4;
1173 x86_pmu.lbr_tos = MSR_LBR_TOS;
1174 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1175 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1176
1177 /*
1178 * SW branch filter usage:
1179 * - compensate for lack of HW filter
1180 */
1181 }
1182
1183 /* nehalem/westmere */
intel_pmu_lbr_init_nhm(void)1184 void __init intel_pmu_lbr_init_nhm(void)
1185 {
1186 x86_pmu.lbr_nr = 16;
1187 x86_pmu.lbr_tos = MSR_LBR_TOS;
1188 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1189 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1190
1191 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1192 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1193
1194 /*
1195 * SW branch filter usage:
1196 * - workaround LBR_SEL errata (see above)
1197 * - support syscall, sysret capture.
1198 * That requires LBR_FAR but that means far
1199 * jmp need to be filtered out
1200 */
1201 }
1202
1203 /* sandy bridge */
intel_pmu_lbr_init_snb(void)1204 void __init intel_pmu_lbr_init_snb(void)
1205 {
1206 x86_pmu.lbr_nr = 16;
1207 x86_pmu.lbr_tos = MSR_LBR_TOS;
1208 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1209 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1210
1211 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1212 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1213
1214 /*
1215 * SW branch filter usage:
1216 * - support syscall, sysret capture.
1217 * That requires LBR_FAR but that means far
1218 * jmp need to be filtered out
1219 */
1220 }
1221
1222 /* haswell */
intel_pmu_lbr_init_hsw(void)1223 void intel_pmu_lbr_init_hsw(void)
1224 {
1225 x86_pmu.lbr_nr = 16;
1226 x86_pmu.lbr_tos = MSR_LBR_TOS;
1227 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1228 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1229
1230 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1231 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1232
1233 if (lbr_from_signext_quirk_needed())
1234 static_branch_enable(&lbr_from_quirk_key);
1235 }
1236
1237 /* skylake */
intel_pmu_lbr_init_skl(void)1238 __init void intel_pmu_lbr_init_skl(void)
1239 {
1240 x86_pmu.lbr_nr = 32;
1241 x86_pmu.lbr_tos = MSR_LBR_TOS;
1242 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1243 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1244
1245 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1246 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1247
1248 /*
1249 * SW branch filter usage:
1250 * - support syscall, sysret capture.
1251 * That requires LBR_FAR but that means far
1252 * jmp need to be filtered out
1253 */
1254 }
1255
1256 /* atom */
intel_pmu_lbr_init_atom(void)1257 void __init intel_pmu_lbr_init_atom(void)
1258 {
1259 /*
1260 * only models starting at stepping 10 seems
1261 * to have an operational LBR which can freeze
1262 * on PMU interrupt
1263 */
1264 if (boot_cpu_data.x86_model == 28
1265 && boot_cpu_data.x86_stepping < 10) {
1266 pr_cont("LBR disabled due to erratum");
1267 return;
1268 }
1269
1270 x86_pmu.lbr_nr = 8;
1271 x86_pmu.lbr_tos = MSR_LBR_TOS;
1272 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1273 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1274
1275 /*
1276 * SW branch filter usage:
1277 * - compensate for lack of HW filter
1278 */
1279 }
1280
1281 /* slm */
intel_pmu_lbr_init_slm(void)1282 void __init intel_pmu_lbr_init_slm(void)
1283 {
1284 x86_pmu.lbr_nr = 8;
1285 x86_pmu.lbr_tos = MSR_LBR_TOS;
1286 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1287 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1288
1289 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1290 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1291
1292 /*
1293 * SW branch filter usage:
1294 * - compensate for lack of HW filter
1295 */
1296 pr_cont("8-deep LBR, ");
1297 }
1298
1299 /* Knights Landing */
intel_pmu_lbr_init_knl(void)1300 void intel_pmu_lbr_init_knl(void)
1301 {
1302 x86_pmu.lbr_nr = 8;
1303 x86_pmu.lbr_tos = MSR_LBR_TOS;
1304 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1305 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1306
1307 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1308 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1309
1310 /* Knights Landing does have MISPREDICT bit */
1311 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
1312 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;
1313 }
1314